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/dpdk/drivers/common/cnxk/
H A Droc_hash.c40 B = _H[1]; in roc_hash_sha1_gen()
47 temp = ((B & C) | ((~B) & D)) + _K[0]; in roc_hash_sha1_gen()
51 temp = ((B & C) | (B & D) | (C & D)) + _K[2]; in roc_hash_sha1_gen()
59 B = A; in roc_hash_sha1_gen()
64 B += _H[1]; in roc_hash_sha1_gen()
134 temp[2] = (A & B) ^ (A & C) ^ (B & C); in roc_hash_sha256_gen()
142 C = B; in roc_hash_sha256_gen()
143 B = A; in roc_hash_sha256_gen()
246 temp[2] = (A & B) ^ (A & C) ^ (B & C); in roc_hash_sha512_gen()
254 C = B; in roc_hash_sha512_gen()
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/dpdk/doc/guides/sample_app_ug/
H A Dtest_pipeline.rst15 * Core A ("RX core") receives traffic from the NIC ports and feeds core B with traffic through SW…
17 * Core B ("Pipeline core") implements a single-table DPDK pipeline
19 Core B receives traffic from core A through software queues,
23 * Core C ("TX core") receives traffic from core B through software queues and sends it to the NIC…
51 The first CPU core in the core mask is assigned for core A, the second for core B and the third for…
78 …| **#** | **TABLE_TYPE** | **Description of Core B Table** | **Pr…
81 …| 1 | none | Core B is not implementing a DPDK pipeline. | N/A …
82 …| | | Core B is implementing a pass-through from its input set | …
86 …| 2 | stub | Stub table. Core B is implementing the same pass-through | N/A …
228 Regardless of the table type used for the core B pipeline,
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H A Dqos_scheduler.rst76 * --rsz "A, B, C": Ring sizes:
81 * B = Size (in number of elements) of each of the software rings used
87 * --bsz "A, B, C, D": Burst sizes
91 * B = I/O RX lcore write burst size to the output software rings,
100 * --rth "A, B, C": The RX queue threshold parameters
104 * B = RX host threshold (the default value is 8)
108 * --tth "A, B, C": TX queue threshold parameters
112 * B = TX host threshold (the default value is 0)
174 * qavg port X subport Y pipe Z tc A q B: Show average queue size of a specific queue.
H A Dvdpa.rst102 the source host with SW vhost VM and B is the destination host with vDPA.
109 B: <qemu-command-line> -incoming tcp:0:4444 (or other PORT))
115 A: (qemu) migrate -d tcp:<B ip>:4444 (or other PORT)
H A Dip_frag.rst77 Initializing port 0 on lcore 2... Address:00:1B:21:76:FA:2C, rxq=0 txq=2,0 txq=4,1
80 Initializing port 2 on lcore 4... Address:00:1B:21:5C:FF:54, rxq=0 txq=2,0 txq=4,1
H A Dip_reassembly.rst73 Initializing port 0 on lcore 2... Address:00:1B:21:76:FA:2C, rxq=0 txq=2,0 txq=4,1
76 Initializing port 2 on lcore 4... Address:00:1B:21:5C:FF:54, rxq=0 txq=2,0 txq=4,1
/dpdk/devtools/cocci/
H A Dnamespace_ethdev.cocci40 B;
42 coccinelle .B="rte_eth_" + A[4:];
46 identifier p2.B;
49 + struct B
/dpdk/doc/guides/nics/
H A Daf_packet.rst29 * ``framesz`` - PACKET_MMAP frame size (optional, default 2048B; Note: multiple
30 of 16B);
38 As an example, if one changes ``framesz`` to be 1024B, it is expected that
39 ``blocksz`` is set to at least 1024B as well (although 2048B in this case would
62 default options described above (blocksz=4096B, framesz=2048B and
H A Dkni.rst113 Port 0: 1A:4A:5B:7C:A2:8C
130 RX packets 0 bytes 0 (0.0 B)
132 TX packets 0 bytes 0 (0.0 B)
137 RX packets 0 bytes 0 (0.0 B)
139 TX packets 0 bytes 0 (0.0 B)
H A Dark.rst293 * ``1d6c:100d`` - AR-ARKA-FX0 [Arkville 32B DPDK Data Mover]
294 * ``1d6c:100e`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover]
295 * ``1d6c:100f`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for Versal]
296 * ``1d6c:1010`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for Agilex]
297 * ``1d6c:1017`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Primary Endpoint]
298 * ``1d6c:1018`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Secondary Endpoint]
299 * ``1d6c:1019`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Tertiary Endpoint]
300 * ``1d6c:101e`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for Agilex R-Tile]
H A Denic.rst387 64B Completion Queue Entry
390 Recent VIC adapters support 64B completion queue entries, as well as
391 16B entries that are available on all adapter models. ENIC PMD enables
392 and uses 64B entries by default, if available. 64B entries generally
398 If 64B entries are not available, PMD uses 16B entries. The user may
399 explicitly disable 64B entries and use 16B entries by setting
410 PMD: rte_enic_pmd: Using 16B CQ entry size
485 - ``rx_good_bytes`` (ibytes) always includes VLAN header (4B) and CRC bytes (4B).
490 ``rx_good_bytes`` still increments by 4B if the packet is not VLAN tagged or
491 VLAN stripping is disabled, or by 8B if the packet is VLAN tagged and stripping
H A Dliquidio.rst85 ip link set p4p1 vf 0 mac F2:A8:1B:5E:B4:66
128 Port 0: F2:A8:1B:5E:B4:66
H A Daf_xdp.rst92 which is less than the page size (4096B) may be 3072B. In this case, the maximum
/dpdk/examples/l3fwd/
H A Dem_default_v6.cfg13 R2001:0200:0000:000B:0000:0000:0000:0000 2001:0200:0000:000B:0000:0000:0000:0001 9 9 0x11 11
H A Dlpm_default_v6.cfg13 R2001:0200:0000:000B:0000:0000:0000:0000/64 11
/dpdk/doc/guides/cryptodevs/
H A Dmlx5.rst59 - The first credential in plaintext, 40B.
60 - The first import_KEK in plaintext: kek size 0 for 16B or 1 for 32B, kek data.
140 - The supported data-unit lengths are 512B and 4KB and 1MB. In case the `dataunit_len`
/dpdk/doc/guides/faq/
H A Dfaq.rst106 Therefore, each 64B chunk is interleaved across both memory domains.
108 The first 64B chunk is mapped to node 0, the second 64B chunk is mapped to node 1, the third to nod…
109 If you allocated 256B, you would get memory that looks like this:
113 256B buffer
/dpdk/doc/guides/dmadevs/
H A Dhisilicon.rst31 The name of the ``dmadev`` created is like "B:D.F-chX", e.g. DMA 0000:7b:00.0
/dpdk/doc/guides/prog_guide/
H A Dswitch_representation.rst309 .----(A)----. .----(B)----. .----(C)----. | |
331 - **B**: port representor for VF 1.
429 .----(A)----. .----(B)----. .----(C)----. | |
556 .----(A)----. .----(B)----. |
611 - Matches **A**, **B** or **C** in `traffic steering`_.
620 - Targets **A**, **B** or **C** in `traffic steering`_.
733 .----(A)----. .----(B)----. .----(C)----. | |
759 respective representors (**B** and **C**) if supported.
762 are based on port representors **A**, **B** and **C**.
H A Dbbdev.rst560 In CB-mode, CRC24A/B is an optional operation.
562 in 3GPP TS 36.212 section 5.1.2), this size is inclusive of CRC24A/B.
563 The ``length`` is inclusive of CRC24A/B and equals to ``k`` in this case.
565 Not all BBDEV PMDs are capable of CRC24A/B calculation. Flags
663 3GPP TS 36.212 section 5.1.2), this size is inclusive of CRC24A/B.
736 | Set to attach code block CRC-24B |
846 CRC24A/B where present and is equal to the code block size ``K``.
854 Not all BBDEV PMDs may be capable of CRC24A/B calculation. Flags
889 | Set for code block CRC-24B checking |
1040 K (CRC24A/B is the last 24-bit in each decoded CB).
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/dpdk/doc/guides/rel_notes/
H A Drelease_16_11.rst276 - BIOS: SE5C600.86B.02.02.0002.122320131210
281 - BIOS: SE5C600.86B.02.01.0002.082220131453
286 - BIOS: SE5C610.86B.01.01.0009.060120151350
291 - BIOS: SE5C610.86B.01.01.0005.101720141054
296 - BIOS: SE5C610.86B.11.01.0044.090120151156
H A Drelease_16_07.rst369 - BIOS: SE5C600.86B.02.02.0002.122320131210
374 - BIOS: SE5C600.86B.02.01.0002.082220131453
379 - BIOS: SE5C610.86B.01.01.0009.060120151350
384 - BIOS: SE5C610.86B.01.01.0005.101720141054
389 - BIOS: SE5C610.86B.11.01.0044.090120151156
H A Drelease_16_04.rst559 - BIOS: SE5C600.86B.02.02.0002.122320131210
564 - BIOS: SE5C600.86B.02.01.0002.082220131453
569 - BIOS: SE5C610.86B.01.01.0009.060120151350
574 - BIOS: SE5C610.86B.01.01.0005.101720141054
579 - BIOS: SE5C610.86B.11.01.0044.090120151156
/dpdk/examples/ip_pipeline/examples/
H A Drss.cli22 ; | |-------|-|-----+ | | +---|------->| (CORE B) | | TX |
/dpdk/doc/guides/rawdevs/
H A Dntb.rst131 | System A +---------+ | | System B +---------+ |

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