1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ 3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s 4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ 5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s 6declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( 7 <vscale x 1 x half>, 8 half, 9 iXLen); 10 11define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, iXLen %1) nounwind { 12; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu 15; CHECK-NEXT: vfmv.v.f v8, fa0 16; CHECK-NEXT: ret 17entry: 18 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( 19 <vscale x 1 x half> undef, 20 half %0, 21 iXLen %1) 22 23 ret <vscale x 1 x half> %a 24} 25 26declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( 27 <vscale x 2 x half>, 28 half, 29 iXLen); 30 31define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, iXLen %1) nounwind { 32; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: 33; CHECK: # %bb.0: # %entry 34; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu 35; CHECK-NEXT: vfmv.v.f v8, fa0 36; CHECK-NEXT: ret 37entry: 38 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( 39 <vscale x 2 x half> undef, 40 half %0, 41 iXLen %1) 42 43 ret <vscale x 2 x half> %a 44} 45 46declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( 47 <vscale x 4 x half>, 48 half, 49 iXLen); 50 51define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, iXLen %1) nounwind { 52; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: 53; CHECK: # %bb.0: # %entry 54; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu 55; CHECK-NEXT: vfmv.v.f v8, fa0 56; CHECK-NEXT: ret 57entry: 58 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( 59 <vscale x 4 x half> undef, 60 half %0, 61 iXLen %1) 62 63 ret <vscale x 4 x half> %a 64} 65 66declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( 67 <vscale x 8 x half>, 68 half, 69 iXLen); 70 71define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, iXLen %1) nounwind { 72; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu 75; CHECK-NEXT: vfmv.v.f v8, fa0 76; CHECK-NEXT: ret 77entry: 78 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( 79 <vscale x 8 x half> undef, 80 half %0, 81 iXLen %1) 82 83 ret <vscale x 8 x half> %a 84} 85 86declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( 87 <vscale x 16 x half>, 88 half, 89 iXLen); 90 91define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, iXLen %1) nounwind { 92; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: 93; CHECK: # %bb.0: # %entry 94; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu 95; CHECK-NEXT: vfmv.v.f v8, fa0 96; CHECK-NEXT: ret 97entry: 98 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( 99 <vscale x 16 x half> undef, 100 half %0, 101 iXLen %1) 102 103 ret <vscale x 16 x half> %a 104} 105 106declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( 107 <vscale x 32 x half>, 108 half, 109 iXLen); 110 111define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, iXLen %1) nounwind { 112; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: 113; CHECK: # %bb.0: # %entry 114; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu 115; CHECK-NEXT: vfmv.v.f v8, fa0 116; CHECK-NEXT: ret 117entry: 118 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( 119 <vscale x 32 x half> undef, 120 half %0, 121 iXLen %1) 122 123 ret <vscale x 32 x half> %a 124} 125 126declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( 127 <vscale x 1 x float>, 128 float, 129 iXLen); 130 131define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(float %0, iXLen %1) nounwind { 132; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32: 133; CHECK: # %bb.0: # %entry 134; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu 135; CHECK-NEXT: vfmv.v.f v8, fa0 136; CHECK-NEXT: ret 137entry: 138 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( 139 <vscale x 1 x float> undef, 140 float %0, 141 iXLen %1) 142 143 ret <vscale x 1 x float> %a 144} 145 146declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( 147 <vscale x 2 x float>, 148 float, 149 iXLen); 150 151define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32(float %0, iXLen %1) nounwind { 152; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32: 153; CHECK: # %bb.0: # %entry 154; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu 155; CHECK-NEXT: vfmv.v.f v8, fa0 156; CHECK-NEXT: ret 157entry: 158 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( 159 <vscale x 2 x float> undef, 160 float %0, 161 iXLen %1) 162 163 ret <vscale x 2 x float> %a 164} 165 166declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( 167 <vscale x 4 x float>, 168 float, 169 iXLen); 170 171define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32(float %0, iXLen %1) nounwind { 172; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32: 173; CHECK: # %bb.0: # %entry 174; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu 175; CHECK-NEXT: vfmv.v.f v8, fa0 176; CHECK-NEXT: ret 177entry: 178 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( 179 <vscale x 4 x float> undef, 180 float %0, 181 iXLen %1) 182 183 ret <vscale x 4 x float> %a 184} 185 186declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( 187 <vscale x 8 x float>, 188 float, 189 iXLen); 190 191define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32(float %0, iXLen %1) nounwind { 192; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32: 193; CHECK: # %bb.0: # %entry 194; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu 195; CHECK-NEXT: vfmv.v.f v8, fa0 196; CHECK-NEXT: ret 197entry: 198 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( 199 <vscale x 8 x float> undef, 200 float %0, 201 iXLen %1) 202 203 ret <vscale x 8 x float> %a 204} 205 206declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( 207 <vscale x 16 x float>, 208 float, 209 iXLen); 210 211define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32(float %0, iXLen %1) nounwind { 212; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32: 213; CHECK: # %bb.0: # %entry 214; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu 215; CHECK-NEXT: vfmv.v.f v8, fa0 216; CHECK-NEXT: ret 217entry: 218 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( 219 <vscale x 16 x float> undef, 220 float %0, 221 iXLen %1) 222 223 ret <vscale x 16 x float> %a 224} 225 226declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( 227 <vscale x 1 x double>, 228 double, 229 iXLen); 230 231define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64(double %0, iXLen %1) nounwind { 232; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64: 233; CHECK: # %bb.0: # %entry 234; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu 235; CHECK-NEXT: vfmv.v.f v8, fa0 236; CHECK-NEXT: ret 237entry: 238 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( 239 <vscale x 1 x double> undef, 240 double %0, 241 iXLen %1) 242 243 ret <vscale x 1 x double> %a 244} 245 246declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( 247 <vscale x 2 x double>, 248 double, 249 iXLen); 250 251define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64(double %0, iXLen %1) nounwind { 252; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64: 253; CHECK: # %bb.0: # %entry 254; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu 255; CHECK-NEXT: vfmv.v.f v8, fa0 256; CHECK-NEXT: ret 257entry: 258 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( 259 <vscale x 2 x double> undef, 260 double %0, 261 iXLen %1) 262 263 ret <vscale x 2 x double> %a 264} 265 266declare <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( 267 <vscale x 4 x double>, 268 double, 269 iXLen); 270 271define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64(double %0, iXLen %1) nounwind { 272; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64: 273; CHECK: # %bb.0: # %entry 274; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu 275; CHECK-NEXT: vfmv.v.f v8, fa0 276; CHECK-NEXT: ret 277entry: 278 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( 279 <vscale x 4 x double> undef, 280 double %0, 281 iXLen %1) 282 283 ret <vscale x 4 x double> %a 284} 285 286declare <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( 287 <vscale x 8 x double>, 288 double, 289 iXLen); 290 291define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64(double %0, iXLen %1) nounwind { 292; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64: 293; CHECK: # %bb.0: # %entry 294; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu 295; CHECK-NEXT: vfmv.v.f v8, fa0 296; CHECK-NEXT: ret 297entry: 298 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( 299 <vscale x 8 x double> undef, 300 double %0, 301 iXLen %1) 302 303 ret <vscale x 8 x double> %a 304} 305 306define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16(iXLen %0) nounwind { 307; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16: 308; CHECK: # %bb.0: # %entry 309; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu 310; CHECK-NEXT: vmv.v.i v8, 0 311; CHECK-NEXT: ret 312entry: 313 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( 314 <vscale x 1 x half> undef, 315 half 0.0, 316 iXLen %0) 317 318 ret <vscale x 1 x half> %a 319} 320 321define <vscale x 2 x half> @intrinsic_vmv.v.i_zero_nxv2f16(iXLen %0) nounwind { 322; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16: 323; CHECK: # %bb.0: # %entry 324; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu 325; CHECK-NEXT: vmv.v.i v8, 0 326; CHECK-NEXT: ret 327entry: 328 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( 329 <vscale x 2 x half> undef, 330 half 0.0, 331 iXLen %0) 332 333 ret <vscale x 2 x half> %a 334} 335 336define <vscale x 4 x half> @intrinsic_vmv.v.i_zero_nxv4f16(iXLen %0) nounwind { 337; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16: 338; CHECK: # %bb.0: # %entry 339; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu 340; CHECK-NEXT: vmv.v.i v8, 0 341; CHECK-NEXT: ret 342entry: 343 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( 344 <vscale x 4 x half> undef, 345 half 0.0, 346 iXLen %0) 347 348 ret <vscale x 4 x half> %a 349} 350 351define <vscale x 8 x half> @intrinsic_vmv.v.i_zero_nxv8f16(iXLen %0) nounwind { 352; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16: 353; CHECK: # %bb.0: # %entry 354; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu 355; CHECK-NEXT: vmv.v.i v8, 0 356; CHECK-NEXT: ret 357entry: 358 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( 359 <vscale x 8 x half> undef, 360 half 0.0, 361 iXLen %0) 362 363 ret <vscale x 8 x half> %a 364} 365 366define <vscale x 16 x half> @intrinsic_vmv.v.i_zero_nxv16f16(iXLen %0) nounwind { 367; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16: 368; CHECK: # %bb.0: # %entry 369; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu 370; CHECK-NEXT: vmv.v.i v8, 0 371; CHECK-NEXT: ret 372entry: 373 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( 374 <vscale x 16 x half> undef, 375 half 0.0, 376 iXLen %0) 377 378 ret <vscale x 16 x half> %a 379} 380 381define <vscale x 32 x half> @intrinsic_vmv.v.i_zero_nxv32f16(iXLen %0) nounwind { 382; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16: 383; CHECK: # %bb.0: # %entry 384; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu 385; CHECK-NEXT: vmv.v.i v8, 0 386; CHECK-NEXT: ret 387entry: 388 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( 389 <vscale x 32 x half> undef, 390 half 0.0, 391 iXLen %0) 392 393 ret <vscale x 32 x half> %a 394} 395 396define <vscale x 1 x float> @intrinsic_vmv.v.i_zero_nxv1f32(iXLen %0) nounwind { 397; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32: 398; CHECK: # %bb.0: # %entry 399; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu 400; CHECK-NEXT: vmv.v.i v8, 0 401; CHECK-NEXT: ret 402entry: 403 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32( 404 <vscale x 1 x float> undef, 405 float 0.0, 406 iXLen %0) 407 408 ret <vscale x 1 x float> %a 409} 410 411define <vscale x 2 x float> @intrinsic_vmv.v.i_zero_nxv2f32(iXLen %0) nounwind { 412; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32: 413; CHECK: # %bb.0: # %entry 414; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu 415; CHECK-NEXT: vmv.v.i v8, 0 416; CHECK-NEXT: ret 417entry: 418 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32( 419 <vscale x 2 x float> undef, 420 float 0.0, 421 iXLen %0) 422 423 ret <vscale x 2 x float> %a 424} 425 426define <vscale x 4 x float> @intrinsic_vmv.v.i_zero_nxv4f32(iXLen %0) nounwind { 427; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32: 428; CHECK: # %bb.0: # %entry 429; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu 430; CHECK-NEXT: vmv.v.i v8, 0 431; CHECK-NEXT: ret 432entry: 433 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32( 434 <vscale x 4 x float> undef, 435 float 0.0, 436 iXLen %0) 437 438 ret <vscale x 4 x float> %a 439} 440 441define <vscale x 8 x float> @intrinsic_vmv.v.i_zero_nxv8f32(iXLen %0) nounwind { 442; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32: 443; CHECK: # %bb.0: # %entry 444; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu 445; CHECK-NEXT: vmv.v.i v8, 0 446; CHECK-NEXT: ret 447entry: 448 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32( 449 <vscale x 8 x float> undef, 450 float 0.0, 451 iXLen %0) 452 453 ret <vscale x 8 x float> %a 454} 455 456define <vscale x 16 x float> @intrinsic_vmv.v.i_zero_nxv16f32(iXLen %0) nounwind { 457; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32: 458; CHECK: # %bb.0: # %entry 459; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu 460; CHECK-NEXT: vmv.v.i v8, 0 461; CHECK-NEXT: ret 462entry: 463 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32( 464 <vscale x 16 x float> undef, 465 float 0.0, 466 iXLen %0) 467 468 ret <vscale x 16 x float> %a 469} 470 471define <vscale x 1 x double> @intrinsic_vmv.v.i_zero_nxv1f64(iXLen %0) nounwind { 472; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64: 473; CHECK: # %bb.0: # %entry 474; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu 475; CHECK-NEXT: vmv.v.i v8, 0 476; CHECK-NEXT: ret 477entry: 478 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64( 479 <vscale x 1 x double> undef, 480 double 0.0, 481 iXLen %0) 482 483 ret <vscale x 1 x double> %a 484} 485 486define <vscale x 2 x double> @intrinsic_vmv.v.i_zero_nxv2f64(iXLen %0) nounwind { 487; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64: 488; CHECK: # %bb.0: # %entry 489; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu 490; CHECK-NEXT: vmv.v.i v8, 0 491; CHECK-NEXT: ret 492entry: 493 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64( 494 <vscale x 2 x double> undef, 495 double 0.0, 496 iXLen %0) 497 498 ret <vscale x 2 x double> %a 499} 500 501define <vscale x 4 x double> @intrinsic_vmv.v.i_zero_nxv4f64(iXLen %0) nounwind { 502; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64: 503; CHECK: # %bb.0: # %entry 504; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu 505; CHECK-NEXT: vmv.v.i v8, 0 506; CHECK-NEXT: ret 507entry: 508 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64( 509 <vscale x 4 x double> undef, 510 double 0.0, 511 iXLen %0) 512 513 ret <vscale x 4 x double> %a 514} 515 516define <vscale x 8 x double> @intrinsic_vmv.v.i_zero_nxv8f64(iXLen %0) nounwind { 517; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64: 518; CHECK: # %bb.0: # %entry 519; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu 520; CHECK-NEXT: vmv.v.i v8, 0 521; CHECK-NEXT: ret 522entry: 523 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64( 524 <vscale x 8 x double> undef, 525 double 0.0, 526 iXLen %0) 527 528 ret <vscale x 8 x double> %a 529} 530