1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2020 Broadcom 3 * All rights reserved. 4 */ 5 6 7 #ifndef ULP_TEMPLATE_DB_H_ 8 #define ULP_TEMPLATE_DB_H_ 9 10 #define BNXT_ULP_REGFILE_MAX_SZ 15 11 #define BNXT_ULP_MAX_NUM_DEVICES 4 12 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 13 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4 14 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256 15 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4 16 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 17 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 18 #define BNXT_ULP_CLASS_HID_SHFTR 16 19 #define BNXT_ULP_CLASS_HID_SHFTL 23 20 #define BNXT_ULP_CLASS_HID_MASK 255 21 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256 22 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4 23 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 24 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 25 #define BNXT_ULP_ACT_HID_SHFTR 0 26 #define BNXT_ULP_ACT_HID_SHFTL 23 27 #define BNXT_ULP_ACT_HID_MASK 255 28 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 29 #define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2 30 31 enum bnxt_ulp_action_bit { 32 BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001, 33 BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002, 34 BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004, 35 BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008, 36 BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010, 37 BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020, 38 BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040, 39 BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080, 40 BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100, 41 BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200, 42 BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400, 43 BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800, 44 BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000, 45 BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000, 46 BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000, 47 BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000, 48 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000, 49 BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000, 50 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000, 51 BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000, 52 BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000, 53 BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000, 54 BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000, 55 BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000, 56 BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000, 57 BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000, 58 BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000, 59 BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000 60 }; 61 62 enum bnxt_ulp_hdr_bit { 63 BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001, 64 BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002, 65 BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004, 66 BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008, 67 BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010, 68 BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020, 69 BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040, 70 BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080, 71 BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100, 72 BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200, 73 BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400, 74 BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800, 75 BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000 76 }; 77 78 enum bnxt_ulp_act_type { 79 BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0, 80 BNXT_ULP_ACT_TYPE_SUPPORTED = 1, 81 BNXT_ULP_ACT_TYPE_END = 2, 82 BNXT_ULP_ACT_TYPE_LAST = 3 83 }; 84 85 enum bnxt_ulp_byte_order { 86 BNXT_ULP_BYTE_ORDER_BE = 0, 87 BNXT_ULP_BYTE_ORDER_LE = 1, 88 BNXT_ULP_BYTE_ORDER_LAST = 2 89 }; 90 91 enum bnxt_ulp_cf_idx { 92 BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0, 93 BNXT_ULP_CF_IDX_O_VTAG_NUM = 1, 94 BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2, 95 BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3, 96 BNXT_ULP_CF_IDX_I_VTAG_NUM = 4, 97 BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5, 98 BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6, 99 BNXT_ULP_CF_IDX_INCOMING_IF = 7, 100 BNXT_ULP_CF_IDX_DIRECTION = 8, 101 BNXT_ULP_CF_IDX_SVIF_FLAG = 9, 102 BNXT_ULP_CF_IDX_O_L3 = 10, 103 BNXT_ULP_CF_IDX_I_L3 = 11, 104 BNXT_ULP_CF_IDX_O_L4 = 12, 105 BNXT_ULP_CF_IDX_I_L4 = 13, 106 BNXT_ULP_CF_IDX_DEV_PORT_ID = 14, 107 BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15, 108 BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16, 109 BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17, 110 BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18, 111 BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19, 112 BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20, 113 BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21, 114 BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22, 115 BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23, 116 BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24, 117 BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25, 118 BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26, 119 BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27, 120 BNXT_ULP_CF_IDX_LAST = 28 121 }; 122 123 enum bnxt_ulp_critical_resource { 124 BNXT_ULP_CRITICAL_RESOURCE_NO = 0, 125 BNXT_ULP_CRITICAL_RESOURCE_YES = 1, 126 BNXT_ULP_CRITICAL_RESOURCE_LAST = 2 127 }; 128 129 enum bnxt_ulp_device_id { 130 BNXT_ULP_DEVICE_ID_WH_PLUS = 0, 131 BNXT_ULP_DEVICE_ID_THOR = 1, 132 BNXT_ULP_DEVICE_ID_STINGRAY = 2, 133 BNXT_ULP_DEVICE_ID_STINGRAY2 = 3, 134 BNXT_ULP_DEVICE_ID_LAST = 4 135 }; 136 137 enum bnxt_ulp_direction { 138 BNXT_ULP_DIRECTION_INGRESS = 0, 139 BNXT_ULP_DIRECTION_EGRESS = 1, 140 BNXT_ULP_DIRECTION_LAST = 2 141 }; 142 143 enum bnxt_ulp_glb_regfile_index { 144 BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0, 145 BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1 146 }; 147 148 enum bnxt_ulp_hdr_type { 149 BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0, 150 BNXT_ULP_HDR_TYPE_SUPPORTED = 1, 151 BNXT_ULP_HDR_TYPE_END = 2, 152 BNXT_ULP_HDR_TYPE_LAST = 3 153 }; 154 155 enum bnxt_ulp_mark_enable { 156 BNXT_ULP_MARK_ENABLE_NO = 0, 157 BNXT_ULP_MARK_ENABLE_YES = 1, 158 BNXT_ULP_MARK_ENABLE_LAST = 2 159 }; 160 161 enum bnxt_ulp_mask_opc { 162 BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0, 163 BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1, 164 BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2, 165 BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3, 166 BNXT_ULP_MASK_OPC_ADD_PAD = 4, 167 BNXT_ULP_MASK_OPC_LAST = 5 168 }; 169 170 enum bnxt_ulp_match_type { 171 BNXT_ULP_MATCH_TYPE_EM = 0, 172 BNXT_ULP_MATCH_TYPE_WC = 1, 173 BNXT_ULP_MATCH_TYPE_LAST = 2 174 }; 175 176 enum bnxt_ulp_priority { 177 BNXT_ULP_PRIORITY_LEVEL_0 = 0, 178 BNXT_ULP_PRIORITY_LEVEL_1 = 1, 179 BNXT_ULP_PRIORITY_LEVEL_2 = 2, 180 BNXT_ULP_PRIORITY_LEVEL_3 = 3, 181 BNXT_ULP_PRIORITY_LEVEL_4 = 4, 182 BNXT_ULP_PRIORITY_LEVEL_5 = 5, 183 BNXT_ULP_PRIORITY_LEVEL_6 = 6, 184 BNXT_ULP_PRIORITY_LEVEL_7 = 7, 185 BNXT_ULP_PRIORITY_NOT_USED = 8, 186 BNXT_ULP_PRIORITY_LAST = 9 187 }; 188 189 enum bnxt_ulp_regfile_index { 190 BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0, 191 BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1, 192 BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2, 193 BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3, 194 BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4, 195 BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5, 196 BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6, 197 BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7, 198 BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8, 199 BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9, 200 BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10, 201 BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11, 202 BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12, 203 BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13, 204 BNXT_ULP_REGFILE_INDEX_NOT_USED = 14, 205 BNXT_ULP_REGFILE_INDEX_LAST = 15 206 }; 207 208 enum bnxt_ulp_result_opc { 209 BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0, 210 BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1, 211 BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2, 212 BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3, 213 BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4, 214 BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5, 215 BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6, 216 BNXT_ULP_RESULT_OPC_LAST = 7 217 }; 218 219 enum bnxt_ulp_search_before_alloc { 220 BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0, 221 BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1, 222 BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2 223 }; 224 225 enum bnxt_ulp_spec_opc { 226 BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0, 227 BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1, 228 BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2, 229 BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3, 230 BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4, 231 BNXT_ULP_SPEC_OPC_ADD_PAD = 5, 232 BNXT_ULP_SPEC_OPC_LAST = 6 233 }; 234 235 enum bnxt_ulp_vfr_flag { 236 BNXT_ULP_VFR_FLAG_NO = 0, 237 BNXT_ULP_VFR_FLAG_YES = 1, 238 BNXT_ULP_VFR_FLAG_LAST = 2 239 }; 240 241 enum bnxt_ulp_encap_vtag_encoding { 242 BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4, 243 BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5, 244 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6, 245 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7, 246 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8, 247 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9, 248 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10, 249 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11, 250 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12, 251 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13, 252 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14, 253 BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15, 254 BNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0, 255 BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1, 256 BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2, 257 BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3 258 }; 259 260 enum bnxt_ulp_vfr_flag { 261 BNXT_ULP_VFR_FLAG_NO = 0, 262 BNXT_ULP_VFR_FLAG_YES = 1, 263 BNXT_ULP_VFR_FLAG_LAST = 2 264 }; 265 266 enum bnxt_ulp_fdb_resource_flags { 267 BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01, 268 BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00 269 }; 270 271 enum bnxt_ulp_fdb_type { 272 BNXT_ULP_FDB_TYPE_DEFAULT = 1, 273 BNXT_ULP_FDB_TYPE_REGULAR = 0 274 }; 275 276 enum bnxt_ulp_flow_dir_bitmask { 277 BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000, 278 BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000 279 }; 280 281 enum bnxt_ulp_match_type_bitmask { 282 BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000, 283 BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001 284 }; 285 286 enum bnxt_ulp_resource_func { 287 BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, 288 BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20, 289 BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40, 290 BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, 291 BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, 292 BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, 293 BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82, 294 BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83, 295 BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84, 296 BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85 297 }; 298 299 enum bnxt_ulp_resource_sub_type { 300 BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0, 301 BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1, 302 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3, 303 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2, 304 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0, 305 BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1, 306 BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0 307 }; 308 309 enum bnxt_ulp_sym { 310 BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0, 311 BNXT_ULP_SYM_AGG_ERROR_NO = 0, 312 BNXT_ULP_SYM_AGG_ERROR_YES = 1, 313 BNXT_ULP_SYM_BIG_ENDIAN = 0, 314 BNXT_ULP_SYM_DECAP_FUNC_NONE = 0, 315 BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11, 316 BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12, 317 BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13, 318 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3, 319 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8, 320 BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9, 321 BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10, 322 BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0, 323 BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1, 324 BNXT_ULP_SYM_ECV_L2_EN_NO = 0, 325 BNXT_ULP_SYM_ECV_L2_EN_YES = 1, 326 BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4, 327 BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5, 328 BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6, 329 BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7, 330 BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0, 331 BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0, 332 BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4, 333 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5, 334 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, 335 BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, 336 BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1, 337 BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5, 338 BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3, 339 BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0, 340 BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4, 341 BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2, 342 BNXT_ULP_SYM_ECV_VALID_NO = 0, 343 BNXT_ULP_SYM_ECV_VALID_YES = 1, 344 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, 345 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, 346 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, 347 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, 348 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, 349 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, 350 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, 351 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, 352 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, 353 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, 354 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, 355 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, 356 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, 357 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, 358 BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, 359 BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0, 360 BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0, 361 BNXT_ULP_SYM_HREC_NEXT_NO = 0, 362 BNXT_ULP_SYM_HREC_NEXT_YES = 1, 363 BNXT_ULP_SYM_IP_PROTO_ICMP = 1, 364 BNXT_ULP_SYM_IP_PROTO_IGMP = 2, 365 BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4, 366 BNXT_ULP_SYM_IP_PROTO_TCP = 6, 367 BNXT_ULP_SYM_IP_PROTO_UDP = 17, 368 BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0, 369 BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0, 370 BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1, 371 BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0, 372 BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0, 373 BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2, 374 BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1, 375 BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0, 376 BNXT_ULP_SYM_L2_HDR_VALID_NO = 0, 377 BNXT_ULP_SYM_L2_HDR_VALID_YES = 1, 378 BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0, 379 BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0, 380 BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1, 381 BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3, 382 BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0, 383 BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2, 384 BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0, 385 BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0, 386 BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0, 387 BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1, 388 BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0, 389 BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0, 390 BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1, 391 BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0, 392 BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0, 393 BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1, 394 BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2, 395 BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4, 396 BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6, 397 BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0, 398 BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0, 399 BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1, 400 BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3, 401 BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5, 402 BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7, 403 BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8, 404 BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0, 405 BNXT_ULP_SYM_L3_HDR_VALID_NO = 0, 406 BNXT_ULP_SYM_L3_HDR_VALID_YES = 1, 407 BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0, 408 BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0, 409 BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1, 410 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, 411 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0, 412 BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1, 413 BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0, 414 BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0, 415 BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1, 416 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, 417 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, 418 BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, 419 BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5, 420 BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2, 421 BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0, 422 BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0, 423 BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1, 424 BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3, 425 BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4, 426 BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0, 427 BNXT_ULP_SYM_L4_HDR_VALID_NO = 0, 428 BNXT_ULP_SYM_L4_HDR_VALID_YES = 1, 429 BNXT_ULP_SYM_LITTLE_ENDIAN = 1, 430 BNXT_ULP_SYM_MATCH_TYPE_EM = 0, 431 BNXT_ULP_SYM_MATCH_TYPE_WM = 1, 432 BNXT_ULP_SYM_NO = 0, 433 BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0, 434 BNXT_ULP_SYM_PKT_TYPE_L2 = 0, 435 BNXT_ULP_SYM_POP_VLAN_NO = 0, 436 BNXT_ULP_SYM_POP_VLAN_YES = 1, 437 BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0, 438 BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1, 439 BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3, 440 BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2, 441 BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0, 442 BNXT_ULP_SYM_RESERVED_IGNORE = 0, 443 BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3, 444 BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3, 445 BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3, 446 BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0, 447 BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0, 448 BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0, 449 BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0, 450 BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1, 451 BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0, 452 BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0, 453 BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1, 454 BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3, 455 BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0, 456 BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2, 457 BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0, 458 BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0, 459 BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0, 460 BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1, 461 BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0, 462 BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0, 463 BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1, 464 BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0, 465 BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0, 466 BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1, 467 BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0, 468 BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0, 469 BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1, 470 BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0, 471 BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0, 472 BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1, 473 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, 474 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0, 475 BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1, 476 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, 477 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0, 478 BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1, 479 BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0, 480 BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0, 481 BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1, 482 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, 483 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, 484 BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, 485 BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0, 486 BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0, 487 BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1, 488 BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0, 489 BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0, 490 BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1, 491 BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0, 492 BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0, 493 BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1, 494 BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0, 495 BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1, 496 BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3, 497 BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0, 498 BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4, 499 BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5, 500 BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7, 501 BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15, 502 BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2, 503 BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6, 504 BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8, 505 BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9, 506 BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0, 507 BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0, 508 BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0, 509 BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1, 510 BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3, 511 BNXT_ULP_SYM_YES = 1 512 }; 513 514 enum bnxt_ulp_act_prop_sz { 515 BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4, 516 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4, 517 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4, 518 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4, 519 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4, 520 BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4, 521 BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4, 522 BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4, 523 BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4, 524 BNXT_ULP_ACT_PROP_SZ_VNIC = 4, 525 BNXT_ULP_ACT_PROP_SZ_VPORT = 4, 526 BNXT_ULP_ACT_PROP_SZ_MARK = 4, 527 BNXT_ULP_ACT_PROP_SZ_COUNT = 4, 528 BNXT_ULP_ACT_PROP_SZ_METER = 4, 529 BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8, 530 BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8, 531 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4, 532 BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4, 533 BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4, 534 BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4, 535 BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4, 536 BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16, 537 BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16, 538 BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4, 539 BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4, 540 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4, 541 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4, 542 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4, 543 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4, 544 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4, 545 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4, 546 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4, 547 BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4, 548 BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6, 549 BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6, 550 BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8, 551 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32, 552 BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16, 553 BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4, 554 BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, 555 BNXT_ULP_ACT_PROP_SZ_LAST = 4 556 }; 557 558 enum bnxt_ulp_act_prop_idx { 559 BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0, 560 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4, 561 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8, 562 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12, 563 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16, 564 BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20, 565 BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24, 566 BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28, 567 BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32, 568 BNXT_ULP_ACT_PROP_IDX_VNIC = 36, 569 BNXT_ULP_ACT_PROP_IDX_VPORT = 40, 570 BNXT_ULP_ACT_PROP_IDX_MARK = 44, 571 BNXT_ULP_ACT_PROP_IDX_COUNT = 48, 572 BNXT_ULP_ACT_PROP_IDX_METER = 52, 573 BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56, 574 BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64, 575 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72, 576 BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76, 577 BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80, 578 BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84, 579 BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88, 580 BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92, 581 BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108, 582 BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124, 583 BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128, 584 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132, 585 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136, 586 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140, 587 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144, 588 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148, 589 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152, 590 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156, 591 BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160, 592 BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164, 593 BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170, 594 BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176, 595 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184, 596 BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216, 597 BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232, 598 BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236, 599 BNXT_ULP_ACT_PROP_IDX_LAST = 268 600 }; 601 602 enum bnxt_ulp_class_hid { 603 BNXT_ULP_CLASS_HID_0080 = 0x0080, 604 BNXT_ULP_CLASS_HID_0000 = 0x0000, 605 BNXT_ULP_CLASS_HID_0087 = 0x0087 606 }; 607 608 enum bnxt_ulp_act_hid { 609 BNXT_ULP_ACT_HID_00a1 = 0x00a1, 610 BNXT_ULP_ACT_HID_0040 = 0x0040, 611 BNXT_ULP_ACT_HID_0029 = 0x0029 612 }; 613 614 #endif 615