1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_PHY_H_ 6 #define _TXGBE_PHY_H_ 7 8 #include "txgbe_type.h" 9 10 #define TXGBE_SFP_DETECT_RETRIES 10 11 #define TXGBE_MD_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 12 13 14 /* ETH PHY Registers */ 15 #define SR_XS_PCS_MMD_STATUS1 0x030001 16 #define SR_XS_PCS_CTRL2 0x030007 17 #define SR_PCS_CTRL2_TYPE_SEL MS16(0, 0x3) 18 #define SR_PCS_CTRL2_TYPE_SEL_R LS16(0, 0, 0x3) 19 #define SR_PCS_CTRL2_TYPE_SEL_X LS16(1, 0, 0x3) 20 #define SR_PCS_CTRL2_TYPE_SEL_W LS16(2, 0, 0x3) 21 #define SR_PMA_CTRL1 0x010000 22 #define SR_PMA_CTRL1_SS13 MS16(13, 0x1) 23 #define SR_PMA_CTRL1_SS13_KX LS16(0, 13, 0x1) 24 #define SR_PMA_CTRL1_SS13_KX4 LS16(1, 13, 0x1) 25 #define SR_PMA_CTRL1_LB MS16(0, 0x1) 26 #define SR_MII_MMD_CTL 0x1F0000 27 #define SR_MII_MMD_CTL_AN_EN 0x1000 28 #define SR_MII_MMD_CTL_RESTART_AN 0x0200 29 #define SR_MII_MMD_DIGI_CTL 0x1F8000 30 #define SR_MII_MMD_AN_CTL 0x1F8001 31 #define SR_MII_MMD_AN_ADV 0x1F0004 32 #define SR_MII_MMD_AN_ADV_PAUSE(v) ((0x3 & (v)) << 7) 33 #define SR_MII_MMD_AN_ADV_PAUSE_ASM 0x80 34 #define SR_MII_MMD_AN_ADV_PAUSE_SYM 0x100 35 #define SR_MII_MMD_LP_BABL 0x1F0005 36 #define SR_AN_CTRL 0x070000 37 #define SR_AN_CTRL_RSTRT_AN MS16(9, 0x1) 38 #define SR_AN_CTRL_AN_EN MS16(12, 0x1) 39 #define SR_AN_MMD_ADV_REG1 0x070010 40 #define SR_AN_MMD_ADV_REG1_PAUSE(v) ((0x3 & (v)) << 10) 41 #define SR_AN_MMD_ADV_REG1_PAUSE_SYM 0x400 42 #define SR_AN_MMD_ADV_REG1_PAUSE_ASM 0x800 43 #define SR_AN_MMD_ADV_REG2 0x070011 44 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4 0x40 45 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KX 0x20 46 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KR 0x80 47 #define SR_AN_MMD_ADV_REG2_BP_TYPE_MASK 0xFFFF 48 #define SR_AN_MMD_LP_ABL1 0x070013 49 #define VR_AN_KR_MODE_CL 0x078003 50 #define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000 51 #define VR_XS_OR_PCS_MMD_DIGI_CTL1_ENABLE 0x1000 52 #define VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST 0x8000 53 #define VR_XS_OR_PCS_MMD_DIGI_STATUS 0x038010 54 #define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK 0x1C 55 #define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD 0x10 56 57 #define TXGBE_PHY_MPLLA_CTL0 0x018071 58 #define TXGBE_PHY_MPLLA_CTL3 0x018077 59 #define TXGBE_PHY_MISC_CTL0 0x018090 60 #define TXGBE_PHY_VCO_CAL_LD0 0x018092 61 #define TXGBE_PHY_VCO_CAL_LD1 0x018093 62 #define TXGBE_PHY_VCO_CAL_LD2 0x018094 63 #define TXGBE_PHY_VCO_CAL_LD3 0x018095 64 #define TXGBE_PHY_VCO_CAL_REF0 0x018096 65 #define TXGBE_PHY_VCO_CAL_REF1 0x018097 66 #define TXGBE_PHY_RX_AD_ACK 0x018098 67 #define TXGBE_PHY_AFE_DFE_ENABLE 0x01805D 68 #define TXGBE_PHY_DFE_TAP_CTL0 0x01805E 69 #define TXGBE_PHY_RX_EQ_ATT_LVL0 0x018057 70 #define TXGBE_PHY_RX_EQ_CTL0 0x018058 71 #define TXGBE_PHY_RX_EQ_CTL 0x01805C 72 #define TXGBE_PHY_TX_EQ_CTL0 0x018036 73 #define TXGBE_PHY_TX_EQ_CTL1 0x018037 74 #define TXGBE_PHY_TX_RATE_CTL 0x018034 75 #define TXGBE_PHY_RX_RATE_CTL 0x018054 76 #define TXGBE_PHY_TX_GEN_CTL2 0x018032 77 #define TXGBE_PHY_RX_GEN_CTL2 0x018052 78 #define TXGBE_PHY_RX_GEN_CTL3 0x018053 79 #define TXGBE_PHY_MPLLA_CTL2 0x018073 80 #define TXGBE_PHY_RX_POWER_ST_CTL 0x018055 81 #define TXGBE_PHY_TX_POWER_ST_CTL 0x018035 82 #define TXGBE_PHY_TX_GENCTRL1 0x018031 83 84 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX 32 85 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_10GBASER_KR 33 86 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER 40 87 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_MASK 0xFF 88 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX 0x46 89 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR 0x7B 90 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER 0x56 91 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_MASK 0x7FF 92 #define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_0 0x1 93 #define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_3_1 0xE 94 #define TXGBE_PHY_MISC_CTL0_RX_VREF_CTRL 0x1F00 95 #define TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX 1344 96 #define TXGBE_PHY_VCO_CAL_LD0_10GBASER_KR 1353 97 #define TXGBE_PHY_VCO_CAL_LD0_OTHER 1360 98 #define TXGBE_PHY_VCO_CAL_LD0_MASK 0x1000 99 #define TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX 42 100 #define TXGBE_PHY_VCO_CAL_REF0_LD0_10GBASER_KR 41 101 #define TXGBE_PHY_VCO_CAL_REF0_LD0_OTHER 34 102 #define TXGBE_PHY_VCO_CAL_REF0_LD0_MASK 0x3F 103 #define TXGBE_PHY_AFE_DFE_ENABLE_DFE_EN0 0x10 104 #define TXGBE_PHY_AFE_DFE_ENABLE_AFE_EN0 0x1 105 #define TXGBE_PHY_AFE_DFE_ENABLE_MASK 0xFF 106 #define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT0 0x1 107 #define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT_MASK 0xF 108 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_10GBASER_KR 0x0 109 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_RXAUI 0x1 110 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX 0x3 111 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_OTHER 0x2 112 #define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_OTHER 0x20 113 #define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_OTHER 0x200 114 #define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_OTHER 0x2000 115 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_MASK 0x7 116 #define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_MASK 0x70 117 #define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_MASK 0x700 118 #define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_MASK 0x7000 119 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_10GBASER_KR 0x0 120 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_RXAUI 0x1 121 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX 0x3 122 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_OTHER 0x2 123 #define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_OTHER 0x20 124 #define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_OTHER 0x200 125 #define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_OTHER 0x2000 126 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_MASK 0x7 127 #define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_MASK 0x70 128 #define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_MASK 0x700 129 #define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_MASK 0x7000 130 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR 0x200 131 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR_RXAUI 0x300 132 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER 0x100 133 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_MASK 0x300 134 #define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_OTHER 0x400 135 #define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_MASK 0xC00 136 #define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_OTHER 0x1000 137 #define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_MASK 0x3000 138 #define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_OTHER 0x4000 139 #define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_MASK 0xC000 140 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR 0x200 141 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR_RXAUI 0x300 142 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER 0x100 143 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_MASK 0x300 144 #define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_OTHER 0x400 145 #define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_MASK 0xC00 146 #define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_OTHER 0x1000 147 #define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_MASK 0x3000 148 #define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_OTHER 0x4000 149 #define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_MASK 0xC000 150 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_8 0x100 151 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10 0x200 152 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_16P5 0x400 153 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_MASK 0x700 154 155 /****************************************************************************** 156 * SFP I2C Registers: 157 ******************************************************************************/ 158 /* SFP IDs: format of OUI is 0x[byte0][byte1][byte2][00] */ 159 #define TXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 160 #define TXGBE_SFF_VENDOR_OUI_FTL 0x00906500 161 #define TXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 162 #define TXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 163 164 /* EEPROM (dev_addr = 0xA0) */ 165 #define TXGBE_I2C_EEPROM_DEV_ADDR 0xA0 166 #define TXGBE_SFF_IDENTIFIER 0x00 167 #define TXGBE_SFF_IDENTIFIER_SFP 0x03 168 #define TXGBE_SFF_VENDOR_OUI_BYTE0 0x25 169 #define TXGBE_SFF_VENDOR_OUI_BYTE1 0x26 170 #define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27 171 #define TXGBE_SFF_1GBE_COMP_CODES 0x06 172 #define TXGBE_SFF_10GBE_COMP_CODES 0x03 173 #define TXGBE_SFF_CABLE_TECHNOLOGY 0x08 174 #define TXGBE_SFF_CABLE_DA_PASSIVE 0x4 175 #define TXGBE_SFF_CABLE_DA_ACTIVE 0x8 176 #define TXGBE_SFF_CABLE_SPEC_COMP 0x3C 177 #define TXGBE_SFF_SFF_8472_SWAP 0x5C 178 #define TXGBE_SFF_SFF_8472_COMP 0x5E 179 #define TXGBE_SFF_SFF_8472_OSCB 0x6E 180 #define TXGBE_SFF_SFF_8472_ESCB 0x76 181 182 #define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0x0D 183 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 184 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 185 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 186 #define TXGBE_SFF_QSFP_CONNECTOR 0x82 187 #define TXGBE_SFF_QSFP_10GBE_COMP 0x83 188 #define TXGBE_SFF_QSFP_1GBE_COMP 0x86 189 #define TXGBE_SFF_QSFP_CABLE_LENGTH 0x92 190 #define TXGBE_SFF_QSFP_DEVICE_TECH 0x93 191 192 /* Bitmasks */ 193 #define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 194 #define TXGBE_SFF_1GBASESX_CAPABLE 0x1 195 #define TXGBE_SFF_1GBASELX_CAPABLE 0x2 196 #define TXGBE_SFF_1GBASET_CAPABLE 0x8 197 #define TXGBE_SFF_10GBASESR_CAPABLE 0x10 198 #define TXGBE_SFF_10GBASELR_CAPABLE 0x20 199 #define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 200 #define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8 201 #define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0 202 #define TXGBE_SFF_ADDRESSING_MODE 0x4 203 #define TXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 204 #define TXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 205 #define TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 206 #define TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL 0x0 207 #define TXGBE_I2C_EEPROM_READ_MASK 0x100 208 #define TXGBE_I2C_EEPROM_STATUS_MASK 0x3 209 #define TXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 210 #define TXGBE_I2C_EEPROM_STATUS_PASS 0x1 211 #define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2 212 #define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 213 214 /* EEPROM for SFF-8472 (dev_addr = 0xA2) */ 215 #define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 216 217 /* SFP+ SFF-8472 Compliance */ 218 #define TXGBE_SFF_SFF_8472_UNSUP 0x00 219 220 /****************************************************************************** 221 * PHY MDIO Registers: 222 ******************************************************************************/ 223 #define TXGBE_MAX_PHY_ADDR 32 224 /* PHY IDs*/ 225 #define TXGBE_PHYID_MTD3310 0x00000000U 226 #define TXGBE_PHYID_TN1010 0x00A19410U 227 #define TXGBE_PHYID_QT2022 0x0043A400U 228 #define TXGBE_PHYID_ATH 0x03429050U 229 230 /* (dev_type = 1) */ 231 #define TXGBE_MD_DEV_PMA_PMD 0x1 232 #define TXGBE_MD_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 233 #define TXGBE_MD_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 234 #define TXGBE_PHY_REVISION_MASK 0xFFFFFFF0 235 #define TXGBE_MD_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 236 #define TXGBE_MD_PHY_SPEED_10G 0x0001 /* 10G capable */ 237 #define TXGBE_MD_PHY_SPEED_1G 0x0010 /* 1G capable */ 238 #define TXGBE_MD_PHY_SPEED_100M 0x0020 /* 100M capable */ 239 #define TXGBE_MD_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 240 #define TXGBE_MD_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 241 #define TXGBE_MD_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 242 #define TXGBE_MD_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 243 #define TXGBE_MD_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 244 245 #define TXGBE_MD_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 246 #define TXGBE_MD_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 247 #define TXGBE_MD_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 248 #define TXGBE_MD_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 249 250 #define TXGBE_MD_FW_REV_LO 0xC011 251 #define TXGBE_MD_FW_REV_HI 0xC012 252 253 #define TXGBE_TN_LASI_STATUS_REG 0x9005 254 #define TXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 255 256 /* (dev_type = 3) */ 257 #define TXGBE_MD_DEV_PCS 0x3 258 #define TXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */ 259 #define TXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */ 260 #define TXGBE_PCRC8ECH_MASK 0x1F 261 #define TXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */ 262 #define TXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */ 263 264 /* (dev_type = 4) */ 265 #define TXGBE_MD_DEV_PHY_XS 0x4 266 #define TXGBE_MD_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 267 #define TXGBE_MD_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 268 269 /* (dev_type = 7) */ 270 #define TXGBE_MD_DEV_AUTO_NEG 0x7 271 272 #define TXGBE_MD_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 273 #define TXGBE_MD_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 274 #define TXGBE_MD_AUTO_NEG_VENDOR_STAT 0xC800 /*AUTO_NEG Vendor Status Reg*/ 275 #define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ 276 #define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ 277 #define TXGBE_MD_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ 278 #define TXGBE_MD_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 279 #define TXGBE_TAF_SYM_PAUSE MS16(10, 0x3) 280 #define TXGBE_TAF_ASM_PAUSE MS16(11, 0x3) 281 282 #define TXGBE_MD_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 283 #define TXGBE_MD_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 284 /* PHY address definitions for new protocol MDIO commands */ 285 #define TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 286 #define TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 287 #define TXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 288 #define TXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 289 #define TXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 290 #define TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 291 #define TXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 292 #define TXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 293 #define TXGBE_MII_5GBASE_T_ADVERTISE 0x0800 294 #define TXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 295 #define TXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 296 #define TXGBE_MII_RESTART 0x200 297 #define TXGBE_MII_AUTONEG_COMPLETE 0x20 298 #define TXGBE_MII_AUTONEG_LINK_UP 0x04 299 #define TXGBE_MII_AUTONEG_REG 0x0 300 #define TXGBE_MD_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ 301 #define TXGBE_MD_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ 302 #define TXGBE_MD_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ 303 #define TXGBE_MD_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ 304 305 /* (dev_type = 30) */ 306 #define TXGBE_MD_DEV_VENDOR_1 30 307 #define TXGBE_MD_DEV_XFI_DSP 30 308 #define TNX_FW_REV 0xB 309 #define TXGBE_MD_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 310 #define TXGBE_MD_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 311 #define TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 312 #define TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 313 #define TXGBE_MD_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 314 #define TXGBE_MD_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 315 316 /* (dev_type = 31) */ 317 #define TXGBE_MD_DEV_GENERAL 31 318 #define TXGBE_MD_PORT_CTRL 0xF001 319 #define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1) 320 321 /****************************************************************************** 322 * SFP I2C Registers: 323 ******************************************************************************/ 324 #define TXGBE_I2C_SLAVEADDR (0x50) 325 326 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr); 327 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id); 328 s32 txgbe_get_phy_id(struct txgbe_hw *hw); 329 s32 txgbe_identify_phy(struct txgbe_hw *hw); 330 s32 txgbe_reset_phy(struct txgbe_hw *hw); 331 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, 332 u16 *phy_data); 333 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, 334 u16 phy_data); 335 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 336 u32 device_type, u16 *phy_data); 337 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 338 u32 device_type, u16 phy_data); 339 s32 txgbe_setup_phy_link(struct txgbe_hw *hw); 340 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw, 341 u32 speed, 342 bool autoneg_wait_to_complete); 343 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw, 344 u32 *speed, 345 bool *autoneg); 346 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw); 347 348 /* PHY specific */ 349 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, 350 u32 *speed, 351 bool *link_up); 352 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw); 353 354 s32 txgbe_identify_module(struct txgbe_hw *hw); 355 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw); 356 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw); 357 358 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 359 u8 dev_addr, u8 *data); 360 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 361 u8 dev_addr, u8 *data); 362 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 363 u8 dev_addr, u8 data); 364 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 365 u8 dev_addr, u8 data); 366 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset, 367 u8 *sff8472_data); 368 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 369 u8 *eeprom_data); 370 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 371 u8 eeprom_data); 372 u64 txgbe_autoc_read(struct txgbe_hw *hw); 373 void txgbe_autoc_write(struct txgbe_hw *hw, u64 value); 374 375 #endif /* _TXGBE_PHY_H_ */ 376