1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2020 Broadcom 3 * All rights reserved. 4 */ 5 6 #include "ulp_template_db_enum.h" 7 #include "ulp_template_db_field.h" 8 #include "ulp_template_struct.h" 9 #include "ulp_rte_parser.h" 10 11 uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { 12 [BNXT_ULP_ACT_HID_015a] = 1, 13 [BNXT_ULP_ACT_HID_00eb] = 2, 14 [BNXT_ULP_ACT_HID_0043] = 3, 15 [BNXT_ULP_ACT_HID_03d8] = 4, 16 [BNXT_ULP_ACT_HID_02c1] = 5, 17 [BNXT_ULP_ACT_HID_015e] = 6, 18 [BNXT_ULP_ACT_HID_00ef] = 7, 19 [BNXT_ULP_ACT_HID_0047] = 8, 20 [BNXT_ULP_ACT_HID_03dc] = 9, 21 [BNXT_ULP_ACT_HID_02c5] = 10, 22 [BNXT_ULP_ACT_HID_025b] = 11, 23 [BNXT_ULP_ACT_HID_01ec] = 12, 24 [BNXT_ULP_ACT_HID_0144] = 13, 25 [BNXT_ULP_ACT_HID_04d9] = 14, 26 [BNXT_ULP_ACT_HID_03c2] = 15, 27 [BNXT_ULP_ACT_HID_025f] = 16, 28 [BNXT_ULP_ACT_HID_01f0] = 17, 29 [BNXT_ULP_ACT_HID_0148] = 18, 30 [BNXT_ULP_ACT_HID_04dd] = 19, 31 [BNXT_ULP_ACT_HID_03c6] = 20, 32 [BNXT_ULP_ACT_HID_0000] = 21, 33 [BNXT_ULP_ACT_HID_0002] = 22, 34 [BNXT_ULP_ACT_HID_0800] = 23, 35 [BNXT_ULP_ACT_HID_0101] = 24, 36 [BNXT_ULP_ACT_HID_0020] = 25, 37 [BNXT_ULP_ACT_HID_0901] = 26, 38 [BNXT_ULP_ACT_HID_0121] = 27, 39 [BNXT_ULP_ACT_HID_0004] = 28, 40 [BNXT_ULP_ACT_HID_0006] = 29, 41 [BNXT_ULP_ACT_HID_0804] = 30, 42 [BNXT_ULP_ACT_HID_0105] = 31, 43 [BNXT_ULP_ACT_HID_0024] = 32, 44 [BNXT_ULP_ACT_HID_0905] = 33, 45 [BNXT_ULP_ACT_HID_0125] = 34, 46 [BNXT_ULP_ACT_HID_0001] = 35, 47 [BNXT_ULP_ACT_HID_0005] = 36, 48 [BNXT_ULP_ACT_HID_0009] = 37, 49 [BNXT_ULP_ACT_HID_000d] = 38, 50 [BNXT_ULP_ACT_HID_0021] = 39, 51 [BNXT_ULP_ACT_HID_0029] = 40, 52 [BNXT_ULP_ACT_HID_0025] = 41, 53 [BNXT_ULP_ACT_HID_002d] = 42, 54 [BNXT_ULP_ACT_HID_0801] = 43, 55 [BNXT_ULP_ACT_HID_0809] = 44, 56 [BNXT_ULP_ACT_HID_0805] = 45, 57 [BNXT_ULP_ACT_HID_080d] = 46, 58 [BNXT_ULP_ACT_HID_0c15] = 47, 59 [BNXT_ULP_ACT_HID_0c19] = 48, 60 [BNXT_ULP_ACT_HID_02f6] = 49, 61 [BNXT_ULP_ACT_HID_04f8] = 50, 62 [BNXT_ULP_ACT_HID_01df] = 51, 63 [BNXT_ULP_ACT_HID_07e5] = 52, 64 [BNXT_ULP_ACT_HID_06ce] = 53, 65 [BNXT_ULP_ACT_HID_02fa] = 54, 66 [BNXT_ULP_ACT_HID_04fc] = 55, 67 [BNXT_ULP_ACT_HID_01e3] = 56, 68 [BNXT_ULP_ACT_HID_07e9] = 57, 69 [BNXT_ULP_ACT_HID_06d2] = 58, 70 [BNXT_ULP_ACT_HID_03f7] = 59, 71 [BNXT_ULP_ACT_HID_05f9] = 60, 72 [BNXT_ULP_ACT_HID_02e0] = 61, 73 [BNXT_ULP_ACT_HID_08e6] = 62, 74 [BNXT_ULP_ACT_HID_07cf] = 63, 75 [BNXT_ULP_ACT_HID_03fb] = 64, 76 [BNXT_ULP_ACT_HID_05fd] = 65, 77 [BNXT_ULP_ACT_HID_02e4] = 66, 78 [BNXT_ULP_ACT_HID_08ea] = 67, 79 [BNXT_ULP_ACT_HID_07d3] = 68, 80 [BNXT_ULP_ACT_HID_040d] = 69, 81 [BNXT_ULP_ACT_HID_040f] = 70, 82 [BNXT_ULP_ACT_HID_0413] = 71, 83 [BNXT_ULP_ACT_HID_0567] = 72, 84 [BNXT_ULP_ACT_HID_0a49] = 73, 85 [BNXT_ULP_ACT_HID_050e] = 74, 86 [BNXT_ULP_ACT_HID_0668] = 75, 87 [BNXT_ULP_ACT_HID_0b4a] = 76, 88 [BNXT_ULP_ACT_HID_0411] = 77, 89 [BNXT_ULP_ACT_HID_056b] = 78, 90 [BNXT_ULP_ACT_HID_0a4d] = 79, 91 [BNXT_ULP_ACT_HID_0512] = 80, 92 [BNXT_ULP_ACT_HID_066c] = 81, 93 [BNXT_ULP_ACT_HID_0b4e] = 82 94 }; 95 96 struct bnxt_ulp_act_match_info ulp_act_match_list[] = { 97 [1] = { 98 .act_hid = BNXT_ULP_ACT_HID_015a, 99 .act_sig = { .bits = 100 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 101 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 102 .act_tid = 1 103 }, 104 [2] = { 105 .act_hid = BNXT_ULP_ACT_HID_00eb, 106 .act_sig = { .bits = 107 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 108 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 109 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 110 .act_tid = 1 111 }, 112 [3] = { 113 .act_hid = BNXT_ULP_ACT_HID_0043, 114 .act_sig = { .bits = 115 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 116 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 117 .act_tid = 1 118 }, 119 [4] = { 120 .act_hid = BNXT_ULP_ACT_HID_03d8, 121 .act_sig = { .bits = 122 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 123 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 124 BNXT_ULP_ACTION_BIT_SET_TP_DST | 125 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 126 .act_tid = 1 127 }, 128 [5] = { 129 .act_hid = BNXT_ULP_ACT_HID_02c1, 130 .act_sig = { .bits = 131 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 132 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 133 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 134 BNXT_ULP_ACTION_BIT_SET_TP_DST | 135 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 136 .act_tid = 1 137 }, 138 [6] = { 139 .act_hid = BNXT_ULP_ACT_HID_015e, 140 .act_sig = { .bits = 141 BNXT_ULP_ACTION_BIT_COUNT | 142 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 143 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 144 .act_tid = 1 145 }, 146 [7] = { 147 .act_hid = BNXT_ULP_ACT_HID_00ef, 148 .act_sig = { .bits = 149 BNXT_ULP_ACTION_BIT_COUNT | 150 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 151 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 152 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 153 .act_tid = 1 154 }, 155 [8] = { 156 .act_hid = BNXT_ULP_ACT_HID_0047, 157 .act_sig = { .bits = 158 BNXT_ULP_ACTION_BIT_COUNT | 159 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 160 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 161 .act_tid = 1 162 }, 163 [9] = { 164 .act_hid = BNXT_ULP_ACT_HID_03dc, 165 .act_sig = { .bits = 166 BNXT_ULP_ACTION_BIT_COUNT | 167 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 168 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 169 BNXT_ULP_ACTION_BIT_SET_TP_DST | 170 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 171 .act_tid = 1 172 }, 173 [10] = { 174 .act_hid = BNXT_ULP_ACT_HID_02c5, 175 .act_sig = { .bits = 176 BNXT_ULP_ACTION_BIT_COUNT | 177 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 178 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 179 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 180 BNXT_ULP_ACTION_BIT_SET_TP_DST | 181 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 182 .act_tid = 1 183 }, 184 [11] = { 185 .act_hid = BNXT_ULP_ACT_HID_025b, 186 .act_sig = { .bits = 187 BNXT_ULP_ACTION_BIT_DEC_TTL | 188 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 189 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 190 .act_tid = 1 191 }, 192 [12] = { 193 .act_hid = BNXT_ULP_ACT_HID_01ec, 194 .act_sig = { .bits = 195 BNXT_ULP_ACTION_BIT_DEC_TTL | 196 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 197 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 198 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 199 .act_tid = 1 200 }, 201 [13] = { 202 .act_hid = BNXT_ULP_ACT_HID_0144, 203 .act_sig = { .bits = 204 BNXT_ULP_ACTION_BIT_DEC_TTL | 205 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 206 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 207 .act_tid = 1 208 }, 209 [14] = { 210 .act_hid = BNXT_ULP_ACT_HID_04d9, 211 .act_sig = { .bits = 212 BNXT_ULP_ACTION_BIT_DEC_TTL | 213 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 214 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 215 BNXT_ULP_ACTION_BIT_SET_TP_DST | 216 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 217 .act_tid = 1 218 }, 219 [15] = { 220 .act_hid = BNXT_ULP_ACT_HID_03c2, 221 .act_sig = { .bits = 222 BNXT_ULP_ACTION_BIT_DEC_TTL | 223 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 224 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 225 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 226 BNXT_ULP_ACTION_BIT_SET_TP_DST | 227 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 228 .act_tid = 1 229 }, 230 [16] = { 231 .act_hid = BNXT_ULP_ACT_HID_025f, 232 .act_sig = { .bits = 233 BNXT_ULP_ACTION_BIT_DEC_TTL | 234 BNXT_ULP_ACTION_BIT_COUNT | 235 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 236 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 237 .act_tid = 1 238 }, 239 [17] = { 240 .act_hid = BNXT_ULP_ACT_HID_01f0, 241 .act_sig = { .bits = 242 BNXT_ULP_ACTION_BIT_DEC_TTL | 243 BNXT_ULP_ACTION_BIT_COUNT | 244 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 245 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 246 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 247 .act_tid = 1 248 }, 249 [18] = { 250 .act_hid = BNXT_ULP_ACT_HID_0148, 251 .act_sig = { .bits = 252 BNXT_ULP_ACTION_BIT_DEC_TTL | 253 BNXT_ULP_ACTION_BIT_COUNT | 254 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 255 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 256 .act_tid = 1 257 }, 258 [19] = { 259 .act_hid = BNXT_ULP_ACT_HID_04dd, 260 .act_sig = { .bits = 261 BNXT_ULP_ACTION_BIT_DEC_TTL | 262 BNXT_ULP_ACTION_BIT_COUNT | 263 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 264 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 265 BNXT_ULP_ACTION_BIT_SET_TP_DST | 266 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 267 .act_tid = 1 268 }, 269 [20] = { 270 .act_hid = BNXT_ULP_ACT_HID_03c6, 271 .act_sig = { .bits = 272 BNXT_ULP_ACTION_BIT_DEC_TTL | 273 BNXT_ULP_ACTION_BIT_COUNT | 274 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 275 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 276 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 277 BNXT_ULP_ACTION_BIT_SET_TP_DST | 278 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 279 .act_tid = 1 280 }, 281 [21] = { 282 .act_hid = BNXT_ULP_ACT_HID_0000, 283 .act_sig = { .bits = 284 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 285 .act_tid = 2 286 }, 287 [22] = { 288 .act_hid = BNXT_ULP_ACT_HID_0002, 289 .act_sig = { .bits = 290 BNXT_ULP_ACTION_BIT_DROP | 291 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 292 .act_tid = 2 293 }, 294 [23] = { 295 .act_hid = BNXT_ULP_ACT_HID_0800, 296 .act_sig = { .bits = 297 BNXT_ULP_ACTION_BIT_POP_VLAN | 298 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 299 .act_tid = 2 300 }, 301 [24] = { 302 .act_hid = BNXT_ULP_ACT_HID_0101, 303 .act_sig = { .bits = 304 BNXT_ULP_ACTION_BIT_DEC_TTL | 305 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 306 .act_tid = 2 307 }, 308 [25] = { 309 .act_hid = BNXT_ULP_ACT_HID_0020, 310 .act_sig = { .bits = 311 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 312 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 313 .act_tid = 2 314 }, 315 [26] = { 316 .act_hid = BNXT_ULP_ACT_HID_0901, 317 .act_sig = { .bits = 318 BNXT_ULP_ACTION_BIT_DEC_TTL | 319 BNXT_ULP_ACTION_BIT_POP_VLAN | 320 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 321 .act_tid = 2 322 }, 323 [27] = { 324 .act_hid = BNXT_ULP_ACT_HID_0121, 325 .act_sig = { .bits = 326 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 327 BNXT_ULP_ACTION_BIT_DEC_TTL | 328 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 329 .act_tid = 2 330 }, 331 [28] = { 332 .act_hid = BNXT_ULP_ACT_HID_0004, 333 .act_sig = { .bits = 334 BNXT_ULP_ACTION_BIT_COUNT | 335 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 336 .act_tid = 2 337 }, 338 [29] = { 339 .act_hid = BNXT_ULP_ACT_HID_0006, 340 .act_sig = { .bits = 341 BNXT_ULP_ACTION_BIT_COUNT | 342 BNXT_ULP_ACTION_BIT_DROP | 343 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 344 .act_tid = 2 345 }, 346 [30] = { 347 .act_hid = BNXT_ULP_ACT_HID_0804, 348 .act_sig = { .bits = 349 BNXT_ULP_ACTION_BIT_COUNT | 350 BNXT_ULP_ACTION_BIT_POP_VLAN | 351 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 352 .act_tid = 2 353 }, 354 [31] = { 355 .act_hid = BNXT_ULP_ACT_HID_0105, 356 .act_sig = { .bits = 357 BNXT_ULP_ACTION_BIT_COUNT | 358 BNXT_ULP_ACTION_BIT_DEC_TTL | 359 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 360 .act_tid = 2 361 }, 362 [32] = { 363 .act_hid = BNXT_ULP_ACT_HID_0024, 364 .act_sig = { .bits = 365 BNXT_ULP_ACTION_BIT_COUNT | 366 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 367 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 368 .act_tid = 2 369 }, 370 [33] = { 371 .act_hid = BNXT_ULP_ACT_HID_0905, 372 .act_sig = { .bits = 373 BNXT_ULP_ACTION_BIT_COUNT | 374 BNXT_ULP_ACTION_BIT_DEC_TTL | 375 BNXT_ULP_ACTION_BIT_POP_VLAN | 376 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 377 .act_tid = 2 378 }, 379 [34] = { 380 .act_hid = BNXT_ULP_ACT_HID_0125, 381 .act_sig = { .bits = 382 BNXT_ULP_ACTION_BIT_COUNT | 383 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 384 BNXT_ULP_ACTION_BIT_DEC_TTL | 385 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 386 .act_tid = 2 387 }, 388 [35] = { 389 .act_hid = BNXT_ULP_ACT_HID_0001, 390 .act_sig = { .bits = 391 BNXT_ULP_ACTION_BIT_MARK | 392 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 393 .act_tid = 3 394 }, 395 [36] = { 396 .act_hid = BNXT_ULP_ACT_HID_0005, 397 .act_sig = { .bits = 398 BNXT_ULP_ACTION_BIT_MARK | 399 BNXT_ULP_ACTION_BIT_COUNT | 400 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 401 .act_tid = 3 402 }, 403 [37] = { 404 .act_hid = BNXT_ULP_ACT_HID_0009, 405 .act_sig = { .bits = 406 BNXT_ULP_ACTION_BIT_MARK | 407 BNXT_ULP_ACTION_BIT_RSS | 408 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 409 .act_tid = 3 410 }, 411 [38] = { 412 .act_hid = BNXT_ULP_ACT_HID_000d, 413 .act_sig = { .bits = 414 BNXT_ULP_ACTION_BIT_MARK | 415 BNXT_ULP_ACTION_BIT_RSS | 416 BNXT_ULP_ACTION_BIT_COUNT | 417 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 418 .act_tid = 3 419 }, 420 [39] = { 421 .act_hid = BNXT_ULP_ACT_HID_0021, 422 .act_sig = { .bits = 423 BNXT_ULP_ACTION_BIT_MARK | 424 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 425 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 426 .act_tid = 3 427 }, 428 [40] = { 429 .act_hid = BNXT_ULP_ACT_HID_0029, 430 .act_sig = { .bits = 431 BNXT_ULP_ACTION_BIT_MARK | 432 BNXT_ULP_ACTION_BIT_RSS | 433 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 434 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 435 .act_tid = 3 436 }, 437 [41] = { 438 .act_hid = BNXT_ULP_ACT_HID_0025, 439 .act_sig = { .bits = 440 BNXT_ULP_ACTION_BIT_MARK | 441 BNXT_ULP_ACTION_BIT_COUNT | 442 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 443 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 444 .act_tid = 3 445 }, 446 [42] = { 447 .act_hid = BNXT_ULP_ACT_HID_002d, 448 .act_sig = { .bits = 449 BNXT_ULP_ACTION_BIT_MARK | 450 BNXT_ULP_ACTION_BIT_RSS | 451 BNXT_ULP_ACTION_BIT_COUNT | 452 BNXT_ULP_ACTION_BIT_VXLAN_DECAP | 453 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 454 .act_tid = 3 455 }, 456 [43] = { 457 .act_hid = BNXT_ULP_ACT_HID_0801, 458 .act_sig = { .bits = 459 BNXT_ULP_ACTION_BIT_MARK | 460 BNXT_ULP_ACTION_BIT_POP_VLAN | 461 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 462 .act_tid = 3 463 }, 464 [44] = { 465 .act_hid = BNXT_ULP_ACT_HID_0809, 466 .act_sig = { .bits = 467 BNXT_ULP_ACTION_BIT_MARK | 468 BNXT_ULP_ACTION_BIT_RSS | 469 BNXT_ULP_ACTION_BIT_POP_VLAN | 470 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 471 .act_tid = 3 472 }, 473 [45] = { 474 .act_hid = BNXT_ULP_ACT_HID_0805, 475 .act_sig = { .bits = 476 BNXT_ULP_ACTION_BIT_MARK | 477 BNXT_ULP_ACTION_BIT_COUNT | 478 BNXT_ULP_ACTION_BIT_POP_VLAN | 479 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 480 .act_tid = 3 481 }, 482 [46] = { 483 .act_hid = BNXT_ULP_ACT_HID_080d, 484 .act_sig = { .bits = 485 BNXT_ULP_ACTION_BIT_MARK | 486 BNXT_ULP_ACTION_BIT_RSS | 487 BNXT_ULP_ACTION_BIT_COUNT | 488 BNXT_ULP_ACTION_BIT_POP_VLAN | 489 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 490 .act_tid = 3 491 }, 492 [47] = { 493 .act_hid = BNXT_ULP_ACT_HID_0c15, 494 .act_sig = { .bits = 495 BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | 496 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 497 .act_tid = 4 498 }, 499 [48] = { 500 .act_hid = BNXT_ULP_ACT_HID_0c19, 501 .act_sig = { .bits = 502 BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | 503 BNXT_ULP_ACTION_BIT_COUNT | 504 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 505 .act_tid = 4 506 }, 507 [49] = { 508 .act_hid = BNXT_ULP_ACT_HID_02f6, 509 .act_sig = { .bits = 510 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 511 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 512 .act_tid = 5 513 }, 514 [50] = { 515 .act_hid = BNXT_ULP_ACT_HID_04f8, 516 .act_sig = { .bits = 517 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 518 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 519 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 520 .act_tid = 5 521 }, 522 [51] = { 523 .act_hid = BNXT_ULP_ACT_HID_01df, 524 .act_sig = { .bits = 525 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 526 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 527 .act_tid = 5 528 }, 529 [52] = { 530 .act_hid = BNXT_ULP_ACT_HID_07e5, 531 .act_sig = { .bits = 532 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 533 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 534 BNXT_ULP_ACTION_BIT_SET_TP_DST | 535 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 536 .act_tid = 5 537 }, 538 [53] = { 539 .act_hid = BNXT_ULP_ACT_HID_06ce, 540 .act_sig = { .bits = 541 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 542 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 543 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 544 BNXT_ULP_ACTION_BIT_SET_TP_DST | 545 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 546 .act_tid = 5 547 }, 548 [54] = { 549 .act_hid = BNXT_ULP_ACT_HID_02fa, 550 .act_sig = { .bits = 551 BNXT_ULP_ACTION_BIT_COUNT | 552 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 553 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 554 .act_tid = 5 555 }, 556 [55] = { 557 .act_hid = BNXT_ULP_ACT_HID_04fc, 558 .act_sig = { .bits = 559 BNXT_ULP_ACTION_BIT_COUNT | 560 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 561 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 562 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 563 .act_tid = 5 564 }, 565 [56] = { 566 .act_hid = BNXT_ULP_ACT_HID_01e3, 567 .act_sig = { .bits = 568 BNXT_ULP_ACTION_BIT_COUNT | 569 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 570 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 571 .act_tid = 5 572 }, 573 [57] = { 574 .act_hid = BNXT_ULP_ACT_HID_07e9, 575 .act_sig = { .bits = 576 BNXT_ULP_ACTION_BIT_COUNT | 577 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 578 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 579 BNXT_ULP_ACTION_BIT_SET_TP_DST | 580 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 581 .act_tid = 5 582 }, 583 [58] = { 584 .act_hid = BNXT_ULP_ACT_HID_06d2, 585 .act_sig = { .bits = 586 BNXT_ULP_ACTION_BIT_COUNT | 587 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 588 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 589 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 590 BNXT_ULP_ACTION_BIT_SET_TP_DST | 591 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 592 .act_tid = 5 593 }, 594 [59] = { 595 .act_hid = BNXT_ULP_ACT_HID_03f7, 596 .act_sig = { .bits = 597 BNXT_ULP_ACTION_BIT_DEC_TTL | 598 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 599 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 600 .act_tid = 5 601 }, 602 [60] = { 603 .act_hid = BNXT_ULP_ACT_HID_05f9, 604 .act_sig = { .bits = 605 BNXT_ULP_ACTION_BIT_DEC_TTL | 606 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 607 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 608 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 609 .act_tid = 5 610 }, 611 [61] = { 612 .act_hid = BNXT_ULP_ACT_HID_02e0, 613 .act_sig = { .bits = 614 BNXT_ULP_ACTION_BIT_DEC_TTL | 615 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 616 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 617 .act_tid = 5 618 }, 619 [62] = { 620 .act_hid = BNXT_ULP_ACT_HID_08e6, 621 .act_sig = { .bits = 622 BNXT_ULP_ACTION_BIT_DEC_TTL | 623 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 624 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 625 BNXT_ULP_ACTION_BIT_SET_TP_DST | 626 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 627 .act_tid = 5 628 }, 629 [63] = { 630 .act_hid = BNXT_ULP_ACT_HID_07cf, 631 .act_sig = { .bits = 632 BNXT_ULP_ACTION_BIT_DEC_TTL | 633 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 634 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 635 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 636 BNXT_ULP_ACTION_BIT_SET_TP_DST | 637 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 638 .act_tid = 5 639 }, 640 [64] = { 641 .act_hid = BNXT_ULP_ACT_HID_03fb, 642 .act_sig = { .bits = 643 BNXT_ULP_ACTION_BIT_DEC_TTL | 644 BNXT_ULP_ACTION_BIT_COUNT | 645 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 646 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 647 .act_tid = 5 648 }, 649 [65] = { 650 .act_hid = BNXT_ULP_ACT_HID_05fd, 651 .act_sig = { .bits = 652 BNXT_ULP_ACTION_BIT_DEC_TTL | 653 BNXT_ULP_ACTION_BIT_COUNT | 654 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 655 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 656 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 657 .act_tid = 5 658 }, 659 [66] = { 660 .act_hid = BNXT_ULP_ACT_HID_02e4, 661 .act_sig = { .bits = 662 BNXT_ULP_ACTION_BIT_DEC_TTL | 663 BNXT_ULP_ACTION_BIT_COUNT | 664 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 665 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 666 .act_tid = 5 667 }, 668 [67] = { 669 .act_hid = BNXT_ULP_ACT_HID_08ea, 670 .act_sig = { .bits = 671 BNXT_ULP_ACTION_BIT_DEC_TTL | 672 BNXT_ULP_ACTION_BIT_COUNT | 673 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 674 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 675 BNXT_ULP_ACTION_BIT_SET_TP_DST | 676 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 677 .act_tid = 5 678 }, 679 [68] = { 680 .act_hid = BNXT_ULP_ACT_HID_07d3, 681 .act_sig = { .bits = 682 BNXT_ULP_ACTION_BIT_DEC_TTL | 683 BNXT_ULP_ACTION_BIT_COUNT | 684 BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | 685 BNXT_ULP_ACTION_BIT_SET_IPV4_DST | 686 BNXT_ULP_ACTION_BIT_SET_TP_SRC | 687 BNXT_ULP_ACTION_BIT_SET_TP_DST | 688 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 689 .act_tid = 5 690 }, 691 [69] = { 692 .act_hid = BNXT_ULP_ACT_HID_040d, 693 .act_sig = { .bits = 694 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 695 .act_tid = 6 696 }, 697 [70] = { 698 .act_hid = BNXT_ULP_ACT_HID_040f, 699 .act_sig = { .bits = 700 BNXT_ULP_ACTION_BIT_DROP | 701 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 702 .act_tid = 6 703 }, 704 [71] = { 705 .act_hid = BNXT_ULP_ACT_HID_0413, 706 .act_sig = { .bits = 707 BNXT_ULP_ACTION_BIT_DROP | 708 BNXT_ULP_ACTION_BIT_COUNT | 709 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 710 .act_tid = 6 711 }, 712 [72] = { 713 .act_hid = BNXT_ULP_ACT_HID_0567, 714 .act_sig = { .bits = 715 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | 716 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 717 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 718 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 719 .act_tid = 6 720 }, 721 [73] = { 722 .act_hid = BNXT_ULP_ACT_HID_0a49, 723 .act_sig = { .bits = 724 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 725 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 726 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 727 .act_tid = 6 728 }, 729 [74] = { 730 .act_hid = BNXT_ULP_ACT_HID_050e, 731 .act_sig = { .bits = 732 BNXT_ULP_ACTION_BIT_DEC_TTL | 733 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 734 .act_tid = 6 735 }, 736 [75] = { 737 .act_hid = BNXT_ULP_ACT_HID_0668, 738 .act_sig = { .bits = 739 BNXT_ULP_ACTION_BIT_DEC_TTL | 740 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | 741 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 742 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 743 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 744 .act_tid = 6 745 }, 746 [76] = { 747 .act_hid = BNXT_ULP_ACT_HID_0b4a, 748 .act_sig = { .bits = 749 BNXT_ULP_ACTION_BIT_DEC_TTL | 750 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 751 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 752 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 753 .act_tid = 6 754 }, 755 [77] = { 756 .act_hid = BNXT_ULP_ACT_HID_0411, 757 .act_sig = { .bits = 758 BNXT_ULP_ACTION_BIT_COUNT | 759 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 760 .act_tid = 6 761 }, 762 [78] = { 763 .act_hid = BNXT_ULP_ACT_HID_056b, 764 .act_sig = { .bits = 765 BNXT_ULP_ACTION_BIT_COUNT | 766 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | 767 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 768 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 769 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 770 .act_tid = 6 771 }, 772 [79] = { 773 .act_hid = BNXT_ULP_ACT_HID_0a4d, 774 .act_sig = { .bits = 775 BNXT_ULP_ACTION_BIT_COUNT | 776 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 777 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 778 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 779 .act_tid = 6 780 }, 781 [80] = { 782 .act_hid = BNXT_ULP_ACT_HID_0512, 783 .act_sig = { .bits = 784 BNXT_ULP_ACTION_BIT_COUNT | 785 BNXT_ULP_ACTION_BIT_DEC_TTL | 786 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 787 .act_tid = 6 788 }, 789 [81] = { 790 .act_hid = BNXT_ULP_ACT_HID_066c, 791 .act_sig = { .bits = 792 BNXT_ULP_ACTION_BIT_COUNT | 793 BNXT_ULP_ACTION_BIT_DEC_TTL | 794 BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | 795 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 796 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 797 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 798 .act_tid = 6 799 }, 800 [82] = { 801 .act_hid = BNXT_ULP_ACT_HID_0b4e, 802 .act_sig = { .bits = 803 BNXT_ULP_ACTION_BIT_COUNT | 804 BNXT_ULP_ACTION_BIT_DEC_TTL | 805 BNXT_ULP_ACTION_BIT_SET_VLAN_VID | 806 BNXT_ULP_ACTION_BIT_PUSH_VLAN | 807 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 808 .act_tid = 6 809 } 810 }; 811