1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _TF_DEVICE_P4_H_ 7 #define _TF_DEVICE_P4_H_ 8 9 #include "cfa_resource_types.h" 10 #include "tf_core.h" 11 #include "tf_rm.h" 12 #include "tf_if_tbl.h" 13 #include "tf_global_cfg.h" 14 15 extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; 16 17 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { 18 [TF_IDENT_TYPE_L2_CTXT_HIGH] = { 19 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, 20 0, 0 21 }, 22 [TF_IDENT_TYPE_L2_CTXT_LOW] = { 23 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW, 24 0, 0 25 }, 26 [TF_IDENT_TYPE_PROF_FUNC] = { 27 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC, 28 0, 0 29 }, 30 [TF_IDENT_TYPE_WC_PROF] = { 31 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID, 32 0, 0 33 }, 34 [TF_IDENT_TYPE_EM_PROF] = { 35 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID, 36 0, 0 37 }, 38 }; 39 40 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { 41 [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { 42 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, 43 0, 0 44 }, 45 [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { 46 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, 47 0, 0 48 }, 49 [TF_TCAM_TBL_TYPE_PROF_TCAM] = { 50 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM, 51 0, 0 52 }, 53 [TF_TCAM_TBL_TYPE_WC_TCAM] = { 54 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM, 55 0, 0 56 }, 57 [TF_TCAM_TBL_TYPE_SP_TCAM] = { 58 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM, 59 0, 0 60 }, 61 }; 62 63 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { 64 [TF_EM_TBL_TYPE_TBL_SCOPE] = { 65 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, 66 0, 0 67 }, 68 }; 69 70 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { 71 [TF_EM_TBL_TYPE_EM_RECORD] = { 72 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC, 73 0, 0 74 }, 75 }; 76 77 /* Note that hcapi_types from this table are from hcapi_cfa_p4.h 78 * These are not CFA resource types because they are not allocated 79 * CFA resources - they are identifiers for the interface tables 80 * shared between the firmware and the host. It may make sense to 81 * move these types to cfa_resource_types.h. 82 */ 83 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = { 84 [TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = { 85 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT 86 }, 87 [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = { 88 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR 89 }, 90 [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = { 91 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR 92 }, 93 [TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = { 94 TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR 95 }, 96 }; 97 98 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { 99 [TF_TUNNEL_ENCAP] = { 100 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP 101 }, 102 [TF_ACTION_BLOCK] = { 103 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK 104 }, 105 }; 106 107 const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { 108 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { 109 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH 110 }, 111 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { 112 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW 113 }, 114 [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { 115 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC 116 }, 117 [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { 118 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF 119 }, 120 [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { 121 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF 122 }, 123 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { 124 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH 125 }, 126 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { 127 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW 128 }, 129 [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { 130 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM 131 }, 132 [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { 133 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM 134 }, 135 [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { 136 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM 137 }, 138 [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { 139 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 140 }, 141 [CFA_RESOURCE_TYPE_P4_METER_PROF] = { 142 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF 143 }, 144 [CFA_RESOURCE_TYPE_P4_METER] = { 145 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST 146 }, 147 [CFA_RESOURCE_TYPE_P4_MIRROR] = { 148 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG 149 }, 150 [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { 151 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD 152 }, 153 [CFA_RESOURCE_TYPE_P4_MCG] = { 154 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS 155 }, 156 [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { 157 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B 158 }, 159 [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { 160 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B 161 }, 162 [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { 163 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B 164 }, 165 [CFA_RESOURCE_TYPE_P4_SP_MAC] = { 166 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC 167 }, 168 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { 169 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 170 }, 171 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { 172 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 173 }, 174 [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { 175 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 176 }, 177 [CFA_RESOURCE_TYPE_P4_EM_REC] = { 178 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD 179 }, 180 [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { 181 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE 182 }, 183 }; 184 185 #endif /* _TF_DEVICE_P4_H_ */ 186