1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
3 */
4
5 #ifndef _RTE_CRC_X86_H_
6 #define _RTE_CRC_X86_H_
7
8 static inline uint32_t
crc32c_sse42_u8(uint8_t data,uint32_t init_val)9 crc32c_sse42_u8(uint8_t data, uint32_t init_val)
10 {
11 __asm__ volatile(
12 "crc32b %[data], %[init_val];"
13 : [init_val] "+r" (init_val)
14 : [data] "rm" (data));
15 return init_val;
16 }
17
18 static inline uint32_t
crc32c_sse42_u16(uint16_t data,uint32_t init_val)19 crc32c_sse42_u16(uint16_t data, uint32_t init_val)
20 {
21 __asm__ volatile(
22 "crc32w %[data], %[init_val];"
23 : [init_val] "+r" (init_val)
24 : [data] "rm" (data));
25 return init_val;
26 }
27
28 static inline uint32_t
crc32c_sse42_u32(uint32_t data,uint32_t init_val)29 crc32c_sse42_u32(uint32_t data, uint32_t init_val)
30 {
31 __asm__ volatile(
32 "crc32l %[data], %[init_val];"
33 : [init_val] "+r" (init_val)
34 : [data] "rm" (data));
35 return init_val;
36 }
37
38 static inline uint32_t
crc32c_sse42_u64_mimic(uint64_t data,uint64_t init_val)39 crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
40 {
41 union {
42 uint32_t u32[2];
43 uint64_t u64;
44 } d;
45
46 d.u64 = data;
47 init_val = crc32c_sse42_u32(d.u32[0], (uint32_t)init_val);
48 init_val = crc32c_sse42_u32(d.u32[1], (uint32_t)init_val);
49 return (uint32_t)init_val;
50 }
51
52 static inline uint32_t
crc32c_sse42_u64(uint64_t data,uint64_t init_val)53 crc32c_sse42_u64(uint64_t data, uint64_t init_val)
54 {
55 __asm__ volatile(
56 "crc32q %[data], %[init_val];"
57 : [init_val] "+r" (init_val)
58 : [data] "rm" (data));
59 return (uint32_t)init_val;
60 }
61
62 /*
63 * Use single crc32 instruction to perform a hash on a byte value.
64 * Fall back to software crc32 implementation in case SSE4.2 is
65 * not supported.
66 */
67 static inline uint32_t
rte_hash_crc_1byte(uint8_t data,uint32_t init_val)68 rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
69 {
70 if (likely(crc32_alg & CRC32_SSE42))
71 return crc32c_sse42_u8(data, init_val);
72
73 return crc32c_1byte(data, init_val);
74 }
75
76 /*
77 * Use single crc32 instruction to perform a hash on a 2 bytes value.
78 * Fall back to software crc32 implementation in case SSE4.2 is
79 * not supported.
80 */
81 static inline uint32_t
rte_hash_crc_2byte(uint16_t data,uint32_t init_val)82 rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
83 {
84 if (likely(crc32_alg & CRC32_SSE42))
85 return crc32c_sse42_u16(data, init_val);
86
87 return crc32c_2bytes(data, init_val);
88 }
89
90 /*
91 * Use single crc32 instruction to perform a hash on a 4 byte value.
92 * Fall back to software crc32 implementation in case SSE4.2 is
93 * not supported.
94 */
95 static inline uint32_t
rte_hash_crc_4byte(uint32_t data,uint32_t init_val)96 rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
97 {
98 if (likely(crc32_alg & CRC32_SSE42))
99 return crc32c_sse42_u32(data, init_val);
100
101 return crc32c_1word(data, init_val);
102 }
103
104 /*
105 * Use single crc32 instruction to perform a hash on a 8 byte value.
106 * Fall back to software crc32 implementation in case SSE4.2 is
107 * not supported.
108 */
109 static inline uint32_t
rte_hash_crc_8byte(uint64_t data,uint32_t init_val)110 rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
111 {
112 #ifdef RTE_ARCH_X86_64
113 if (likely(crc32_alg == CRC32_SSE42_x64))
114 return crc32c_sse42_u64(data, init_val);
115 #endif
116
117 if (likely(crc32_alg & CRC32_SSE42))
118 return crc32c_sse42_u64_mimic(data, init_val);
119
120 return crc32c_2words(data, init_val);
121 }
122
123 #endif /* _RTE_CRC_X86_H_ */
124