1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 *
3 * Copyright 2008-2016 Freescale Semiconductor Inc.
4 * Copyright 2016,2019 NXP
5 */
6
7 #ifndef __RTA_NFIFO_CMD_H__
8 #define __RTA_NFIFO_CMD_H__
9
10 extern enum rta_sec_era rta_sec_era;
11
12 static const uint32_t nfifo_src[][2] = {
13 /*1*/ { IFIFO, NFIFOENTRY_STYPE_DFIFO },
14 { OFIFO, NFIFOENTRY_STYPE_OFIFO },
15 { PAD, NFIFOENTRY_STYPE_PAD },
16 /*4*/ { MSGOUTSNOOP, NFIFOENTRY_STYPE_SNOOP | NFIFOENTRY_DEST_BOTH },
17 /*5*/ { ALTSOURCE, NFIFOENTRY_STYPE_ALTSOURCE },
18 { OFIFO_SYNC, NFIFOENTRY_STYPE_OFIFO_SYNC },
19 /*7*/ { MSGOUTSNOOP_ALT, NFIFOENTRY_STYPE_SNOOP_ALT | NFIFOENTRY_DEST_BOTH }
20 };
21
22 /*
23 * Allowed NFIFO LOAD sources for each SEC Era.
24 * Values represent the number of entries from nfifo_src[] that are supported.
25 */
26 static const unsigned int nfifo_src_sz[] = {4, 5, 5, 5, 5, 5, 5, 7, 7, 7};
27
28 static const uint32_t nfifo_data[][2] = {
29 { MSG, NFIFOENTRY_DTYPE_MSG },
30 { MSG1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_MSG },
31 { MSG2, NFIFOENTRY_DEST_CLASS2 | NFIFOENTRY_DTYPE_MSG },
32 { IV1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_IV },
33 { IV2, NFIFOENTRY_DEST_CLASS2 | NFIFOENTRY_DTYPE_IV },
34 { ICV1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_ICV },
35 { ICV2, NFIFOENTRY_DEST_CLASS2 | NFIFOENTRY_DTYPE_ICV },
36 { SAD1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_SAD },
37 { AAD1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_AAD },
38 { AAD2, NFIFOENTRY_DEST_CLASS2 | NFIFOENTRY_DTYPE_AAD },
39 { AFHA_SBOX, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_SBOX },
40 { SKIP, NFIFOENTRY_DTYPE_SKIP },
41 { PKE, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_E },
42 { PKN, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_N },
43 { PKA, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_A },
44 { PKA0, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_A0 },
45 { PKA1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_A1 },
46 { PKA2, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_A2 },
47 { PKA3, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_A3 },
48 { PKB, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_B },
49 { PKB0, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_B0 },
50 { PKB1, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_B1 },
51 { PKB2, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_B2 },
52 { PKB3, NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_DTYPE_PK_B3 },
53 { AB1, NFIFOENTRY_DEST_CLASS1 },
54 { AB2, NFIFOENTRY_DEST_CLASS2 },
55 { ABD, NFIFOENTRY_DEST_DECO }
56 };
57
58 static const uint32_t nfifo_flags[][2] = {
59 /*1*/ { LAST1, NFIFOENTRY_LC1 },
60 { LAST2, NFIFOENTRY_LC2 },
61 { FLUSH1, NFIFOENTRY_FC1 },
62 { BP, NFIFOENTRY_BND },
63 { PAD_ZERO, NFIFOENTRY_PTYPE_ZEROS },
64 { PAD_NONZERO, NFIFOENTRY_PTYPE_RND_NOZEROS },
65 { PAD_INCREMENT, NFIFOENTRY_PTYPE_INCREMENT },
66 { PAD_RANDOM, NFIFOENTRY_PTYPE_RND },
67 { PAD_ZERO_N1, NFIFOENTRY_PTYPE_ZEROS_NZ },
68 { PAD_NONZERO_0, NFIFOENTRY_PTYPE_RND_NZ_LZ },
69 { PAD_N1, NFIFOENTRY_PTYPE_N },
70 /*12*/ { PAD_NONZERO_N, NFIFOENTRY_PTYPE_RND_NZ_N },
71 { FLUSH2, NFIFOENTRY_FC2 },
72 { OC, NFIFOENTRY_OC }
73 };
74
75 /*
76 * Allowed NFIFO LOAD flags for each SEC Era.
77 * Values represent the number of entries from nfifo_flags[] that are supported.
78 */
79 static const unsigned int nfifo_flags_sz[] = {12, 14, 14, 14, 14, 14,
80 14, 14, 14, 14};
81
82 static const uint32_t nfifo_pad_flags[][2] = {
83 { BM, NFIFOENTRY_BM },
84 { PS, NFIFOENTRY_PS },
85 { PR, NFIFOENTRY_PR }
86 };
87
88 /*
89 * Allowed NFIFO LOAD pad flags for each SEC Era.
90 * Values represent the number of entries from nfifo_pad_flags[] that are
91 * supported.
92 */
93 static const unsigned int nfifo_pad_flags_sz[] = {2, 2, 2, 2, 3, 3, 3, 3, 3, 3};
94
95 static inline int
rta_nfifo_load(struct program * program,uint32_t src,uint32_t data,uint32_t length,uint32_t flags)96 rta_nfifo_load(struct program *program, uint32_t src,
97 uint32_t data, uint32_t length, uint32_t flags)
98 {
99 uint32_t opcode = 0, val;
100 int ret = -EINVAL;
101 uint32_t load_cmd = CMD_LOAD | LDST_IMM | LDST_CLASS_IND_CCB |
102 LDST_SRCDST_WORD_INFO_FIFO;
103 unsigned int start_pc = program->current_pc;
104
105 if ((data == AFHA_SBOX) && (rta_sec_era == RTA_SEC_ERA_7)) {
106 pr_err("NFIFO: AFHA S-box not supported by SEC Era %d\n",
107 USER_SEC_ERA(rta_sec_era));
108 goto err;
109 }
110
111 /* write source field */
112 ret = __rta_map_opcode(src, nfifo_src, nfifo_src_sz[rta_sec_era], &val);
113 if (ret < 0) {
114 pr_err("NFIFO: Invalid SRC. SEC PC: %d; Instr: %d\n",
115 program->current_pc, program->current_instruction);
116 goto err;
117 }
118 opcode |= val;
119
120 /* write type field */
121 ret = __rta_map_opcode(data, nfifo_data, ARRAY_SIZE(nfifo_data), &val);
122 if (ret < 0) {
123 pr_err("NFIFO: Invalid data. SEC PC: %d; Instr: %d\n",
124 program->current_pc, program->current_instruction);
125 goto err;
126 }
127 opcode |= val;
128
129 /* write DL field */
130 if (!(flags & EXT)) {
131 opcode |= length & NFIFOENTRY_DLEN_MASK;
132 load_cmd |= 4;
133 } else {
134 load_cmd |= 8;
135 }
136
137 /* write flags */
138 __rta_map_flags(flags, nfifo_flags, nfifo_flags_sz[rta_sec_era],
139 &opcode);
140
141 /* in case of padding, check the destination */
142 if (src == PAD)
143 __rta_map_flags(flags, nfifo_pad_flags,
144 nfifo_pad_flags_sz[rta_sec_era], &opcode);
145
146 /* write LOAD command first */
147 __rta_out32(program, load_cmd);
148 __rta_out32(program, opcode);
149
150 if (flags & EXT)
151 __rta_out32(program, length & NFIFOENTRY_DLEN_MASK);
152
153 program->current_instruction++;
154
155 return (int)start_pc;
156
157 err:
158 program->first_error_pc = start_pc;
159 program->current_instruction++;
160 return ret;
161 }
162
163 #endif /* __RTA_NFIFO_CMD_H__ */
164