1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
3 */
4
5 #ifndef __OTX2_TM_H__
6 #define __OTX2_TM_H__
7
8 #include <stdbool.h>
9
10 #include <rte_tm_driver.h>
11
12 #define NIX_TM_DEFAULT_TREE BIT_ULL(0)
13 #define NIX_TM_COMMITTED BIT_ULL(1)
14 #define NIX_TM_RATE_LIMIT_TREE BIT_ULL(2)
15 #define NIX_TM_TL1_NO_SP BIT_ULL(3)
16
17 struct otx2_eth_dev;
18
19 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
20 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
21 int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
22 int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
23 int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
24 uint32_t *rr_quantum, uint16_t *smq);
25 int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
26 uint16_t queue_idx, uint16_t tx_rate);
27 int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
28 int otx2_nix_sq_flush_post(void *_txq);
29 int otx2_nix_sq_enable(void *_txq);
30 int otx2_nix_get_link(struct otx2_eth_dev *dev);
31 int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
32
33 struct otx2_nix_tm_node {
34 TAILQ_ENTRY(otx2_nix_tm_node) node;
35 uint32_t id;
36 uint32_t hw_id;
37 uint32_t priority;
38 uint32_t weight;
39 uint16_t lvl;
40 uint16_t hw_lvl;
41 uint32_t rr_prio;
42 uint32_t rr_num;
43 uint32_t max_prio;
44 uint32_t parent_hw_id;
45 uint32_t flags:16;
46 #define NIX_TM_NODE_HWRES BIT_ULL(0)
47 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
48 #define NIX_TM_NODE_USER BIT_ULL(2)
49 #define NIX_TM_NODE_RED_DISCARD BIT_ULL(3)
50 /* Shaper algorithm for RED state @NIX_REDALG_E */
51 uint32_t red_algo:2;
52 uint32_t pkt_mode:1;
53
54 struct otx2_nix_tm_node *parent;
55 struct rte_tm_node_params params;
56
57 /* Last stats */
58 uint64_t last_pkts;
59 uint64_t last_bytes;
60 };
61
62 struct otx2_nix_tm_shaper_profile {
63 TAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;
64 uint32_t shaper_profile_id;
65 uint32_t reference_count;
66 struct rte_tm_shaper_params params; /* Rate in bits/sec */
67 };
68
69 struct shaper_params {
70 uint64_t burst_exponent;
71 uint64_t burst_mantissa;
72 uint64_t div_exp;
73 uint64_t exponent;
74 uint64_t mantissa;
75 uint64_t burst;
76 uint64_t rate;
77 };
78
79 TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);
80 TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
81
82 #define MAX_SCHED_WEIGHT ((uint8_t)~0)
83 #define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
84 #define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight) \
85 ((((__weight) & MAX_SCHED_WEIGHT) * \
86 NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)
87
88 /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */
89 /* = NIX_MAX_HW_MTU */
90 #define DEFAULT_RR_WEIGHT 71
91
92 /** NIX rate limits */
93 #define MAX_RATE_DIV_EXP 12
94 #define MAX_RATE_EXPONENT 0xf
95 #define MAX_RATE_MANTISSA 0xff
96
97 #define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)
98
99 /* NIX rate calculation in Bits/Sec
100 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
101 * << NIX_*_PIR[RATE_EXPONENT]) / 256
102 * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
103 *
104 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
105 * << NIX_*_CIR[RATE_EXPONENT]) / 256
106 * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
107 */
108 #define SHAPER_RATE(exponent, mantissa, div_exp) \
109 ((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\
110 / (((1ull << (div_exp)) * 256)))
111
112 /* 96xx rate limits in Bits/Sec */
113 #define MIN_SHAPER_RATE \
114 SHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)
115
116 #define MAX_SHAPER_RATE \
117 SHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)
118
119 /* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */
120 #define NIX_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1)
121 #define NIX_LENGTH_ADJUST_MAX 255
122
123 /** TM Shaper - low level operations */
124
125 /** NIX burst limits */
126 #define MAX_BURST_EXPONENT 0xf
127 #define MAX_BURST_MANTISSA 0xff
128
129 /* NIX burst calculation
130 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
131 * << (NIX_*_PIR[BURST_EXPONENT] + 1))
132 * / 256
133 *
134 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
135 * << (NIX_*_CIR[BURST_EXPONENT] + 1))
136 * / 256
137 */
138 #define SHAPER_BURST(exponent, mantissa) \
139 (((256 + (mantissa)) << ((exponent) + 1)) / 256)
140
141 /** Shaper burst limits */
142 #define MIN_SHAPER_BURST \
143 SHAPER_BURST(0, 0)
144
145 #define MAX_SHAPER_BURST \
146 SHAPER_BURST(MAX_BURST_EXPONENT,\
147 MAX_BURST_MANTISSA)
148
149 /* Default TL1 priority and Quantum from AF */
150 #define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)
151 #define TXSCH_TL1_DFLT_RR_PRIO 1
152
153 #define TXSCH_TLX_SP_PRIO_MAX 10
154
155 static inline const char *
nix_hwlvl2str(uint32_t hw_lvl)156 nix_hwlvl2str(uint32_t hw_lvl)
157 {
158 switch (hw_lvl) {
159 case NIX_TXSCH_LVL_MDQ:
160 return "SMQ/MDQ";
161 case NIX_TXSCH_LVL_TL4:
162 return "TL4";
163 case NIX_TXSCH_LVL_TL3:
164 return "TL3";
165 case NIX_TXSCH_LVL_TL2:
166 return "TL2";
167 case NIX_TXSCH_LVL_TL1:
168 return "TL1";
169 default:
170 break;
171 }
172
173 return "???";
174 }
175
176 #endif /* __OTX2_TM_H__ */
177