1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2020 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_REGEXDEV_H_ 6 #define _OTX2_REGEXDEV_H_ 7 8 #include <rte_common.h> 9 #include <rte_regexdev.h> 10 11 #include "otx2_dev.h" 12 13 #define ree_func_trace otx2_ree_dbg 14 15 /* Marvell OCTEON TX2 Regex PMD device name */ 16 #define REGEXDEV_NAME_OCTEONTX2_PMD regex_octeontx2 17 18 #define OTX2_REE_MAX_LFS 36 19 #define OTX2_REE_MAX_QUEUES_PER_VF 36 20 #define OTX2_REE_MAX_MATCHES_PER_VF 254 21 22 #define OTX2_REE_MAX_PAYLOAD_SIZE (1 << 14) 23 24 #define OTX2_REE_NON_INC_PROG 0 25 #define OTX2_REE_INC_PROG 1 26 27 #define REE_MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++) 28 29 30 /** 31 * Device vf data 32 */ 33 struct otx2_ree_vf { 34 struct otx2_dev otx2_dev; 35 /**< Base class */ 36 uint16_t max_queues; 37 /**< Max queues supported */ 38 uint8_t nb_queues; 39 /**< Number of regex queues attached */ 40 uint16_t max_matches; 41 /**< Max matches supported*/ 42 uint16_t lf_msixoff[OTX2_REE_MAX_LFS]; 43 /**< MSI-X offsets */ 44 uint8_t block_address; 45 /**< REE Block Address */ 46 uint8_t err_intr_registered:1; 47 /**< Are error interrupts registered? */ 48 }; 49 50 /** 51 * Device private data 52 */ 53 struct otx2_ree_data { 54 uint32_t regexdev_capa; 55 uint64_t rule_flags; 56 /**< Feature flags exposes HW/SW features for the given device */ 57 uint16_t max_rules_per_group; 58 /**< Maximum rules supported per subset by this device */ 59 uint16_t max_groups; 60 /**< Maximum subset supported by this device */ 61 void **queue_pairs; 62 /**< Array of pointers to queue pairs. */ 63 uint16_t nb_queue_pairs; 64 /**< Number of device queue pairs. */ 65 struct otx2_ree_vf vf; 66 /**< vf data */ 67 struct rte_regexdev_rule *rules; 68 /**< rules to be compiled */ 69 uint16_t nb_rules; 70 /**< number of rules */ 71 } __rte_cache_aligned; 72 73 struct otx2_ree_rid { 74 uintptr_t rid; 75 /** Request id of a ree operation */ 76 uint64_t user_id; 77 /* Client data */ 78 /**< IOVA address of the pattern to be matched. */ 79 }; 80 81 struct otx2_ree_pending_queue { 82 uint64_t pending_count; 83 /** Pending requests count */ 84 struct otx2_ree_rid *rid_queue; 85 /** Array of pending requests */ 86 uint16_t enq_tail; 87 /** Tail of queue to be used for enqueue */ 88 uint16_t deq_head; 89 /** Head of queue to be used for dequeue */ 90 }; 91 92 struct otx2_ree_qp { 93 uint32_t id; 94 /**< Queue pair id */ 95 uintptr_t base; 96 /**< Base address where BAR is mapped */ 97 struct otx2_ree_pending_queue pend_q; 98 /**< Pending queue */ 99 rte_iova_t iq_dma_addr; 100 /**< Instruction queue address */ 101 uint32_t otx2_regexdev_jobid; 102 /**< Job ID */ 103 uint32_t write_offset; 104 /**< write offset */ 105 regexdev_stop_flush_t cb; 106 /**< Callback function called during rte_regex_dev_stop()*/ 107 }; 108 109 #endif /* _OTX2_REGEXDEV_H_ */ 110