1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
3 */
4
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
7
8 #include <math.h>
9 #include <stdint.h>
10
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
13 #include <rte_kvargs.h>
14 #include <rte_mbuf.h>
15 #include <rte_mempool.h>
16 #include <rte_security_driver.h>
17 #include <rte_string_fns.h>
18 #include <rte_time.h>
19
20 #include "otx2_common.h"
21 #include "otx2_dev.h"
22 #include "otx2_flow.h"
23 #include "otx2_irq.h"
24 #include "otx2_mempool.h"
25 #include "otx2_rx.h"
26 #include "otx2_tm.h"
27 #include "otx2_tx.h"
28
29 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
30
31 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
32
33 /* Minimum CQ size should be 4K */
34 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
35 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
36 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
37 /* Limit CQ being full */
38 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
39 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
40 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
41
42 /* Used for struct otx2_eth_dev::flags */
43 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
44
45 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
46 * In Tx space is always reserved for this in FRS.
47 */
48 #define NIX_MAX_VTAG_INS 2
49 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
50
51 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
52 #define NIX_L2_OVERHEAD \
53 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
54
55 /* HW config of frame size doesn't include FCS */
56 #define NIX_MAX_HW_FRS 9212
57 #define NIX_MIN_HW_FRS 60
58
59 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
60 #define NIX_MAX_FRS \
61 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
62
63 #define NIX_MIN_FRS \
64 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
65
66 #define NIX_MAX_MTU \
67 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
68
69 #define NIX_MAX_SQB 512
70 #define NIX_DEF_SQB 16
71 #define NIX_MIN_SQB 8
72 #define NIX_SQB_LIST_SPACE 2
73 #define NIX_RSS_RETA_SIZE_MAX 256
74 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
75 #define NIX_RSS_GRPS 8
76 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
77 #define NIX_RSS_RETA_SIZE 64
78 #define NIX_RX_MIN_DESC 16
79 #define NIX_RX_MIN_DESC_ALIGN 16
80 #define NIX_RX_NB_SEG_MAX 6
81 #define NIX_CQ_ENTRY_SZ 128
82 #define NIX_CQ_ALIGN 512
83 #define NIX_SQB_LOWER_THRESH 70
84 #define LMT_SLOT_MASK 0x7f
85 #define NIX_RX_DEFAULT_RING_SZ 4096
86
87 /* If PTP is enabled additional SEND MEM DESC is required which
88 * takes 2 words, hence max 7 iova address are possible
89 */
90 #if defined(RTE_LIBRTE_IEEE1588)
91 #define NIX_TX_NB_SEG_MAX 7
92 #else
93 #define NIX_TX_NB_SEG_MAX 9
94 #endif
95
96 #define NIX_TX_MSEG_SG_DWORDS \
97 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
98 + NIX_TX_NB_SEG_MAX)
99
100 /* Apply BP/DROP when CQ is 95% full */
101 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
102 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
103
104 #define CQ_OP_STAT_OP_ERR 63
105 #define CQ_OP_STAT_CQ_ERR 46
106
107 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
108 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
109
110 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
111 * NIX_LF_CINTX_CNT[QCOUNT]
112 * crosses this value
113 */
114 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
115 #define CQ_TIMER_THRESH_MAX 255
116
117 #define NIX_RSS_L3_L4_SRC_DST (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY \
118 | ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
119
120 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
121 ETH_RSS_TCP | ETH_RSS_SCTP | \
122 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
123 NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
124 ETH_RSS_C_VLAN)
125
126 #define NIX_TX_OFFLOAD_CAPA ( \
127 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
128 DEV_TX_OFFLOAD_MT_LOCKFREE | \
129 DEV_TX_OFFLOAD_VLAN_INSERT | \
130 DEV_TX_OFFLOAD_QINQ_INSERT | \
131 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
133 DEV_TX_OFFLOAD_TCP_CKSUM | \
134 DEV_TX_OFFLOAD_UDP_CKSUM | \
135 DEV_TX_OFFLOAD_SCTP_CKSUM | \
136 DEV_TX_OFFLOAD_TCP_TSO | \
137 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
138 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
139 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS | \
141 DEV_TX_OFFLOAD_IPV4_CKSUM)
142
143 #define NIX_RX_OFFLOAD_CAPA ( \
144 DEV_RX_OFFLOAD_CHECKSUM | \
145 DEV_RX_OFFLOAD_SCTP_CKSUM | \
146 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_RX_OFFLOAD_SCATTER | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
150 DEV_RX_OFFLOAD_VLAN_STRIP | \
151 DEV_RX_OFFLOAD_VLAN_FILTER | \
152 DEV_RX_OFFLOAD_QINQ_STRIP | \
153 DEV_RX_OFFLOAD_TIMESTAMP | \
154 DEV_RX_OFFLOAD_RSS_HASH)
155
156 #define NIX_DEFAULT_RSS_CTX_GROUP 0
157 #define NIX_DEFAULT_RSS_MCAM_IDX -1
158
159 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
160
161 #define NIX_TIMESYNC_TX_CMD_LEN 8
162 /* Additional timesync values. */
163 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
164
165 enum nix_q_size_e {
166 nix_q_size_16, /* 16 entries */
167 nix_q_size_64, /* 64 entries */
168 nix_q_size_256,
169 nix_q_size_1K,
170 nix_q_size_4K,
171 nix_q_size_16K,
172 nix_q_size_64K,
173 nix_q_size_256K,
174 nix_q_size_1M, /* Million entries */
175 nix_q_size_max
176 };
177
178 struct otx2_qint {
179 struct rte_eth_dev *eth_dev;
180 uint8_t qintx;
181 };
182
183 struct otx2_rss_info {
184 uint64_t nix_rss;
185 uint32_t flowkey_cfg;
186 uint16_t rss_size;
187 uint8_t rss_grps;
188 uint8_t alg_idx; /* Selected algo index */
189 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
190 uint8_t key[NIX_HASH_KEY_SIZE];
191 };
192
193 struct otx2_eth_qconf {
194 union {
195 struct rte_eth_txconf tx;
196 struct rte_eth_rxconf rx;
197 } conf;
198 void *mempool;
199 uint32_t socket_id;
200 uint16_t nb_desc;
201 uint8_t valid;
202 };
203
204 struct otx2_fc_info {
205 enum rte_eth_fc_mode mode; /**< Link flow control mode */
206 uint8_t rx_pause;
207 uint8_t tx_pause;
208 uint8_t chan_cnt;
209 uint16_t bpid[NIX_MAX_CHAN];
210 };
211
212 struct vlan_mkex_info {
213 struct npc_xtract_info la_xtract;
214 struct npc_xtract_info lb_xtract;
215 uint64_t lb_lt_offset;
216 };
217
218 struct mcast_entry {
219 struct rte_ether_addr mcast_mac;
220 uint16_t mcam_index;
221 TAILQ_ENTRY(mcast_entry) next;
222 };
223
224 TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
225
226 struct vlan_entry {
227 uint32_t mcam_idx;
228 uint16_t vlan_id;
229 TAILQ_ENTRY(vlan_entry) next;
230 };
231
232 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
233
234 struct otx2_vlan_info {
235 struct otx2_vlan_filter_tbl fltr_tbl;
236 /* MKEX layer info */
237 struct mcam_entry def_tx_mcam_ent;
238 struct mcam_entry def_rx_mcam_ent;
239 struct vlan_mkex_info mkex;
240 /* Default mcam entry that matches vlan packets */
241 uint32_t def_rx_mcam_idx;
242 uint32_t def_tx_mcam_idx;
243 /* MCAM entry that matches double vlan packets */
244 uint32_t qinq_mcam_idx;
245 /* Indices of tx_vtag def registers */
246 uint32_t outer_vlan_idx;
247 uint32_t inner_vlan_idx;
248 uint16_t outer_vlan_tpid;
249 uint16_t inner_vlan_tpid;
250 uint16_t pvid;
251 /* QinQ entry allocated before default one */
252 uint8_t qinq_before_def;
253 uint8_t pvid_insert_on;
254 /* Rx vtag action type */
255 uint8_t vtag_type_idx;
256 uint8_t filter_on;
257 uint8_t strip_on;
258 uint8_t qinq_on;
259 uint8_t promisc_on;
260 };
261
262 struct otx2_eth_dev {
263 OTX2_DEV; /* Base class */
264 RTE_MARKER otx2_eth_dev_data_start;
265 uint16_t sqb_size;
266 uint16_t rx_chan_base;
267 uint16_t tx_chan_base;
268 uint8_t rx_chan_cnt;
269 uint8_t tx_chan_cnt;
270 uint8_t lso_tsov4_idx;
271 uint8_t lso_tsov6_idx;
272 uint8_t lso_base_idx;
273 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
274 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
275 uint8_t max_mac_entries;
276 bool dmac_filter_enable;
277 uint8_t lf_tx_stats;
278 uint8_t lf_rx_stats;
279 uint8_t lock_rx_ctx;
280 uint8_t lock_tx_ctx;
281 uint16_t flags;
282 uint16_t cints;
283 uint16_t qints;
284 uint8_t configured;
285 uint8_t configured_qints;
286 uint8_t configured_cints;
287 uint8_t configured_nb_rx_qs;
288 uint8_t configured_nb_tx_qs;
289 uint8_t ptype_disable;
290 uint16_t nix_msixoff;
291 uintptr_t base;
292 uintptr_t lmt_addr;
293 uint16_t scalar_ena;
294 uint16_t rss_tag_as_xor;
295 uint16_t max_sqb_count;
296 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
297 uint64_t rx_offloads;
298 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
299 uint64_t tx_offloads;
300 uint64_t rx_offload_capa;
301 uint64_t tx_offload_capa;
302 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
303 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
304 uint16_t txschq[NIX_TXSCH_LVL_CNT];
305 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
306 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
307 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
308 /* Dis-contiguous queues */
309 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
310 /* Contiguous queues */
311 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
312 uint16_t otx2_tm_root_lvl;
313 uint16_t link_cfg_lvl;
314 uint16_t tm_flags;
315 uint16_t tm_leaf_cnt;
316 uint64_t tm_rate_min;
317 struct otx2_nix_tm_node_list node_list;
318 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
319 struct otx2_rss_info rss_info;
320 struct otx2_fc_info fc_info;
321 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
322 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
323 struct otx2_npc_flow_info npc_flow;
324 struct otx2_vlan_info vlan_info;
325 struct otx2_eth_qconf *tx_qconf;
326 struct otx2_eth_qconf *rx_qconf;
327 struct rte_eth_dev *eth_dev;
328 eth_rx_burst_t rx_pkt_burst_no_offload;
329 /* PTP counters */
330 bool ptp_en;
331 struct otx2_timesync_info tstamp;
332 struct rte_timecounter systime_tc;
333 struct rte_timecounter rx_tstamp_tc;
334 struct rte_timecounter tx_tstamp_tc;
335 double clk_freq_mult;
336 uint64_t clk_delta;
337 bool mc_tbl_set;
338 struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
339 bool sdp_link; /* SDP flag */
340 /* Inline IPsec params */
341 uint16_t ipsec_in_max_spi;
342 uint8_t duplex;
343 uint32_t speed;
344 } __rte_cache_aligned;
345
346 struct otx2_eth_txq {
347 uint64_t cmd[8];
348 int64_t fc_cache_pkts;
349 uint64_t *fc_mem;
350 void *lmt_addr;
351 rte_iova_t io_addr;
352 rte_iova_t fc_iova;
353 uint16_t sqes_per_sqb_log2;
354 int16_t nb_sqb_bufs_adj;
355 RTE_MARKER slow_path_start;
356 uint16_t nb_sqb_bufs;
357 uint16_t sq;
358 uint64_t offloads;
359 struct otx2_eth_dev *dev;
360 struct rte_mempool *sqb_pool;
361 struct otx2_eth_qconf qconf;
362 } __rte_cache_aligned;
363
364 struct otx2_eth_rxq {
365 uint64_t mbuf_initializer;
366 uint64_t data_off;
367 uintptr_t desc;
368 void *lookup_mem;
369 uintptr_t cq_door;
370 uint64_t wdata;
371 int64_t *cq_status;
372 uint32_t head;
373 uint32_t qmask;
374 uint32_t available;
375 uint16_t rq;
376 struct otx2_timesync_info *tstamp;
377 RTE_MARKER slow_path_start;
378 uint64_t aura;
379 uint64_t offloads;
380 uint32_t qlen;
381 struct rte_mempool *pool;
382 enum nix_q_size_e qsize;
383 struct rte_eth_dev *eth_dev;
384 struct otx2_eth_qconf qconf;
385 uint16_t cq_drop;
386 } __rte_cache_aligned;
387
388 static inline struct otx2_eth_dev *
otx2_eth_pmd_priv(struct rte_eth_dev * eth_dev)389 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
390 {
391 return eth_dev->data->dev_private;
392 }
393
394 /* Ops */
395 int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
396 struct rte_eth_dev_info *dev_info);
397 int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
398 enum rte_filter_type filter_type,
399 enum rte_filter_op filter_op, void *arg);
400 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
401 size_t fw_size);
402 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
403 struct rte_eth_dev_module_info *modinfo);
404 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
405 struct rte_dev_eeprom_info *info);
406 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
407 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
408 struct rte_eth_rxq_info *qinfo);
409 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
410 struct rte_eth_txq_info *qinfo);
411 int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
412 struct rte_eth_burst_mode *mode);
413 int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
414 struct rte_eth_burst_mode *mode);
415 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
416 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
417 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
418 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
419 int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
420
421 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
422 int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
423 int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
424 int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
425 int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
426 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
427 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
428 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
429
430 /* Multicast filter APIs */
431 void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
432 void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
433 int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
434 int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
435 int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
436 struct rte_ether_addr *mc_addr_set,
437 uint32_t nb_mc_addr);
438
439 /* MTU */
440 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
441 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
442 void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
443
444
445 /* Link */
446 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
447 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
448 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
449 struct cgx_link_user_info *link);
450 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
451 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
452 int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
453
454 /* IRQ */
455 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
456 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
457 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
458 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
459 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
460 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
461 void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
462 void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
463
464 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
465 uint16_t rx_queue_id);
466 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
467 uint16_t rx_queue_id);
468
469 /* Debug */
470 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
471 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
472 struct rte_dev_reg_info *regs);
473 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
474 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
475 void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
476
477 /* Stats */
478 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
479 struct rte_eth_stats *stats);
480 int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
481
482 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
483 uint16_t queue_id, uint8_t stat_idx,
484 uint8_t is_rx);
485 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
486 struct rte_eth_xstat *xstats, unsigned int n);
487 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
488 struct rte_eth_xstat_name *xstats_names,
489 unsigned int limit);
490 int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
491
492 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
493 const uint64_t *ids,
494 uint64_t *values, unsigned int n);
495 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
496 struct rte_eth_xstat_name *xstats_names,
497 const uint64_t *ids, unsigned int limit);
498
499 /* RSS */
500 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
501 uint8_t *key, uint32_t key_len);
502 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
503 uint64_t ethdev_rss, uint8_t rss_level);
504 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
505 uint32_t flowkey_cfg, uint8_t *alg_idx,
506 uint8_t group, int mcam_index);
507 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
508 uint16_t *ind_tbl);
509 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
510
511 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
512 struct rte_eth_rss_reta_entry64 *reta_conf,
513 uint16_t reta_size);
514 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
515 struct rte_eth_rss_reta_entry64 *reta_conf,
516 uint16_t reta_size);
517 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
518 struct rte_eth_rss_conf *rss_conf);
519
520 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
521 struct rte_eth_rss_conf *rss_conf);
522
523 /* CGX */
524 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
525 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
526 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
527 struct rte_ether_addr *addr);
528
529 /* Flow Control */
530 int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
531
532 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
533 struct rte_eth_fc_conf *fc_conf);
534
535 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
536 struct rte_eth_fc_conf *fc_conf);
537
538 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
539
540 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
541
542 /* VLAN */
543 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
544 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
545 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
546 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
547 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
548 int on);
549 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
550 uint16_t queue, int on);
551 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
552 enum rte_vlan_type type, uint16_t tpid);
553 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
554
555 /* Lookup configuration */
556 void *otx2_nix_fastpath_lookup_mem_get(void);
557
558 /* PTYPES */
559 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
560 int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
561
562 /* Mac address handling */
563 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
564 struct rte_ether_addr *addr);
565 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
566 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
567 struct rte_ether_addr *addr,
568 uint32_t index, uint32_t pool);
569 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
570 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
571
572 /* Devargs */
573 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
574 struct otx2_eth_dev *dev);
575
576 /* Rx and Tx routines */
577 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
578 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
579 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
580
581 /* Timesync - PTP routines */
582 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
583 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
584 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
585 struct timespec *timestamp,
586 uint32_t flags);
587 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
588 struct timespec *timestamp);
589 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
590 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
591 const struct timespec *ts);
592 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
593 struct timespec *ts);
594 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
595 int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
596 int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
597 void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
598
599 #endif /* __OTX2_ETHDEV_H__ */
600