1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_COMMON_H_ 6 #define _OTX2_COMMON_H_ 7 8 #include <rte_atomic.h> 9 #include <rte_common.h> 10 #include <rte_cycles.h> 11 #include <rte_kvargs.h> 12 #include <rte_memory.h> 13 #include <rte_memzone.h> 14 #include <rte_io.h> 15 16 #include "hw/otx2_rvu.h" 17 #include "hw/otx2_nix.h" 18 #include "hw/otx2_npc.h" 19 #include "hw/otx2_npa.h" 20 #include "hw/otx2_sdp.h" 21 #include "hw/otx2_sso.h" 22 #include "hw/otx2_ssow.h" 23 #include "hw/otx2_tim.h" 24 #include "hw/otx2_ree.h" 25 26 /* Alignment */ 27 #define OTX2_ALIGN 128 28 29 /* Bits manipulation */ 30 #ifndef BIT_ULL 31 #define BIT_ULL(nr) (1ULL << (nr)) 32 #endif 33 #ifndef BIT 34 #define BIT(nr) (1UL << (nr)) 35 #endif 36 37 #ifndef BITS_PER_LONG 38 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 39 #endif 40 #ifndef BITS_PER_LONG_LONG 41 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8) 42 #endif 43 44 #ifndef GENMASK 45 #define GENMASK(h, l) \ 46 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 47 #endif 48 #ifndef GENMASK_ULL 49 #define GENMASK_ULL(h, l) \ 50 (((~0ULL) - (1ULL << (l)) + 1) & \ 51 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) 52 #endif 53 54 #define OTX2_NPA_LOCK_MASK "npa_lock_mask" 55 56 /* Intra device related functions */ 57 struct otx2_npa_lf; 58 struct otx2_idev_cfg { 59 uint16_t sso_pf_func; 60 uint16_t npa_pf_func; 61 struct otx2_npa_lf *npa_lf; 62 RTE_STD_C11 63 union { 64 rte_atomic16_t npa_refcnt; 65 uint16_t npa_refcnt_u16; 66 }; 67 uint64_t npa_lock_mask; 68 }; 69 70 __rte_internal 71 struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void); 72 __rte_internal 73 void otx2_sso_pf_func_set(uint16_t sso_pf_func); 74 __rte_internal 75 uint16_t otx2_sso_pf_func_get(void); 76 __rte_internal 77 uint16_t otx2_npa_pf_func_get(void); 78 __rte_internal 79 struct otx2_npa_lf *otx2_npa_lf_obj_get(void); 80 __rte_internal 81 void otx2_npa_set_defaults(struct otx2_idev_cfg *idev); 82 __rte_internal 83 int otx2_npa_lf_active(void *dev); 84 __rte_internal 85 int otx2_npa_lf_obj_ref(void); 86 __rte_internal 87 void otx2_parse_common_devargs(struct rte_kvargs *kvlist); 88 89 /* Log */ 90 extern int otx2_logtype_base; 91 extern int otx2_logtype_mbox; 92 extern int otx2_logtype_npa; 93 extern int otx2_logtype_nix; 94 extern int otx2_logtype_sso; 95 extern int otx2_logtype_npc; 96 extern int otx2_logtype_tm; 97 extern int otx2_logtype_tim; 98 extern int otx2_logtype_dpi; 99 extern int otx2_logtype_ep; 100 extern int otx2_logtype_ree; 101 102 #define otx2_err(fmt, args...) \ 103 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", \ 104 __func__, __LINE__, ## args) 105 106 #define otx2_info(fmt, args...) \ 107 RTE_LOG(INFO, PMD, fmt"\n", ## args) 108 109 #define otx2_dbg(subsystem, fmt, args...) \ 110 rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \ 111 "[%s] %s():%u " fmt "\n", \ 112 #subsystem, __func__, __LINE__, ##args) 113 114 #define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__) 115 #define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__) 116 #define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__) 117 #define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__) 118 #define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__) 119 #define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__) 120 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__) 121 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__) 122 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__) 123 #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__) 124 #define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__) 125 126 /* PCI IDs */ 127 #define PCI_VENDOR_ID_CAVIUM 0x177D 128 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 129 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 130 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 131 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9 132 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA 133 #define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB 134 #define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC 135 #define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD 136 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE 137 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8 138 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081 139 #define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */ 140 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF 0xA0f6 141 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF 0xA0f7 142 #define PCI_DEVID_OCTEONTX2_RVU_REE_PF 0xA0f4 143 #define PCI_DEVID_OCTEONTX2_RVU_REE_VF 0xA0f5 144 145 /* 146 * REVID for RVU PCIe devices. 147 * Bits 0..1: minor pass 148 * Bits 3..2: major pass 149 * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown 150 */ 151 152 #define RVU_PCI_REV_MIDR_ID(rev_id) (rev_id >> 4) 153 #define RVU_PCI_REV_MAJOR(rev_id) ((rev_id >> 2) & 0x3) 154 #define RVU_PCI_REV_MINOR(rev_id) (rev_id & 0x3) 155 156 #define RVU_PCI_CN96XX_MIDR_ID 0x0 157 #define RVU_PCI_CNF95XX_MIDR_ID 0x1 158 159 /* PCI Config offsets */ 160 #define RVU_PCI_REVISION_ID 0x08 161 162 /* IO Access */ 163 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr)) 164 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr)) 165 166 #if defined(RTE_ARCH_ARM64) 167 #include "otx2_io_arm64.h" 168 #else 169 #include "otx2_io_generic.h" 170 #endif 171 172 /* Fastpath lookup */ 173 #define OTX2_NIX_FASTPATH_LOOKUP_MEM "otx2_nix_fastpath_lookup_mem" 174 #define OTX2_NIX_SA_TBL_START (4096*4 + 69632*2) 175 176 #endif /* _OTX2_COMMON_H_ */ 177