1&l4_abe {						/* 0x40100000 */
2	compatible = "ti,omap4-l4-abe", "simple-bus";
3	reg = <0x40100000 0x400>,
4	      <0x40100400 0x400>;
5	reg-names = "la", "ap";
6	#address-cells = <1>;
7	#size-cells = <1>;
8	ranges = <0x00000000 0x40100000 0x100000>,	/* segment 0 */
9		 <0x49000000 0x49000000 0x100000>;
10	segment@0 {					/* 0x40100000 */
11		compatible = "simple-bus";
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges =
15			 /* CPU to L4 ABE mapping */
16			 <0x00000000 0x00000000 0x000400>,	/* ap 0 */
17			 <0x00000400 0x00000400 0x000400>,	/* ap 1 */
18			 <0x00022000 0x00022000 0x001000>,	/* ap 2 */
19			 <0x00023000 0x00023000 0x001000>,	/* ap 3 */
20			 <0x00024000 0x00024000 0x001000>,	/* ap 4 */
21			 <0x00025000 0x00025000 0x001000>,	/* ap 5 */
22			 <0x00026000 0x00026000 0x001000>,	/* ap 6 */
23			 <0x00027000 0x00027000 0x001000>,	/* ap 7 */
24			 <0x00028000 0x00028000 0x001000>,	/* ap 8 */
25			 <0x00029000 0x00029000 0x001000>,	/* ap 9 */
26			 <0x0002a000 0x0002a000 0x001000>,	/* ap 10 */
27			 <0x0002b000 0x0002b000 0x001000>,	/* ap 11 */
28			 <0x0002e000 0x0002e000 0x001000>,	/* ap 12 */
29			 <0x0002f000 0x0002f000 0x001000>,	/* ap 13 */
30			 <0x00030000 0x00030000 0x001000>,	/* ap 14 */
31			 <0x00031000 0x00031000 0x001000>,	/* ap 15 */
32			 <0x00032000 0x00032000 0x001000>,	/* ap 16 */
33			 <0x00033000 0x00033000 0x001000>,	/* ap 17 */
34			 <0x00038000 0x00038000 0x001000>,	/* ap 18 */
35			 <0x00039000 0x00039000 0x001000>,	/* ap 19 */
36			 <0x0003a000 0x0003a000 0x001000>,	/* ap 20 */
37			 <0x0003b000 0x0003b000 0x001000>,	/* ap 21 */
38			 <0x0003c000 0x0003c000 0x001000>,	/* ap 22 */
39			 <0x0003d000 0x0003d000 0x001000>,	/* ap 23 */
40			 <0x0003e000 0x0003e000 0x001000>,	/* ap 24 */
41			 <0x0003f000 0x0003f000 0x001000>,	/* ap 25 */
42			 <0x00080000 0x00080000 0x010000>,	/* ap 26 */
43			 <0x00080000 0x00080000 0x001000>,	/* ap 27 */
44			 <0x000a0000 0x000a0000 0x010000>,	/* ap 28 */
45			 <0x000a0000 0x000a0000 0x001000>,	/* ap 29 */
46			 <0x000c0000 0x000c0000 0x010000>,	/* ap 30 */
47			 <0x000c0000 0x000c0000 0x001000>,	/* ap 31 */
48			 <0x000f1000 0x000f1000 0x001000>,	/* ap 32 */
49			 <0x000f2000 0x000f2000 0x001000>,	/* ap 33 */
50
51			 /* L3 to L4 ABE mapping */
52			 <0x49000000 0x49000000 0x000400>,	/* ap 0 */
53			 <0x49000400 0x49000400 0x000400>,	/* ap 1 */
54			 <0x49022000 0x49022000 0x001000>,	/* ap 2 */
55			 <0x49023000 0x49023000 0x001000>,	/* ap 3 */
56			 <0x49024000 0x49024000 0x001000>,	/* ap 4 */
57			 <0x49025000 0x49025000 0x001000>,	/* ap 5 */
58			 <0x49026000 0x49026000 0x001000>,	/* ap 6 */
59			 <0x49027000 0x49027000 0x001000>,	/* ap 7 */
60			 <0x49028000 0x49028000 0x001000>,	/* ap 8 */
61			 <0x49029000 0x49029000 0x001000>,	/* ap 9 */
62			 <0x4902a000 0x4902a000 0x001000>,	/* ap 10 */
63			 <0x4902b000 0x4902b000 0x001000>,	/* ap 11 */
64			 <0x4902e000 0x4902e000 0x001000>,	/* ap 12 */
65			 <0x4902f000 0x4902f000 0x001000>,	/* ap 13 */
66			 <0x49030000 0x49030000 0x001000>,	/* ap 14 */
67			 <0x49031000 0x49031000 0x001000>,	/* ap 15 */
68			 <0x49032000 0x49032000 0x001000>,	/* ap 16 */
69			 <0x49033000 0x49033000 0x001000>,	/* ap 17 */
70			 <0x49038000 0x49038000 0x001000>,	/* ap 18 */
71			 <0x49039000 0x49039000 0x001000>,	/* ap 19 */
72			 <0x4903a000 0x4903a000 0x001000>,	/* ap 20 */
73			 <0x4903b000 0x4903b000 0x001000>,	/* ap 21 */
74			 <0x4903c000 0x4903c000 0x001000>,	/* ap 22 */
75			 <0x4903d000 0x4903d000 0x001000>,	/* ap 23 */
76			 <0x4903e000 0x4903e000 0x001000>,	/* ap 24 */
77			 <0x4903f000 0x4903f000 0x001000>,	/* ap 25 */
78			 <0x49080000 0x49080000 0x010000>,	/* ap 26 */
79			 <0x49080000 0x49080000 0x001000>,	/* ap 27 */
80			 <0x490a0000 0x490a0000 0x010000>,	/* ap 28 */
81			 <0x490a0000 0x490a0000 0x001000>,	/* ap 29 */
82			 <0x490c0000 0x490c0000 0x010000>,	/* ap 30 */
83			 <0x490c0000 0x490c0000 0x001000>,	/* ap 31 */
84			 <0x490f1000 0x490f1000 0x001000>,	/* ap 32 */
85			 <0x490f2000 0x490f2000 0x001000>;	/* ap 33 */
86
87		target-module@22000 {			/* 0x40122000, ap 2 02.0 */
88			compatible = "ti,sysc-omap2", "ti,sysc";
89			reg = <0x2208c 0x4>;
90			reg-names = "sysc";
91			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
92					 SYSC_OMAP2_ENAWAKEUP |
93					 SYSC_OMAP2_SOFTRESET)>;
94			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
95					<SYSC_IDLE_NO>,
96					<SYSC_IDLE_SMART>;
97			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
98			clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
99			clock-names = "fck";
100			#address-cells = <1>;
101			#size-cells = <1>;
102			ranges = <0x0 0x22000 0x1000>,
103				 <0x49022000 0x49022000 0x1000>;
104
105			mcbsp1: mcbsp@0 {
106				compatible = "ti,omap4-mcbsp";
107				reg = <0x0 0xff>, /* MPU private access */
108				      <0x49022000 0xff>; /* L3 Interconnect */
109				reg-names = "mpu", "dma";
110				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
111				interrupt-names = "common";
112				ti,buffer-size = <128>;
113				dmas = <&sdma 33>,
114				       <&sdma 34>;
115				dma-names = "tx", "rx";
116				status = "disabled";
117			};
118		};
119
120		target-module@24000 {			/* 0x40124000, ap 4 04.0 */
121			compatible = "ti,sysc-omap2", "ti,sysc";
122			reg = <0x2408c 0x4>;
123			reg-names = "sysc";
124			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
125					 SYSC_OMAP2_ENAWAKEUP |
126					 SYSC_OMAP2_SOFTRESET)>;
127			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
128					<SYSC_IDLE_NO>,
129					<SYSC_IDLE_SMART>;
130			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
131			clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
132			clock-names = "fck";
133			#address-cells = <1>;
134			#size-cells = <1>;
135			ranges = <0x0 0x24000 0x1000>,
136				 <0x49024000 0x49024000 0x1000>;
137
138			mcbsp2: mcbsp@0 {
139				compatible = "ti,omap4-mcbsp";
140				reg = <0x0 0xff>, /* MPU private access */
141				      <0x49024000 0xff>; /* L3 Interconnect */
142				reg-names = "mpu", "dma";
143				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
144				interrupt-names = "common";
145				ti,buffer-size = <128>;
146				dmas = <&sdma 17>,
147				       <&sdma 18>;
148				dma-names = "tx", "rx";
149				status = "disabled";
150			};
151		};
152
153		target-module@26000 {			/* 0x40126000, ap 6 06.0 */
154			compatible = "ti,sysc-omap2", "ti,sysc";
155			reg = <0x2608c 0x4>;
156			reg-names = "sysc";
157			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
158					 SYSC_OMAP2_ENAWAKEUP |
159					 SYSC_OMAP2_SOFTRESET)>;
160			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
161					<SYSC_IDLE_NO>,
162					<SYSC_IDLE_SMART>;
163			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
164			clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
165			clock-names = "fck";
166			#address-cells = <1>;
167			#size-cells = <1>;
168			ranges = <0x0 0x26000 0x1000>,
169				 <0x49026000 0x49026000 0x1000>;
170
171			mcbsp3: mcbsp@0 {
172				compatible = "ti,omap4-mcbsp";
173				reg = <0x0 0xff>, /* MPU private access */
174				      <0x49026000 0xff>; /* L3 Interconnect */
175				reg-names = "mpu", "dma";
176				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
177				interrupt-names = "common";
178				ti,buffer-size = <128>;
179				dmas = <&sdma 19>,
180				       <&sdma 20>;
181				dma-names = "tx", "rx";
182				status = "disabled";
183			};
184		};
185
186		target-module@28000 {			/* 0x40128000, ap 8 08.0 */
187			compatible = "ti,sysc-mcasp", "ti,sysc";
188			reg = <0x28000 0x4>,
189			      <0x28004 0x4>;
190			reg-names = "rev", "sysc";
191			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
192					<SYSC_IDLE_NO>,
193					<SYSC_IDLE_SMART>,
194					<SYSC_IDLE_SMART_WKUP>;
195			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
196			clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
197			clock-names = "fck";
198			#address-cells = <1>;
199			#size-cells = <1>;
200			ranges = <0x0 0x28000 0x1000>,
201				 <0x49028000 0x49028000 0x1000>;
202
203			/*
204			 * Child device unsupported by davinci-mcasp. At least
205			 * RX path is disabled for omap4, and only DIT mode
206			 * works with no I2S. See also old Android kernel
207			 * omap-mcasp driver for more information.
208			 */
209		};
210
211		target-module@2a000 {			/* 0x4012a000, ap 10 0a.0 */
212			compatible = "ti,sysc";
213			status = "disabled";
214			#address-cells = <1>;
215			#size-cells = <1>;
216			ranges = <0x0 0x2a000 0x1000>,
217				 <0x4902a000 0x4902a000 0x1000>;
218		};
219
220		target-module@2e000 {			/* 0x4012e000, ap 12 0c.0 */
221			compatible = "ti,sysc-omap4", "ti,sysc";
222			reg = <0x2e000 0x4>,
223			      <0x2e010 0x4>;
224			reg-names = "rev", "sysc";
225			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
226					 SYSC_OMAP4_SOFTRESET)>;
227			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
228					<SYSC_IDLE_NO>,
229					<SYSC_IDLE_SMART>,
230					<SYSC_IDLE_SMART_WKUP>;
231			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
232			clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
233			clock-names = "fck";
234			#address-cells = <1>;
235			#size-cells = <1>;
236			ranges = <0x0 0x2e000 0x1000>,
237				 <0x4902e000 0x4902e000 0x1000>;
238
239			dmic: dmic@0 {
240				compatible = "ti,omap4-dmic";
241				reg = <0x0 0x7f>, /* MPU private access */
242				      <0x4902e000 0x7f>; /* L3 Interconnect */
243				reg-names = "mpu", "dma";
244				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
245				dmas = <&sdma 67>;
246				dma-names = "up_link";
247				status = "disabled";
248			};
249		};
250
251		target-module@30000 {			/* 0x40130000, ap 14 0e.0 */
252			compatible = "ti,sysc-omap2", "ti,sysc";
253			reg = <0x30000 0x4>,
254			      <0x30010 0x4>,
255			      <0x30014 0x4>;
256			reg-names = "rev", "sysc", "syss";
257			ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
258					 SYSC_OMAP2_SOFTRESET)>;
259			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
260					<SYSC_IDLE_NO>,
261					<SYSC_IDLE_SMART>,
262					<SYSC_IDLE_SMART_WKUP>;
263			ti,syss-mask = <1>;
264			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
265			clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
266			clock-names = "fck";
267			#address-cells = <1>;
268			#size-cells = <1>;
269			ranges = <0x0 0x30000 0x1000>,
270				 <0x49030000 0x49030000 0x1000>;
271
272			wdt3: wdt@0 {
273				compatible = "ti,omap4-wdt", "ti,omap3-wdt";
274				reg = <0x0 0x80>;
275				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
276			};
277		};
278
279		mcpdm_module: target-module@32000 {	/* 0x40132000, ap 16 10.0 */
280			compatible = "ti,sysc-omap4", "ti,sysc";
281			reg = <0x32000 0x4>,
282			      <0x32010 0x4>;
283			reg-names = "rev", "sysc";
284			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
285					 SYSC_OMAP4_SOFTRESET)>;
286			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
287					<SYSC_IDLE_NO>,
288					<SYSC_IDLE_SMART>,
289					<SYSC_IDLE_SMART_WKUP>;
290			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
291			clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
292			clock-names = "fck";
293			#address-cells = <1>;
294			#size-cells = <1>;
295			ranges = <0x0 0x32000 0x1000>,
296				 <0x49032000 0x49032000 0x1000>;
297
298			/* Must be only enabled for boards with pdmclk wired */
299			status = "disabled";
300
301			mcpdm: mcpdm@0 {
302				compatible = "ti,omap4-mcpdm";
303				reg = <0x0 0x7f>, /* MPU private access */
304				      <0x49032000 0x7f>; /* L3 Interconnect */
305				reg-names = "mpu", "dma";
306				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
307				dmas = <&sdma 65>,
308				       <&sdma 66>;
309				dma-names = "up_link", "dn_link";
310			};
311		};
312
313		target-module@38000 {			/* 0x40138000, ap 18 12.0 */
314			compatible = "ti,sysc-omap4-timer", "ti,sysc";
315			reg = <0x38000 0x4>,
316			      <0x38010 0x4>;
317			reg-names = "rev", "sysc";
318			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
319					 SYSC_OMAP4_SOFTRESET)>;
320			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
321					<SYSC_IDLE_NO>,
322					<SYSC_IDLE_SMART>,
323					<SYSC_IDLE_SMART_WKUP>;
324			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
325			clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
326			clock-names = "fck";
327			#address-cells = <1>;
328			#size-cells = <1>;
329			ranges = <0x0 0x38000 0x1000>,
330				 <0x49038000 0x49038000 0x1000>;
331
332			timer5: timer@0 {
333				compatible = "ti,omap4430-timer";
334				reg = <0x00000000 0x80>,
335				      <0x49038000 0x80>;
336				clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>,
337					 <&syc_clk_div_ck>;
338				clock-names = "fck", "timer_sys_ck";
339				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
340				ti,timer-dsp;
341			};
342		};
343
344		target-module@3a000 {			/* 0x4013a000, ap 20 14.0 */
345			compatible = "ti,sysc-omap4-timer", "ti,sysc";
346			reg = <0x3a000 0x4>,
347			      <0x3a010 0x4>;
348			reg-names = "rev", "sysc";
349			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
350					 SYSC_OMAP4_SOFTRESET)>;
351			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
352					<SYSC_IDLE_NO>,
353					<SYSC_IDLE_SMART>,
354					<SYSC_IDLE_SMART_WKUP>;
355			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
356			clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
357			clock-names = "fck";
358			#address-cells = <1>;
359			#size-cells = <1>;
360			ranges = <0x0 0x3a000 0x1000>,
361				 <0x4903a000 0x4903a000 0x1000>;
362
363			timer6: timer@0 {
364				compatible = "ti,omap4430-timer";
365				reg = <0x00000000 0x80>,
366				      <0x4903a000 0x80>;
367				clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>,
368					 <&syc_clk_div_ck>;
369				clock-names = "fck", "timer_sys_ck";
370				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
371				ti,timer-dsp;
372			};
373		};
374
375		target-module@3c000 {			/* 0x4013c000, ap 22 16.0 */
376			compatible = "ti,sysc-omap4-timer", "ti,sysc";
377			reg = <0x3c000 0x4>,
378			      <0x3c010 0x4>;
379			reg-names = "rev", "sysc";
380			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
381					 SYSC_OMAP4_SOFTRESET)>;
382			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
383					<SYSC_IDLE_NO>,
384					<SYSC_IDLE_SMART>,
385					<SYSC_IDLE_SMART_WKUP>;
386			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
387			clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
388			clock-names = "fck";
389			#address-cells = <1>;
390			#size-cells = <1>;
391			ranges = <0x0 0x3c000 0x1000>,
392				 <0x4903c000 0x4903c000 0x1000>;
393
394			timer7: timer@0 {
395				compatible = "ti,omap4430-timer";
396				reg = <0x00000000 0x80>,
397				      <0x4903c000 0x80>;
398				clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>,
399					 <&syc_clk_div_ck>;
400				clock-names = "fck", "timer_sys_ck";
401				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
402				ti,timer-dsp;
403			};
404		};
405
406		target-module@3e000 {			/* 0x4013e000, ap 24 18.0 */
407			compatible = "ti,sysc-omap4-timer", "ti,sysc";
408			reg = <0x3e000 0x4>,
409			      <0x3e010 0x4>;
410			reg-names = "rev", "sysc";
411			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
412					 SYSC_OMAP4_SOFTRESET)>;
413			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
414					<SYSC_IDLE_NO>,
415					<SYSC_IDLE_SMART>,
416					<SYSC_IDLE_SMART_WKUP>;
417			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
418			clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
419			clock-names = "fck";
420			#address-cells = <1>;
421			#size-cells = <1>;
422			ranges = <0x0 0x3e000 0x1000>,
423				 <0x4903e000 0x4903e000 0x1000>;
424
425			timer8: timer@0 {
426				compatible = "ti,omap4430-timer";
427				reg = <0x00000000 0x80>,
428				      <0x4903e000 0x80>;
429				clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>,
430					 <&syc_clk_div_ck>;
431				clock-names = "fck", "timer_sys_ck";
432				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
433				ti,timer-pwm;
434				ti,timer-dsp;
435			};
436		};
437
438		target-module@80000 {			/* 0x40180000, ap 26 1a.0 */
439			compatible = "ti,sysc";
440			status = "disabled";
441			#address-cells = <1>;
442			#size-cells = <1>;
443			ranges = <0x0 0x80000 0x10000>,
444				 <0x49080000 0x49080000 0x10000>;
445		};
446
447		target-module@a0000 {			/* 0x401a0000, ap 28 1c.0 */
448			compatible = "ti,sysc";
449			status = "disabled";
450			#address-cells = <1>;
451			#size-cells = <1>;
452			ranges = <0x0 0xa0000 0x10000>,
453				 <0x490a0000 0x490a0000 0x10000>;
454		};
455
456		target-module@c0000 {			/* 0x401c0000, ap 30 1e.0 */
457			compatible = "ti,sysc";
458			status = "disabled";
459			#address-cells = <1>;
460			#size-cells = <1>;
461			ranges = <0x0 0xc0000 0x10000>,
462				 <0x490c0000 0x490c0000 0x10000>;
463		};
464
465		target-module@f1000 {			/* 0x401f1000, ap 32 20.0 */
466			compatible = "ti,sysc-omap4", "ti,sysc";
467			reg = <0xf1000 0x4>,
468			      <0xf1010 0x4>;
469			reg-names = "rev", "sysc";
470			ti,sysc-midle = <SYSC_IDLE_FORCE>,
471					<SYSC_IDLE_NO>,
472					<SYSC_IDLE_SMART>,
473					<SYSC_IDLE_SMART_WKUP>;
474			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
475					<SYSC_IDLE_NO>,
476					<SYSC_IDLE_SMART>;
477			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
478			clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
479			clock-names = "fck";
480			#address-cells = <1>;
481			#size-cells = <1>;
482			ranges = <0x0 0xf1000 0x1000>,
483				 <0x490f1000 0x490f1000 0x1000>;
484
485			/*
486			 * No child device binding or driver in mainline.
487			 * See Android tree and related upstreaming efforts
488			 * for the old driver.
489			 */
490		};
491	};
492};
493
494