1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd. 3 */ 4 5 #include "ngbe_phy.h" 6 7 #ifndef _NGBE_PHY_RTL_H_ 8 #define _NGBE_PHY_RTL_H_ 9 10 #define NGBE_PHYID_RTL 0x001CC800U 11 12 /* Page 0 */ 13 #define RTL_DEV_ZERO 0 14 #define RTL_BMCR 0x0 15 #define RTL_BMCR_RESET MS16(15, 0x1) 16 #define RTL_BMCR_SPEED_SELECT0 MS16(13, 0x1) 17 #define RTL_BMCR_ANE MS16(12, 0x1) 18 #define RTL_BMCR_RESTART_AN MS16(9, 0x1) 19 #define RTL_BMCR_DUPLEX MS16(8, 0x1) 20 #define RTL_BMCR_SPEED_SELECT1 MS16(6, 0x1) 21 #define RTL_BMSR 0x1 22 #define RTL_BMSR_ANC MS16(5, 0x1) 23 #define RTL_ID1_OFFSET 0x2 24 #define RTL_ID2_OFFSET 0x3 25 #define RTL_ID_MASK 0xFFFFFC00U 26 #define RTL_ANAR 0x4 27 #define RTL_ANAR_APAUSE MS16(11, 0x1) 28 #define RTL_ANAR_PAUSE MS16(10, 0x1) 29 #define RTL_ANAR_100F MS16(8, 0x1) 30 #define RTL_ANAR_100H MS16(7, 0x1) 31 #define RTL_ANAR_10F MS16(6, 0x1) 32 #define RTL_ANAR_10H MS16(5, 0x1) 33 #define RTL_ANLPAR 0x5 34 #define RTL_ANLPAR_LP MS16(10, 0x3) 35 #define RTL_GBCR 0x9 36 #define RTL_GBCR_1000F MS16(9, 0x1) 37 /* Page 0xa42*/ 38 #define RTL_GSR 0x10 39 #define RTL_GSR_ST MS16(0, 0x7) 40 #define RTL_GSR_ST_LANON MS16(0, 0x3) 41 #define RTL_INER 0x12 42 #define RTL_INER_LSC MS16(4, 0x1) 43 #define RTL_INER_ANC MS16(3, 0x1) 44 /* Page 0xa43*/ 45 #define RTL_PHYSR 0x1A 46 #define RTL_PHYSR_SPEED_MASK MS16(4, 0x3) 47 #define RTL_PHYSR_SPEED_RES LS16(3, 4, 0x3) 48 #define RTL_PHYSR_SPEED_1000M LS16(2, 4, 0x3) 49 #define RTL_PHYSR_SPEED_100M LS16(1, 4, 0x3) 50 #define RTL_PHYSR_SPEED_10M LS16(0, 4, 0x3) 51 #define RTL_PHYSR_DP MS16(3, 0x1) 52 #define RTL_PHYSR_RTLS MS16(2, 0x1) 53 #define RTL_INSR 0x1D 54 #define RTL_INSR_ACCESS MS16(5, 0x1) 55 #define RTL_INSR_LSC MS16(4, 0x1) 56 #define RTL_INSR_ANC MS16(3, 0x1) 57 /* Page 0xa46*/ 58 #define RTL_SCR 0x14 59 #define RTL_SCR_EXTINI MS16(1, 0x1) 60 #define RTL_SCR_EFUSE MS16(0, 0x1) 61 /* Page 0xa47*/ 62 /* Page 0xd04*/ 63 #define RTL_LCR 0x10 64 #define RTL_EEELCR 0x11 65 #define RTL_LPCR 0x12 66 67 /* INTERNAL PHY CONTROL */ 68 #define RTL_PAGE_SELECT 31 69 #define NGBE_INTERNAL_PHY_OFFSET_MAX 32 70 #define NGBE_INTERNAL_PHY_ID 0x000732 71 72 #define NGBE_INTPHY_LED0 0x0010 73 #define NGBE_INTPHY_LED1 0x0040 74 #define NGBE_INTPHY_LED2 0x2000 75 76 s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, 77 u16 *phy_data); 78 s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, 79 u16 phy_data); 80 81 s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw, 82 u32 speed, bool autoneg_wait_to_complete); 83 84 s32 ngbe_init_phy_rtl(struct ngbe_hw *hw); 85 s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw); 86 s32 ngbe_get_phy_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit); 87 s32 ngbe_get_phy_lp_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit); 88 s32 ngbe_set_phy_pause_adv_rtl(struct ngbe_hw *hw, u16 pause_bit); 89 s32 ngbe_check_phy_link_rtl(struct ngbe_hw *hw, 90 u32 *speed, bool *link_up); 91 92 #endif /* _NGBE_PHY_RTL_H_ */ 93