1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2011 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * Developed by Ben Gray <[email protected]>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /**
35 * The ARM Cortex-A9 core can support a global timer plus a private and
36 * watchdog timer per core. This driver reserves memory and interrupt
37 * resources for accessing both timer register sets, these resources are
38 * stored globally and used to setup the timecount and eventtimer.
39 *
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
42 *
43 *
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
45 */
46
47 #include <sys/cdefs.h>
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/bus.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/malloc.h>
54 #include <sys/rman.h>
55 #include <sys/timeet.h>
56 #include <sys/timetc.h>
57 #include <sys/watchdog.h>
58 #include <machine/bus.h>
59 #include <machine/cpu.h>
60 #include <machine/intr.h>
61
62 #include <machine/machdep.h> /* For arm_set_delay */
63
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
67
68 #include <machine/bus.h>
69
70 #include <arm/arm/mpcore_timervar.h>
71
72 /* Private (per-CPU) timer register map */
73 #define PRV_TIMER_LOAD 0x0000
74 #define PRV_TIMER_COUNT 0x0004
75 #define PRV_TIMER_CTRL 0x0008
76 #define PRV_TIMER_INTR 0x000C
77
78 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8
79 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
80 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1)
81 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
82
83 #define PRV_TIMER_INTR_EVENT (1UL << 0)
84
85 /* Global timer register map */
86 #define GBL_TIMER_COUNT_LOW 0x0000
87 #define GBL_TIMER_COUNT_HIGH 0x0004
88 #define GBL_TIMER_CTRL 0x0008
89 #define GBL_TIMER_INTR 0x000C
90
91 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8
92 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
93 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
94 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
95 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
96
97 #define GBL_TIMER_INTR_EVENT (1UL << 0)
98
99 struct arm_tmr_softc {
100 device_t dev;
101 int irqrid;
102 int memrid;
103 struct resource * gbl_mem;
104 struct resource * prv_mem;
105 struct resource * prv_irq;
106 uint64_t clkfreq;
107 struct eventtimer et;
108 };
109
110 static struct eventtimer *arm_tmr_et;
111 static struct timecounter *arm_tmr_tc;
112 static uint64_t arm_tmr_freq;
113 static boolean_t arm_tmr_freq_varies;
114
115 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
116 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
117 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
118 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)
119
120 static void arm_tmr_delay(int, void *);
121
122 static timecounter_get_t arm_tmr_get_timecount;
123
124 static struct timecounter arm_tmr_timecount = {
125 .tc_name = "MPCore",
126 .tc_get_timecount = arm_tmr_get_timecount,
127 .tc_poll_pps = NULL,
128 .tc_counter_mask = ~0u,
129 .tc_frequency = 0,
130 .tc_quality = 800,
131 };
132
133 #define TMR_GBL 0x01
134 #define TMR_PRV 0x02
135 #define TMR_BOTH (TMR_GBL | TMR_PRV)
136 #define TMR_NONE 0
137
138 static struct ofw_compat_data compat_data[] = {
139 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
140 {"arm,cortex-a9-global-timer", TMR_GBL},
141 {"arm,cortex-a5-global-timer", TMR_GBL},
142 {"arm,cortex-a9-twd-timer", TMR_PRV},
143 {"arm,cortex-a5-twd-timer", TMR_PRV},
144 {"arm,arm11mp-twd-timer", TMR_PRV},
145 {NULL, TMR_NONE}
146 };
147
148 /**
149 * arm_tmr_get_timecount - reads the timecount (global) timer
150 * @tc: pointer to arm_tmr_timecount struct
151 *
152 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
153 * so (for now?) ignore the upper 32-bits.
154 *
155 * RETURNS
156 * The lower 32-bits of the counter.
157 */
158 static unsigned
arm_tmr_get_timecount(struct timecounter * tc)159 arm_tmr_get_timecount(struct timecounter *tc)
160 {
161 struct arm_tmr_softc *sc;
162
163 sc = tc->tc_priv;
164 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW));
165 }
166
167 /**
168 * arm_tmr_start - starts the eventtimer (private) timer
169 * @et: pointer to eventtimer struct
170 * @first: the number of seconds and fractional sections to trigger in
171 * @period: the period (in seconds and fractional sections) to set
172 *
173 * If the eventtimer is required to be in oneshot mode, period will be
174 * NULL and first will point to the time to trigger. If in periodic mode
175 * period will contain the time period and first may optionally contain
176 * the time for the first period.
177 *
178 * RETURNS
179 * Always returns 0
180 */
181 static int
arm_tmr_start(struct eventtimer * et,sbintime_t first,sbintime_t period)182 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
183 {
184 struct arm_tmr_softc *sc;
185 uint32_t load, count;
186 uint32_t ctrl;
187
188 sc = et->et_priv;
189 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
190 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
191
192 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
193
194 if (period != 0) {
195 load = ((uint32_t)et->et_frequency * period) >> 32;
196 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
197 } else
198 load = 0;
199
200 if (first != 0)
201 count = (uint32_t)((et->et_frequency * first) >> 32);
202 else
203 count = load;
204
205 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load);
206 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count);
207 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);
208
209 return (0);
210 }
211
212 /**
213 * arm_tmr_stop - stops the eventtimer (private) timer
214 * @et: pointer to eventtimer struct
215 *
216 * Simply stops the private timer by clearing all bits in the ctrl register.
217 *
218 * RETURNS
219 * Always returns 0
220 */
221 static int
arm_tmr_stop(struct eventtimer * et)222 arm_tmr_stop(struct eventtimer *et)
223 {
224 struct arm_tmr_softc *sc;
225
226 sc = et->et_priv;
227 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
228 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
229 return (0);
230 }
231
232 /**
233 * arm_tmr_intr - ISR for the eventtimer (private) timer
234 * @arg: pointer to arm_tmr_softc struct
235 *
236 * Clears the event register and then calls the eventtimer callback.
237 *
238 * RETURNS
239 * Always returns FILTER_HANDLED
240 */
241 static int
arm_tmr_intr(void * arg)242 arm_tmr_intr(void *arg)
243 {
244 struct arm_tmr_softc *sc;
245
246 sc = arg;
247 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
248 if (sc->et.et_active)
249 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
250 return (FILTER_HANDLED);
251 }
252
253 /**
254 * arm_tmr_probe - timer probe routine
255 * @dev: new device
256 *
257 * The probe function returns success when probed with the fdt compatible
258 * string set to "arm,mpcore-timers".
259 *
260 * RETURNS
261 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO.
262 */
263 static int
arm_tmr_probe(device_t dev)264 arm_tmr_probe(device_t dev)
265 {
266
267 if (!ofw_bus_status_okay(dev))
268 return (ENXIO);
269
270 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE)
271 return (ENXIO);
272
273 device_set_desc(dev, "ARM MPCore Timers");
274 return (BUS_PROBE_DEFAULT);
275 }
276
277 static int
attach_tc(struct arm_tmr_softc * sc)278 attach_tc(struct arm_tmr_softc *sc)
279 {
280 int rid;
281
282 if (arm_tmr_tc != NULL)
283 return (EBUSY);
284
285 rid = sc->memrid;
286 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
287 RF_ACTIVE);
288 if (sc->gbl_mem == NULL) {
289 device_printf(sc->dev, "could not allocate gbl mem resources\n");
290 return (ENXIO);
291 }
292 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000);
293
294 arm_tmr_timecount.tc_frequency = sc->clkfreq;
295 arm_tmr_timecount.tc_priv = sc;
296 tc_init(&arm_tmr_timecount);
297 arm_tmr_tc = &arm_tmr_timecount;
298
299 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
300
301 return (0);
302 }
303
304 static int
attach_et(struct arm_tmr_softc * sc)305 attach_et(struct arm_tmr_softc *sc)
306 {
307 void *ihl;
308 int irid, mrid;
309
310 if (arm_tmr_et != NULL)
311 return (EBUSY);
312
313 mrid = sc->memrid;
314 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid,
315 RF_ACTIVE);
316 if (sc->prv_mem == NULL) {
317 device_printf(sc->dev, "could not allocate prv mem resources\n");
318 return (ENXIO);
319 }
320 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000);
321
322 irid = sc->irqrid;
323 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE);
324 if (sc->prv_irq == NULL) {
325 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
326 device_printf(sc->dev, "could not allocate prv irq resources\n");
327 return (ENXIO);
328 }
329
330 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr,
331 NULL, sc, &ihl) != 0) {
332 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
333 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq);
334 device_printf(sc->dev, "unable to setup the et irq handler.\n");
335 return (ENXIO);
336 }
337
338 /*
339 * Setup and register the eventtimer. Most event timers set their min
340 * and max period values to some value calculated from the clock
341 * frequency. We might not know yet what our runtime clock frequency
342 * will be, so we just use some safe values. A max of 2 seconds ensures
343 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
344 * we won't overflow our 32-bit timer count register. A min of 20
345 * nanoseconds is pretty much completely arbitrary.
346 */
347 sc->et.et_name = "MPCore";
348 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
349 sc->et.et_quality = 1000;
350 sc->et.et_frequency = sc->clkfreq;
351 sc->et.et_min_period = nstosbt(20);
352 sc->et.et_max_period = 2 * SBT_1S;
353 sc->et.et_start = arm_tmr_start;
354 sc->et.et_stop = arm_tmr_stop;
355 sc->et.et_priv = sc;
356 et_register(&sc->et);
357 arm_tmr_et = &sc->et;
358
359 return (0);
360 }
361
362 /**
363 * arm_tmr_attach - attaches the timer to the simplebus
364 * @dev: new device
365 *
366 * Reserves memory and interrupt resources, stores the softc structure
367 * globally and registers both the timecount and eventtimer objects.
368 *
369 * RETURNS
370 * Zero on success or ENXIO if an error occuried.
371 */
372 static int
arm_tmr_attach(device_t dev)373 arm_tmr_attach(device_t dev)
374 {
375 struct arm_tmr_softc *sc;
376 phandle_t node;
377 pcell_t clock;
378 int et_err, tc_err, tmrtype;
379
380 sc = device_get_softc(dev);
381 sc->dev = dev;
382
383 if (arm_tmr_freq_varies) {
384 sc->clkfreq = arm_tmr_freq;
385 } else {
386 if (arm_tmr_freq != 0) {
387 sc->clkfreq = arm_tmr_freq;
388 } else {
389 /* Get the base clock frequency */
390 node = ofw_bus_get_node(dev);
391 if ((OF_getencprop(node, "clock-frequency", &clock,
392 sizeof(clock))) <= 0) {
393 device_printf(dev, "missing clock-frequency "
394 "attribute in FDT\n");
395 return (ENXIO);
396 }
397 sc->clkfreq = clock;
398 }
399 }
400
401 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
402 tc_err = ENXIO;
403 et_err = ENXIO;
404
405 /*
406 * If we're handling the global timer and it is fixed-frequency, set it
407 * up to use as a timecounter. If it's variable frequency it won't work
408 * as a timecounter. We also can't use it for DELAY(), so hopefully the
409 * platform provides its own implementation. If it doesn't, ours will
410 * get used, but since the frequency isn't set, it will only use the
411 * bogus loop counter.
412 */
413 if (tmrtype & TMR_GBL) {
414 if (!arm_tmr_freq_varies)
415 tc_err = attach_tc(sc);
416 else if (bootverbose)
417 device_printf(sc->dev,
418 "not using variable-frequency device as timecounter\n");
419 sc->memrid++;
420 sc->irqrid++;
421 }
422
423 /* If we are handling the private timer, set it up as an eventtimer. */
424 if (tmrtype & TMR_PRV) {
425 et_err = attach_et(sc);
426 }
427
428 /*
429 * If we didn't successfully set up a timecounter or eventtimer then we
430 * didn't actually attach at all, return error.
431 */
432 if (tc_err != 0 && et_err != 0) {
433 return (ENXIO);
434 }
435
436 #ifdef PLATFORM
437 /*
438 * We can register as the DELAY() implementation only if we successfully
439 * set up the global timer.
440 */
441 if (tc_err == 0)
442 arm_set_delay(arm_tmr_delay, sc);
443 #endif
444
445 return (0);
446 }
447
448 static device_method_t arm_tmr_methods[] = {
449 DEVMETHOD(device_probe, arm_tmr_probe),
450 DEVMETHOD(device_attach, arm_tmr_attach),
451 { 0, 0 }
452 };
453
454 static driver_t arm_tmr_driver = {
455 "mp_tmr",
456 arm_tmr_methods,
457 sizeof(struct arm_tmr_softc),
458 };
459
460 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, 0, 0,
461 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
462 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, 0, 0,
463 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
464
465 /*
466 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
467 * frequency. When the CPU frequency changes due to power-saving or thermal
468 * management, the platform-specific code that causes the frequency change calls
469 * this routine to inform the clock driver, and we in turn inform the event
470 * timer system, which actually updates the value in et->frequency for us and
471 * reschedules the current event(s) in a way that's atomic with respect to
472 * start/stop/intr code that may be running on various CPUs at the time of the
473 * call.
474 *
475 * This routine can also be called by a platform's early init code. If the
476 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
477 * to register as an eventtimer, but not a timecounter. If the value passed in
478 * is any other non-zero value it is used as the fixed frequency for the timer.
479 */
480 void
arm_tmr_change_frequency(uint64_t newfreq)481 arm_tmr_change_frequency(uint64_t newfreq)
482 {
483
484 if (newfreq == ARM_TMR_FREQUENCY_VARIES) {
485 arm_tmr_freq_varies = true;
486 return;
487 }
488
489 arm_tmr_freq = newfreq;
490 if (arm_tmr_et != NULL)
491 et_change_frequency(arm_tmr_et, newfreq);
492 }
493
494 static void
arm_tmr_delay(int usec,void * arg)495 arm_tmr_delay(int usec, void *arg)
496 {
497 struct arm_tmr_softc *sc = arg;
498 int32_t counts_per_usec;
499 int32_t counts;
500 uint32_t first, last;
501
502 /* Get the number of times to count */
503 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
504
505 /*
506 * Clamp the timeout at a maximum value (about 32 seconds with
507 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
508 * near that length of time and if they are, they should be hung
509 * out to dry.
510 */
511 if (usec >= (0x80000000U / counts_per_usec))
512 counts = (0x80000000U / counts_per_usec) - 1;
513 else
514 counts = usec * counts_per_usec;
515
516 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
517
518 while (counts > 0) {
519 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
520 counts -= (int32_t)(last - first);
521 first = last;
522 }
523 }
524
525 #ifndef PLATFORM
526 /**
527 * DELAY - Delay for at least usec microseconds.
528 * @usec: number of microseconds to delay by
529 *
530 * This function is called all over the kernel and is suppose to provide a
531 * consistent delay. This function may also be called before the console
532 * is setup so no printf's can be called here.
533 *
534 * RETURNS:
535 * nothing
536 */
537 void
DELAY(int usec)538 DELAY(int usec)
539 {
540 struct arm_tmr_softc *sc;
541 int32_t counts;
542
543 TSENTER();
544 /* Check the timers are setup, if not just use a for loop for the meantime */
545 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) {
546 for (; usec > 0; usec--)
547 for (counts = 200; counts > 0; counts--)
548 cpufunc_nullop(); /* Prevent gcc from optimizing
549 * out the loop
550 */
551 } else {
552 sc = arm_tmr_tc->tc_priv;
553 arm_tmr_delay(usec, sc);
554 }
555 TSEXIT();
556 }
557 #endif
558