1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef _LIO_STRUCT_H_ 6 #define _LIO_STRUCT_H_ 7 8 #include <stdio.h> 9 #include <stdint.h> 10 #include <sys/queue.h> 11 12 #include <rte_spinlock.h> 13 #include <rte_atomic.h> 14 15 #include "lio_hw_defs.h" 16 17 struct lio_stailq_node { 18 STAILQ_ENTRY(lio_stailq_node) entries; 19 }; 20 21 STAILQ_HEAD(lio_stailq_head, lio_stailq_node); 22 23 struct lio_version { 24 uint16_t major; 25 uint16_t minor; 26 uint16_t micro; 27 uint16_t reserved; 28 }; 29 30 /** Input Queue statistics. Each input queue has four stats fields. */ 31 struct lio_iq_stats { 32 uint64_t instr_posted; /**< Instructions posted to this queue. */ 33 uint64_t instr_processed; /**< Instructions processed in this queue. */ 34 uint64_t instr_dropped; /**< Instructions that could not be processed */ 35 uint64_t bytes_sent; /**< Bytes sent through this queue. */ 36 uint64_t tx_done; /**< Num of packets sent to network. */ 37 uint64_t tx_iq_busy; /**< Num of times this iq was found to be full. */ 38 uint64_t tx_dropped; /**< Num of pkts dropped due to xmitpath errors. */ 39 uint64_t tx_tot_bytes; /**< Total count of bytes sent to network. */ 40 }; 41 42 /** Output Queue statistics. Each output queue has four stats fields. */ 43 struct lio_droq_stats { 44 /** Number of packets received in this queue. */ 45 uint64_t pkts_received; 46 47 /** Bytes received by this queue. */ 48 uint64_t bytes_received; 49 50 /** Packets dropped due to no memory available. */ 51 uint64_t dropped_nomem; 52 53 /** Packets dropped due to large number of pkts to process. */ 54 uint64_t dropped_toomany; 55 56 /** Number of packets sent to stack from this queue. */ 57 uint64_t rx_pkts_received; 58 59 /** Number of Bytes sent to stack from this queue. */ 60 uint64_t rx_bytes_received; 61 62 /** Num of Packets dropped due to receive path failures. */ 63 uint64_t rx_dropped; 64 65 /** Num of vxlan packets received; */ 66 uint64_t rx_vxlan; 67 68 /** Num of failures of rte_pktmbuf_alloc() */ 69 uint64_t rx_alloc_failure; 70 71 }; 72 73 /** The Descriptor Ring Output Queue structure. 74 * This structure has all the information required to implement a 75 * DROQ. 76 */ 77 struct lio_droq { 78 /** A spinlock to protect access to this ring. */ 79 rte_spinlock_t lock; 80 81 uint32_t q_no; 82 83 uint32_t pkt_count; 84 85 struct lio_device *lio_dev; 86 87 /** The 8B aligned descriptor ring starts at this address. */ 88 struct lio_droq_desc *desc_ring; 89 90 /** Index in the ring where the driver should read the next packet */ 91 uint32_t read_idx; 92 93 /** Index in the ring where Octeon will write the next packet */ 94 uint32_t write_idx; 95 96 /** Index in the ring where the driver will refill the descriptor's 97 * buffer 98 */ 99 uint32_t refill_idx; 100 101 /** Packets pending to be processed */ 102 rte_atomic64_t pkts_pending; 103 104 /** Number of descriptors in this ring. */ 105 uint32_t nb_desc; 106 107 /** The number of descriptors pending refill. */ 108 uint32_t refill_count; 109 110 uint32_t refill_threshold; 111 112 /** The 8B aligned info ptrs begin from this address. */ 113 struct lio_droq_info *info_list; 114 115 /** The receive buffer list. This list has the virtual addresses of the 116 * buffers. 117 */ 118 struct lio_recv_buffer *recv_buf_list; 119 120 /** The size of each buffer pointed by the buffer pointer. */ 121 uint32_t buffer_size; 122 123 /** Pointer to the mapped packet credit register. 124 * Host writes number of info/buffer ptrs available to this register 125 */ 126 void *pkts_credit_reg; 127 128 /** Pointer to the mapped packet sent register. 129 * Octeon writes the number of packets DMA'ed to host memory 130 * in this register. 131 */ 132 void *pkts_sent_reg; 133 134 /** Statistics for this DROQ. */ 135 struct lio_droq_stats stats; 136 137 /** DMA mapped address of the DROQ descriptor ring. */ 138 size_t desc_ring_dma; 139 140 /** Info ptr list are allocated at this virtual address. */ 141 size_t info_base_addr; 142 143 /** DMA mapped address of the info list */ 144 size_t info_list_dma; 145 146 /** Allocated size of info list. */ 147 uint32_t info_alloc_size; 148 149 /** Memory zone **/ 150 const struct rte_memzone *desc_ring_mz; 151 const struct rte_memzone *info_mz; 152 struct rte_mempool *mpool; 153 }; 154 155 /** Receive Header */ 156 union octeon_rh { 157 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 158 uint64_t rh64; 159 struct { 160 uint64_t opcode : 4; 161 uint64_t subcode : 8; 162 uint64_t len : 3; /** additional 64-bit words */ 163 uint64_t reserved : 17; 164 uint64_t ossp : 32; /** opcode/subcode specific parameters */ 165 } r; 166 struct { 167 uint64_t opcode : 4; 168 uint64_t subcode : 8; 169 uint64_t len : 3; /** additional 64-bit words */ 170 uint64_t extra : 28; 171 uint64_t vlan : 12; 172 uint64_t priority : 3; 173 uint64_t csum_verified : 3; /** checksum verified. */ 174 uint64_t has_hwtstamp : 1; /** Has hardware timestamp.1 = yes.*/ 175 uint64_t encap_on : 1; 176 uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */ 177 } r_dh; 178 struct { 179 uint64_t opcode : 4; 180 uint64_t subcode : 8; 181 uint64_t len : 3; /** additional 64-bit words */ 182 uint64_t reserved : 8; 183 uint64_t extra : 25; 184 uint64_t gmxport : 16; 185 } r_nic_info; 186 #else 187 uint64_t rh64; 188 struct { 189 uint64_t ossp : 32; /** opcode/subcode specific parameters */ 190 uint64_t reserved : 17; 191 uint64_t len : 3; /** additional 64-bit words */ 192 uint64_t subcode : 8; 193 uint64_t opcode : 4; 194 } r; 195 struct { 196 uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */ 197 uint64_t encap_on : 1; 198 uint64_t has_hwtstamp : 1; /** 1 = has hwtstamp */ 199 uint64_t csum_verified : 3; /** checksum verified. */ 200 uint64_t priority : 3; 201 uint64_t vlan : 12; 202 uint64_t extra : 28; 203 uint64_t len : 3; /** additional 64-bit words */ 204 uint64_t subcode : 8; 205 uint64_t opcode : 4; 206 } r_dh; 207 struct { 208 uint64_t gmxport : 16; 209 uint64_t extra : 25; 210 uint64_t reserved : 8; 211 uint64_t len : 3; /** additional 64-bit words */ 212 uint64_t subcode : 8; 213 uint64_t opcode : 4; 214 } r_nic_info; 215 #endif 216 }; 217 218 #define OCTEON_RH_SIZE (sizeof(union octeon_rh)) 219 220 /** The txpciq info passed to host from the firmware */ 221 union octeon_txpciq { 222 uint64_t txpciq64; 223 224 struct { 225 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 226 uint64_t q_no : 8; 227 uint64_t port : 8; 228 uint64_t pkind : 6; 229 uint64_t use_qpg : 1; 230 uint64_t qpg : 11; 231 uint64_t aura_num : 10; 232 uint64_t reserved : 20; 233 #else 234 uint64_t reserved : 20; 235 uint64_t aura_num : 10; 236 uint64_t qpg : 11; 237 uint64_t use_qpg : 1; 238 uint64_t pkind : 6; 239 uint64_t port : 8; 240 uint64_t q_no : 8; 241 #endif 242 } s; 243 }; 244 245 /** The instruction (input) queue. 246 * The input queue is used to post raw (instruction) mode data or packet 247 * data to Octeon device from the host. Each input queue for 248 * a LIO device has one such structure to represent it. 249 */ 250 struct lio_instr_queue { 251 /** A spinlock to protect access to the input ring. */ 252 rte_spinlock_t lock; 253 254 rte_spinlock_t post_lock; 255 256 struct lio_device *lio_dev; 257 258 uint32_t pkt_in_done; 259 260 rte_atomic64_t iq_flush_running; 261 262 /** Flag that indicates if the queue uses 64 byte commands. */ 263 uint32_t iqcmd_64B:1; 264 265 /** Queue info. */ 266 union octeon_txpciq txpciq; 267 268 uint32_t rsvd:17; 269 270 uint32_t status:8; 271 272 /** Number of descriptors in this ring. */ 273 uint32_t nb_desc; 274 275 /** Index in input ring where the driver should write the next packet */ 276 uint32_t host_write_index; 277 278 /** Index in input ring where Octeon is expected to read the next 279 * packet. 280 */ 281 uint32_t lio_read_index; 282 283 /** This index aids in finding the window in the queue where Octeon 284 * has read the commands. 285 */ 286 uint32_t flush_index; 287 288 /** This field keeps track of the instructions pending in this queue. */ 289 rte_atomic64_t instr_pending; 290 291 /** Pointer to the Virtual Base addr of the input ring. */ 292 uint8_t *base_addr; 293 294 struct lio_request_list *request_list; 295 296 /** Octeon doorbell register for the ring. */ 297 void *doorbell_reg; 298 299 /** Octeon instruction count register for this ring. */ 300 void *inst_cnt_reg; 301 302 /** Number of instructions pending to be posted to Octeon. */ 303 uint32_t fill_cnt; 304 305 /** Statistics for this input queue. */ 306 struct lio_iq_stats stats; 307 308 /** DMA mapped base address of the input descriptor ring. */ 309 uint64_t base_addr_dma; 310 311 /** Application context */ 312 void *app_ctx; 313 314 /* network stack queue index */ 315 int q_index; 316 317 /* Memory zone */ 318 const struct rte_memzone *iq_mz; 319 }; 320 321 /** This structure is used by driver to store information required 322 * to free the mbuff when the packet has been fetched by Octeon. 323 * Bytes offset below assume worst-case of a 64-bit system. 324 */ 325 struct lio_buf_free_info { 326 /** Bytes 1-8. Pointer to network device private structure. */ 327 struct lio_device *lio_dev; 328 329 /** Bytes 9-16. Pointer to mbuff. */ 330 struct rte_mbuf *mbuf; 331 332 /** Bytes 17-24. Pointer to gather list. */ 333 struct lio_gather *g; 334 335 /** Bytes 25-32. Physical address of mbuf->data or gather list. */ 336 uint64_t dptr; 337 338 /** Bytes 33-47. Piggybacked soft command, if any */ 339 struct lio_soft_command *sc; 340 341 /** Bytes 48-63. iq no */ 342 uint64_t iq_no; 343 }; 344 345 /* The Scatter-Gather List Entry. The scatter or gather component used with 346 * input instruction has this format. 347 */ 348 struct lio_sg_entry { 349 /** The first 64 bit gives the size of data in each dptr. */ 350 union { 351 uint16_t size[4]; 352 uint64_t size64; 353 } u; 354 355 /** The 4 dptr pointers for this entry. */ 356 uint64_t ptr[4]; 357 }; 358 359 #define LIO_SG_ENTRY_SIZE (sizeof(struct lio_sg_entry)) 360 361 /** Structure of a node in list of gather components maintained by 362 * driver for each network device. 363 */ 364 struct lio_gather { 365 /** List manipulation. Next and prev pointers. */ 366 struct lio_stailq_node list; 367 368 /** Size of the gather component at sg in bytes. */ 369 int sg_size; 370 371 /** Number of bytes that sg was adjusted to make it 8B-aligned. */ 372 int adjust; 373 374 /** Gather component that can accommodate max sized fragment list 375 * received from the IP layer. 376 */ 377 struct lio_sg_entry *sg; 378 }; 379 380 struct lio_rss_ctx { 381 uint16_t hash_key_size; 382 uint8_t hash_key[LIO_RSS_MAX_KEY_SZ]; 383 /* Ideally a factor of number of queues */ 384 uint8_t itable[LIO_RSS_MAX_TABLE_SZ]; 385 uint8_t itable_size; 386 uint8_t ip; 387 uint8_t tcp_hash; 388 uint8_t ipv6; 389 uint8_t ipv6_tcp_hash; 390 uint8_t ipv6_ex; 391 uint8_t ipv6_tcp_ex_hash; 392 uint8_t hash_disable; 393 }; 394 395 struct lio_io_enable { 396 uint64_t iq; 397 uint64_t oq; 398 uint64_t iq64B; 399 }; 400 401 struct lio_fn_list { 402 void (*setup_iq_regs)(struct lio_device *, uint32_t); 403 void (*setup_oq_regs)(struct lio_device *, uint32_t); 404 405 int (*setup_mbox)(struct lio_device *); 406 void (*free_mbox)(struct lio_device *); 407 408 int (*setup_device_regs)(struct lio_device *); 409 int (*enable_io_queues)(struct lio_device *); 410 void (*disable_io_queues)(struct lio_device *); 411 }; 412 413 struct lio_pf_vf_hs_word { 414 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 415 /** PKIND value assigned for the DPI interface */ 416 uint64_t pkind : 8; 417 418 /** OCTEON core clock multiplier */ 419 uint64_t core_tics_per_us : 16; 420 421 /** OCTEON coprocessor clock multiplier */ 422 uint64_t coproc_tics_per_us : 16; 423 424 /** app that currently running on OCTEON */ 425 uint64_t app_mode : 8; 426 427 /** RESERVED */ 428 uint64_t reserved : 16; 429 430 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 431 432 /** RESERVED */ 433 uint64_t reserved : 16; 434 435 /** app that currently running on OCTEON */ 436 uint64_t app_mode : 8; 437 438 /** OCTEON coprocessor clock multiplier */ 439 uint64_t coproc_tics_per_us : 16; 440 441 /** OCTEON core clock multiplier */ 442 uint64_t core_tics_per_us : 16; 443 444 /** PKIND value assigned for the DPI interface */ 445 uint64_t pkind : 8; 446 #endif 447 }; 448 449 struct lio_sriov_info { 450 /** Number of rings assigned to VF */ 451 uint32_t rings_per_vf; 452 453 /** Number of VF devices enabled */ 454 uint32_t num_vfs; 455 }; 456 457 /* Head of a response list */ 458 struct lio_response_list { 459 /** List structure to add delete pending entries to */ 460 struct lio_stailq_head head; 461 462 /** A lock for this response list */ 463 rte_spinlock_t lock; 464 465 rte_atomic64_t pending_req_count; 466 }; 467 468 /* Structure to define the configuration attributes for each Input queue. */ 469 struct lio_iq_config { 470 /* Max number of IQs available */ 471 uint8_t max_iqs; 472 473 /** Pending list size (usually set to the sum of the size of all Input 474 * queues) 475 */ 476 uint32_t pending_list_size; 477 478 /** Command size - 32 or 64 bytes */ 479 uint32_t instr_type; 480 }; 481 482 /* Structure to define the configuration attributes for each Output queue. */ 483 struct lio_oq_config { 484 /* Max number of OQs available */ 485 uint8_t max_oqs; 486 487 /** If set, the Output queue uses info-pointer mode. (Default: 1 ) */ 488 uint32_t info_ptr; 489 490 /** The number of buffers that were consumed during packet processing by 491 * the driver on this Output queue before the driver attempts to 492 * replenish the descriptor ring with new buffers. 493 */ 494 uint32_t refill_threshold; 495 }; 496 497 /* Structure to define the configuration. */ 498 struct lio_config { 499 uint16_t card_type; 500 const char *card_name; 501 502 /** Input Queue attributes. */ 503 struct lio_iq_config iq; 504 505 /** Output Queue attributes. */ 506 struct lio_oq_config oq; 507 508 int num_nic_ports; 509 510 int num_def_tx_descs; 511 512 /* Num of desc for rx rings */ 513 int num_def_rx_descs; 514 515 int def_rx_buf_size; 516 }; 517 518 /** Status of a RGMII Link on Octeon as seen by core driver. */ 519 union octeon_link_status { 520 uint64_t link_status64; 521 522 struct { 523 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 524 uint64_t duplex : 8; 525 uint64_t mtu : 16; 526 uint64_t speed : 16; 527 uint64_t link_up : 1; 528 uint64_t autoneg : 1; 529 uint64_t if_mode : 5; 530 uint64_t pause : 1; 531 uint64_t flashing : 1; 532 uint64_t reserved : 15; 533 #else 534 uint64_t reserved : 15; 535 uint64_t flashing : 1; 536 uint64_t pause : 1; 537 uint64_t if_mode : 5; 538 uint64_t autoneg : 1; 539 uint64_t link_up : 1; 540 uint64_t speed : 16; 541 uint64_t mtu : 16; 542 uint64_t duplex : 8; 543 #endif 544 } s; 545 }; 546 547 /** The rxpciq info passed to host from the firmware */ 548 union octeon_rxpciq { 549 uint64_t rxpciq64; 550 551 struct { 552 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 553 uint64_t q_no : 8; 554 uint64_t reserved : 56; 555 #else 556 uint64_t reserved : 56; 557 uint64_t q_no : 8; 558 #endif 559 } s; 560 }; 561 562 /** Information for a OCTEON ethernet interface shared between core & host. */ 563 struct octeon_link_info { 564 union octeon_link_status link; 565 uint64_t hw_addr; 566 567 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 568 uint64_t gmxport : 16; 569 uint64_t macaddr_is_admin_assigned : 1; 570 uint64_t vlan_is_admin_assigned : 1; 571 uint64_t rsvd : 30; 572 uint64_t num_txpciq : 8; 573 uint64_t num_rxpciq : 8; 574 #else 575 uint64_t num_rxpciq : 8; 576 uint64_t num_txpciq : 8; 577 uint64_t rsvd : 30; 578 uint64_t vlan_is_admin_assigned : 1; 579 uint64_t macaddr_is_admin_assigned : 1; 580 uint64_t gmxport : 16; 581 #endif 582 583 union octeon_txpciq txpciq[LIO_MAX_IOQS_PER_IF]; 584 union octeon_rxpciq rxpciq[LIO_MAX_IOQS_PER_IF]; 585 }; 586 587 /* ----------------------- THE LIO DEVICE --------------------------- */ 588 /** The lio device. 589 * Each lio device has this structure to represent all its 590 * components. 591 */ 592 struct lio_device { 593 /** PCI device pointer */ 594 struct rte_pci_device *pci_dev; 595 596 /** Octeon Chip type */ 597 uint16_t chip_id; 598 uint16_t pf_num; 599 uint16_t vf_num; 600 601 /** This device's PCIe port used for traffic. */ 602 uint16_t pcie_port; 603 604 /** The state of this device */ 605 rte_atomic64_t status; 606 607 uint8_t intf_open; 608 609 struct octeon_link_info linfo; 610 611 uint8_t *hw_addr; 612 613 struct lio_fn_list fn_list; 614 615 uint32_t num_iqs; 616 617 /** Guards each glist */ 618 rte_spinlock_t *glist_lock; 619 /** Array of gather component linked lists */ 620 struct lio_stailq_head *glist_head; 621 622 /* The pool containing pre allocated buffers used for soft commands */ 623 struct rte_mempool *sc_buf_pool; 624 625 /** The input instruction queues */ 626 struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES]; 627 628 /** The singly-linked tail queues of instruction response */ 629 struct lio_response_list response_list; 630 631 uint32_t num_oqs; 632 633 /** The DROQ output queues */ 634 struct lio_droq *droq[LIO_MAX_POSSIBLE_OUTPUT_QUEUES]; 635 636 struct lio_io_enable io_qmask; 637 638 struct lio_sriov_info sriov_info; 639 640 struct lio_pf_vf_hs_word pfvf_hsword; 641 642 /** Mail Box details of each lio queue. */ 643 struct lio_mbox **mbox; 644 645 char dev_string[LIO_DEVICE_NAME_LEN]; /* Device print string */ 646 647 const struct lio_config *default_config; 648 649 struct rte_eth_dev *eth_dev; 650 651 uint64_t ifflags; 652 uint8_t max_rx_queues; 653 uint8_t max_tx_queues; 654 uint8_t nb_rx_queues; 655 uint8_t nb_tx_queues; 656 uint8_t port_configured; 657 struct lio_rss_ctx rss_state; 658 uint16_t port_id; 659 char firmware_version[LIO_FW_VERSION_LENGTH]; 660 }; 661 #endif /* _LIO_STRUCT_H_ */ 662