1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef _LIO_23XX_REG_H_ 6 #define _LIO_23XX_REG_H_ 7 8 /* ###################### REQUEST QUEUE ######################### */ 9 10 /* 64 registers for Input Queues Start Addr - SLI_PKT(0..63)_INSTR_BADDR */ 11 #define CN23XX_SLI_PKT_INSTR_BADDR_START64 0x10010 12 13 /* 64 registers for Input Doorbell - SLI_PKT(0..63)_INSTR_BAOFF_DBELL */ 14 #define CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START 0x10020 15 16 /* 64 registers for Input Queue size - SLI_PKT(0..63)_INSTR_FIFO_RSIZE */ 17 #define CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START 0x10030 18 19 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE(0..63)_CNTS */ 20 #define CN23XX_SLI_PKT_IN_DONE_CNTS_START64 0x10040 21 22 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & 23 * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. 24 */ 25 #define CN23XX_SLI_PKT_INPUT_CONTROL_START64 0x10000 26 27 /* ------- Request Queue Macros --------- */ 28 29 /* Each Input Queue register is at a 16-byte Offset in BAR0 */ 30 #define CN23XX_IQ_OFFSET 0x20000 31 32 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ 33 (CN23XX_SLI_PKT_INPUT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET)) 34 35 #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \ 36 (CN23XX_SLI_PKT_INSTR_BADDR_START64 + ((iq) * CN23XX_IQ_OFFSET)) 37 38 #define CN23XX_SLI_IQ_SIZE(iq) \ 39 (CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START + ((iq) * CN23XX_IQ_OFFSET)) 40 41 #define CN23XX_SLI_IQ_DOORBELL(iq) \ 42 (CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START + ((iq) * CN23XX_IQ_OFFSET)) 43 44 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ 45 (CN23XX_SLI_PKT_IN_DONE_CNTS_START64 + ((iq) * CN23XX_IQ_OFFSET)) 46 47 /* Number of instructions to be read in one MAC read request. 48 * setting to Max value(4) 49 */ 50 #define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25) 51 #define CN23XX_PKT_INPUT_CTL_IS_64B (1 << 24) 52 #define CN23XX_PKT_INPUT_CTL_RST (1 << 23) 53 #define CN23XX_PKT_INPUT_CTL_QUIET (1 << 28) 54 #define CN23XX_PKT_INPUT_CTL_RING_ENB (1 << 22) 55 #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP (1 << 6) 56 #define CN23XX_PKT_INPUT_CTL_USE_CSR (1 << 4) 57 #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2) 58 59 /* These bits[47:44] select the Physical function number within the MAC */ 60 #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS 45 61 /* These bits[43:32] select the function number within the PF */ 62 #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS 32 63 64 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 65 #define CN23XX_PKT_INPUT_CTL_MASK \ 66 (CN23XX_PKT_INPUT_CTL_RDSIZE | \ 67 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 68 CN23XX_PKT_INPUT_CTL_USE_CSR) 69 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 70 #define CN23XX_PKT_INPUT_CTL_MASK \ 71 (CN23XX_PKT_INPUT_CTL_RDSIZE | \ 72 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 73 CN23XX_PKT_INPUT_CTL_USE_CSR | \ 74 CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP) 75 #endif 76 77 /* ############################ OUTPUT QUEUE ######################### */ 78 79 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ 80 #define CN23XX_SLI_PKT_OUTPUT_CONTROL_START 0x10050 81 82 /* 64 registers for Output queue buffer and info size 83 * SLI_PKT(0..63)_OUT_SIZE 84 */ 85 #define CN23XX_SLI_PKT_OUT_SIZE 0x10060 86 87 /* 64 registers for Output Queue Start Addr - SLI_PKT(0..63)_SLIST_BADDR */ 88 #define CN23XX_SLI_SLIST_BADDR_START64 0x10070 89 90 /* 64 registers for Output Queue Packet Credits 91 * SLI_PKT(0..63)_SLIST_BAOFF_DBELL 92 */ 93 #define CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START 0x10080 94 95 /* 64 registers for Output Queue size - SLI_PKT(0..63)_SLIST_FIFO_RSIZE */ 96 #define CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START 0x10090 97 98 /* 64 registers for Output Queue Packet Count - SLI_PKT(0..63)_CNTS */ 99 #define CN23XX_SLI_PKT_CNTS_START 0x100B0 100 101 /* Each Output Queue register is at a 16-byte Offset in BAR0 */ 102 #define CN23XX_OQ_OFFSET 0x20000 103 104 /* ------- Output Queue Macros --------- */ 105 106 #define CN23XX_SLI_OQ_PKT_CONTROL(oq) \ 107 (CN23XX_SLI_PKT_OUTPUT_CONTROL_START + ((oq) * CN23XX_OQ_OFFSET)) 108 109 #define CN23XX_SLI_OQ_BASE_ADDR64(oq) \ 110 (CN23XX_SLI_SLIST_BADDR_START64 + ((oq) * CN23XX_OQ_OFFSET)) 111 112 #define CN23XX_SLI_OQ_SIZE(oq) \ 113 (CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START + ((oq) * CN23XX_OQ_OFFSET)) 114 115 #define CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) \ 116 (CN23XX_SLI_PKT_OUT_SIZE + ((oq) * CN23XX_OQ_OFFSET)) 117 118 #define CN23XX_SLI_OQ_PKTS_SENT(oq) \ 119 (CN23XX_SLI_PKT_CNTS_START + ((oq) * CN23XX_OQ_OFFSET)) 120 121 #define CN23XX_SLI_OQ_PKTS_CREDIT(oq) \ 122 (CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START + ((oq) * CN23XX_OQ_OFFSET)) 123 124 /* ------------------ Masks ---------------- */ 125 #define CN23XX_PKT_OUTPUT_CTL_IPTR (1 << 11) 126 #define CN23XX_PKT_OUTPUT_CTL_ES (1 << 9) 127 #define CN23XX_PKT_OUTPUT_CTL_NSR (1 << 8) 128 #define CN23XX_PKT_OUTPUT_CTL_ROR (1 << 7) 129 #define CN23XX_PKT_OUTPUT_CTL_DPTR (1 << 6) 130 #define CN23XX_PKT_OUTPUT_CTL_BMODE (1 << 5) 131 #define CN23XX_PKT_OUTPUT_CTL_ES_P (1 << 3) 132 #define CN23XX_PKT_OUTPUT_CTL_NSR_P (1 << 2) 133 #define CN23XX_PKT_OUTPUT_CTL_ROR_P (1 << 1) 134 #define CN23XX_PKT_OUTPUT_CTL_RING_ENB (1 << 0) 135 136 /* Rings per Virtual Function [RO] */ 137 #define CN23XX_PKT_INPUT_CTL_RPVF_MASK 0x3F 138 #define CN23XX_PKT_INPUT_CTL_RPVF_POS 48 139 140 /* These bits[47:44][RO] give the Physical function 141 * number info within the MAC 142 */ 143 #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK 0x7 144 145 /* These bits[43:32][RO] give the virtual function 146 * number info within the PF 147 */ 148 #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK 0x1FFF 149 150 /* ######################### Mailbox Reg Macros ######################## */ 151 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200 152 #define CN23XX_VF_SLI_PKT_MBOX_INT_START 0x10210 153 154 #define CN23XX_SLI_MBOX_OFFSET 0x20000 155 #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8 156 157 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \ 158 (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \ 159 ((q) * CN23XX_SLI_MBOX_OFFSET + \ 160 (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET)) 161 162 #define CN23XX_VF_SLI_PKT_MBOX_INT(q) \ 163 (CN23XX_VF_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET)) 164 165 #endif /* _LIO_23XX_REG_H_ */ 166