1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015 Intel Corporation
3 */
4 #ifndef _IXGBE_REGS_H_
5 #define _IXGBE_REGS_H_
6
7 #include "ixgbe_ethdev.h"
8
9 struct ixgbe_hw;
10 struct reg_info {
11 uint32_t base_addr;
12 uint32_t count;
13 uint32_t stride;
14 const char *name;
15 };
16
17 static const struct reg_info ixgbe_regs_general[] = {
18 {IXGBE_CTRL, 1, 1, "IXGBE_CTRL"},
19 {IXGBE_STATUS, 1, 1, "IXGBE_STATUS"},
20 {IXGBE_CTRL_EXT, 1, 1, "IXGBE_CTRL_EXT"},
21 {IXGBE_ESDP, 1, 1, "IXGBE_ESDP"},
22 {IXGBE_EODSDP, 1, 1, "IXGBE_EODSDP"},
23 {IXGBE_LEDCTL, 1, 1, "IXGBE_LEDCTL"},
24 {IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"},
25 {IXGBE_TCPTIMER, 1, 1, "IXGBE_TCPTIMER"},
26 {0, 0, 0, ""}
27 };
28
29 static const struct reg_info ixgbevf_regs_general[] = {
30 {IXGBE_VFCTRL, 1, 1, "IXGBE_VFCTRL"},
31 {IXGBE_VFSTATUS, 1, 1, "IXGBE_VFSTATUS"},
32 {IXGBE_VFLINKS, 1, 1, "IXGBE_VFLINKS"},
33 {IXGBE_VFFRTIMER, 1, 1, "IXGBE_VFFRTIMER"},
34 {IXGBE_VFMAILBOX, 1, 1, "IXGBE_VFMAILBOX"},
35 {IXGBE_VFMBMEM, 16, 4, "IXGBE_VFMBMEM"},
36 {IXGBE_VFRXMEMWRAP, 1, 1, "IXGBE_VFRXMEMWRAP"},
37 {0, 0, 0, ""}
38 };
39
40 static const struct reg_info ixgbe_regs_nvm[] = {
41 {IXGBE_EEC, 1, 1, "IXGBE_EEC"},
42 {IXGBE_EERD, 1, 1, "IXGBE_EERD"},
43 {IXGBE_FLA, 1, 1, "IXGBE_FLA"},
44 {IXGBE_EEMNGCTL, 1, 1, "IXGBE_EEMNGCTL"},
45 {IXGBE_EEMNGDATA, 1, 1, "IXGBE_EEMNGDATA"},
46 {IXGBE_FLMNGCTL, 1, 1, "IXGBE_FLMNGCTL"},
47 {IXGBE_FLMNGDATA, 1, 1, "IXGBE_FLMNGDATA"},
48 {IXGBE_FLMNGCNT, 1, 1, "IXGBE_FLMNGCNT"},
49 {IXGBE_FLOP, 1, 1, "IXGBE_FLOP"},
50 {IXGBE_GRC, 1, 1, "IXGBE_GRC"},
51 {0, 0, 0, ""}
52 };
53
54 static const struct reg_info ixgbe_regs_interrupt[] = {
55 {IXGBE_EICS, 1, 1, "IXGBE_EICS"},
56 {IXGBE_EIMS, 1, 1, "IXGBE_EIMS"},
57 {IXGBE_EIMC, 1, 1, "IXGBE_EIMC"},
58 {IXGBE_EIAC, 1, 1, "IXGBE_EIAC"},
59 {IXGBE_EIAM, 1, 1, "IXGBE_EIAM"},
60 {IXGBE_EITR(0), 24, 4, "IXGBE_EITR"},
61 {IXGBE_IVAR(0), 24, 4, "IXGBE_IVAR"},
62 {IXGBE_MSIXT, 1, 1, "IXGBE_MSIXT"},
63 {IXGBE_MSIXPBA, 1, 1, "IXGBE_MSIXPBA"},
64 {IXGBE_PBACL(0), 1, 4, "IXGBE_PBACL"},
65 {IXGBE_GPIE, 1, 1, ""},
66 {0, 0, 0, ""}
67 };
68
69 static const struct reg_info ixgbevf_regs_interrupt[] = {
70 {IXGBE_VTEICR, 1, 1, "IXGBE_VTEICR"},
71 {IXGBE_VTEICS, 1, 1, "IXGBE_VTEICS"},
72 {IXGBE_VTEIMS, 1, 1, "IXGBE_VTEIMS"},
73 {IXGBE_VTEIMC, 1, 1, "IXGBE_VTEIMC"},
74 {IXGBE_VTEIAM, 1, 1, "IXGBE_VTEIAM"},
75 {IXGBE_VTEITR(0), 2, 4, "IXGBE_VTEITR"},
76 {IXGBE_VTIVAR(0), 4, 4, "IXGBE_VTIVAR"},
77 {IXGBE_VTIVAR_MISC, 1, 1, "IXGBE_VTIVAR_MISC"},
78 {IXGBE_VTRSCINT(0), 2, 4, "IXGBE_VTRSCINT"},
79 {0, 0, 0, ""}
80 };
81
82 static const struct reg_info ixgbe_regs_fctl_mac_82598EB[] = {
83 {IXGBE_PFCTOP, 1, 1, ""},
84 {IXGBE_FCTTV(0), 4, 4, ""},
85 {IXGBE_FCRTV, 1, 1, ""},
86 {IXGBE_TFCS, 1, 1, ""},
87 {IXGBE_FCRTL(0), 8, 8, "IXGBE_FCRTL"},
88 {IXGBE_FCRTH(0), 8, 8, "IXGBE_FCRTH"},
89 {0, 0, 0, ""}
90 };
91
92 static const struct reg_info ixgbe_regs_fctl_others[] = {
93 {IXGBE_PFCTOP, 1, 1, ""},
94 {IXGBE_FCTTV(0), 4, 4, ""},
95 {IXGBE_FCRTV, 1, 1, ""},
96 {IXGBE_TFCS, 1, 1, ""},
97 {IXGBE_FCRTL_82599(0), 8, 4, "IXGBE_FCRTL"},
98 {IXGBE_FCRTH_82599(0), 8, 4, "IXGBE_FCRTH"},
99 {0, 0, 0, ""}
100 };
101
102 static const struct reg_info ixgbe_regs_rxdma[] = {
103 {IXGBE_RDBAL(0), 64, 0x40, "IXGBE_RDBAL"},
104 {IXGBE_RDBAH(0), 64, 0x40, "IXGBE_RDBAH"},
105 {IXGBE_RDLEN(0), 64, 0x40, "IXGBE_RDLEN"},
106 {IXGBE_RDH(0), 64, 0x40, "IXGBE_RDH"},
107 {IXGBE_RDT(0), 64, 0x40, "IXGBE_RDT"},
108 {IXGBE_RXDCTL(0), 64, 0x40, "IXGBE_RXDCTL"},
109 {IXGBE_SRRCTL(0), 16, 0x4, "IXGBE_SRRCTL"},
110 {IXGBE_DCA_RXCTRL(0), 16, 4, "IXGBE_DCA_RXCTRL"},
111 {IXGBE_RDRXCTL, 1, 1, "IXGBE_RDRXCTL"},
112 {IXGBE_RXPBSIZE(0), 8, 4, "IXGBE_RXPBSIZE"},
113 {IXGBE_RXCTRL, 1, 1, "IXGBE_RXCTRL"},
114 {IXGBE_DROPEN, 1, 1, "IXGBE_DROPEN"},
115 {0, 0, 0, ""}
116 };
117
118 static const struct reg_info ixgbevf_regs_rxdma[] = {
119 {IXGBE_VFRDBAL(0), 8, 0x40, "IXGBE_VFRDBAL"},
120 {IXGBE_VFRDBAH(0), 8, 0x40, "IXGBE_VFRDBAH"},
121 {IXGBE_VFRDLEN(0), 8, 0x40, "IXGBE_VFRDLEN"},
122 {IXGBE_VFRDH(0), 8, 0x40, "IXGBE_VFRDH"},
123 {IXGBE_VFRDT(0), 8, 0x40, "IXGBE_VFRDT"},
124 {IXGBE_VFRXDCTL(0), 8, 0x40, "IXGBE_VFRXDCTL"},
125 {IXGBE_VFSRRCTL(0), 8, 0x40, "IXGBE_VFSRRCTL"},
126 {IXGBE_VFPSRTYPE, 1, 1, "IXGBE_VFPSRTYPE"},
127 {IXGBE_VFRSCCTL(0), 8, 0x40, "IXGBE_VFRSCCTL"},
128 {IXGBE_VFDCA_RXCTRL(0), 8, 0x40, "IXGBE_VFDCA_RXCTRL"},
129 {IXGBE_VFDCA_TXCTRL(0), 8, 0x40, "IXGBE_VFDCA_TXCTRL"},
130 {0, 0, 0, ""}
131 };
132
133 static const struct reg_info ixgbe_regs_rx[] = {
134 {IXGBE_RXCSUM, 1, 1, "IXGBE_RXCSUM"},
135 {IXGBE_RFCTL, 1, 1, "IXGBE_RFCTL"},
136 {IXGBE_RAL(0), 16, 8, "IXGBE_RAL"},
137 {IXGBE_RAH(0), 16, 8, "IXGBE_RAH"},
138 {IXGBE_PSRTYPE(0), 1, 4, "IXGBE_PSRTYPE"},
139 {IXGBE_FCTRL, 1, 1, "IXGBE_FCTRL"},
140 {IXGBE_VLNCTRL, 1, 1, "IXGBE_VLNCTRL"},
141 {IXGBE_MCSTCTRL, 1, 1, "IXGBE_MCSTCTRL"},
142 {IXGBE_MRQC, 1, 1, "IXGBE_MRQC"},
143 {IXGBE_VMD_CTL, 1, 1, "IXGBE_VMD_CTL"},
144 {IXGBE_IMIR(0), 8, 4, "IXGBE_IMIR"},
145 {IXGBE_IMIREXT(0), 8, 4, "IXGBE_IMIREXT"},
146 {IXGBE_IMIRVP, 1, 1, "IXGBE_IMIRVP"},
147 {0, 0, 0, ""}
148 };
149
150 static struct reg_info ixgbe_regs_tx[] = {
151 {IXGBE_TDBAL(0), 32, 0x40, "IXGBE_TDBAL"},
152 {IXGBE_TDBAH(0), 32, 0x40, "IXGBE_TDBAH"},
153 {IXGBE_TDLEN(0), 32, 0x40, "IXGBE_TDLEN"},
154 {IXGBE_TDH(0), 32, 0x40, "IXGBE_TDH"},
155 {IXGBE_TDT(0), 32, 0x40, "IXGBE_TDT"},
156 {IXGBE_TXDCTL(0), 32, 0x40, "IXGBE_TXDCTL"},
157 {IXGBE_TDWBAL(0), 32, 0x40, "IXGBE_TDWBAL"},
158 {IXGBE_TDWBAH(0), 32, 0x40, "IXGBE_TDWBAH"},
159 {IXGBE_DTXCTL, 1, 1, "IXGBE_DTXCTL"},
160 {IXGBE_DCA_TXCTRL(0), 16, 4, "IXGBE_DCA_TXCTRL"},
161 {IXGBE_TXPBSIZE(0), 8, 4, "IXGBE_TXPBSIZE"},
162 {IXGBE_MNGTXMAP, 1, 1, "IXGBE_MNGTXMAP"},
163 {0, 0, 0, ""}
164 };
165
166 static const struct reg_info ixgbevf_regs_tx[] = {
167 {IXGBE_VFTDBAL(0), 4, 0x40, "IXGBE_VFTDBAL"},
168 {IXGBE_VFTDBAH(0), 4, 0x40, "IXGBE_VFTDBAH"},
169 {IXGBE_VFTDLEN(0), 4, 0x40, "IXGBE_VFTDLEN"},
170 {IXGBE_VFTDH(0), 4, 0x40, "IXGBE_VFTDH"},
171 {IXGBE_VFTDT(0), 4, 0x40, "IXGBE_VFTDT"},
172 {IXGBE_VFTXDCTL(0), 4, 0x40, "IXGBE_VFTXDCTL"},
173 {IXGBE_VFTDWBAL(0), 4, 0x40, "IXGBE_VFTDWBAL"},
174 {IXGBE_VFTDWBAH(0), 4, 0x40, "IXGBE_VFTDWBAH"},
175 {0, 0, 0, ""}
176 };
177
178 static const struct reg_info ixgbe_regs_wakeup[] = {
179 {IXGBE_WUC, 1, 1, "IXGBE_WUC"},
180 {IXGBE_WUFC, 1, 1, "IXGBE_WUFC"},
181 {IXGBE_WUS, 1, 1, "IXGBE_WUS"},
182 {IXGBE_IPAV, 1, 1, "IXGBE_IPAV"},
183 {IXGBE_IP4AT, 1, 1, "IXGBE_IP4AT"},
184 {IXGBE_IP6AT, 1, 1, "IXGBE_IP6AT"},
185 {IXGBE_WUPL, 1, 1, "IXGBE_WUPL"},
186 {IXGBE_WUPM, 1, 1, "IXGBE_WUPM"},
187 {IXGBE_FHFT(0), 1, 1, "IXGBE_FHFT"},
188 {0, 0, 0, ""}
189 };
190
191 static const struct reg_info ixgbe_regs_dcb[] = {
192 {IXGBE_RMCS, 1, 1, "IXGBE_RMCS"},
193 {IXGBE_DPMCS, 1, 1, "IXGBE_DPMCS"},
194 {IXGBE_PDPMCS, 1, 1, "IXGBE_PDPMCS"},
195 {IXGBE_RUPPBMR, 1, 1, "IXGBE_RUPPBMR"},
196 {IXGBE_RT2CR(0), 8, 4, "IXGBE_RT2CR"},
197 {IXGBE_RT2SR(0), 8, 4, "IXGBE_RT2SR"},
198 {IXGBE_TDTQ2TCCR(0), 8, 0x40, "IXGBE_TDTQ2TCCR"},
199 {IXGBE_TDTQ2TCSR(0), 8, 0x40, "IXGBE_TDTQ2TCSR"},
200 {IXGBE_TDPT2TCCR(0), 8, 4, "IXGBE_TDPT2TCCR"},
201 {IXGBE_TDPT2TCSR(0), 8, 4, "IXGBE_TDPT2TCSR"},
202 {0, 0, 0, ""}
203 };
204
205 static const struct reg_info ixgbe_regs_mac[] = {
206 {IXGBE_PCS1GCFIG, 1, 1, "IXGBE_PCS1GCFIG"},
207 {IXGBE_PCS1GLCTL, 1, 1, "IXGBE_PCS1GLCTL"},
208 {IXGBE_PCS1GLSTA, 1, 1, "IXGBE_PCS1GLSTA"},
209 {IXGBE_PCS1GDBG0, 1, 1, "IXGBE_PCS1GDBG0"},
210 {IXGBE_PCS1GDBG1, 1, 1, "IXGBE_PCS1GDBG1"},
211 {IXGBE_PCS1GANA, 1, 1, "IXGBE_PCS1GANA"},
212 {IXGBE_PCS1GANLP, 1, 1, "IXGBE_PCS1GANLP"},
213 {IXGBE_PCS1GANNP, 1, 1, "IXGBE_PCS1GANNP"},
214 {IXGBE_PCS1GANLPNP, 1, 1, "IXGBE_PCS1GANLPNP"},
215 {IXGBE_HLREG0, 1, 1, "IXGBE_HLREG0"},
216 {IXGBE_HLREG1, 1, 1, "IXGBE_HLREG1"},
217 {IXGBE_PAP, 1, 1, "IXGBE_PAP"},
218 {IXGBE_MACA, 1, 1, "IXGBE_MACA"},
219 {IXGBE_APAE, 1, 1, "IXGBE_APAE"},
220 {IXGBE_ARD, 1, 1, "IXGBE_ARD"},
221 {IXGBE_AIS, 1, 1, "IXGBE_AIS"},
222 {IXGBE_MSCA, 1, 1, "IXGBE_MSCA"},
223 {IXGBE_MSRWD, 1, 1, "IXGBE_MSRWD"},
224 {IXGBE_MLADD, 1, 1, "IXGBE_MLADD"},
225 {IXGBE_MHADD, 1, 1, "IXGBE_MHADD"},
226 {IXGBE_TREG, 1, 1, "IXGBE_TREG"},
227 {IXGBE_PCSS1, 1, 1, "IXGBE_PCSS1"},
228 {IXGBE_PCSS2, 1, 1, "IXGBE_PCSS2"},
229 {IXGBE_XPCSS, 1, 1, "IXGBE_XPCSS"},
230 {IXGBE_SERDESC, 1, 1, "IXGBE_SERDESC"},
231 {IXGBE_MACS, 1, 1, "IXGBE_MACS"},
232 {IXGBE_AUTOC, 1, 1, "IXGBE_AUTOC"},
233 {IXGBE_LINKS, 1, 1, "IXGBE_LINKS"},
234 {IXGBE_AUTOC2, 1, 1, "IXGBE_AUTOC2"},
235 {IXGBE_AUTOC3, 1, 1, "IXGBE_AUTOC3"},
236 {IXGBE_ANLP1, 1, 1, "IXGBE_ANLP1"},
237 {IXGBE_ANLP2, 1, 1, "IXGBE_ANLP2"},
238 {IXGBE_ATLASCTL, 1, 1, "IXGBE_ATLASCTL"},
239 {0, 0, 0, ""}
240 };
241
242 static const struct reg_info ixgbe_regs_diagnostic[] = {
243 {IXGBE_RDSTATCTL, 1, 1, "IXGBE_RDSTATCTL"},
244 {IXGBE_RDSTAT(0), 8, 4, "IXGBE_RDSTAT"},
245 {IXGBE_RDHMPN, 1, 1, "IXGBE_RDHMPN"},
246 {IXGBE_RIC_DW(0), 4, 4, "IXGBE_RIC_DW"},
247 {IXGBE_RDPROBE, 1, 1, "IXGBE_RDPROBE"},
248 {IXGBE_TDHMPN, 1, 1, "IXGBE_TDHMPN"},
249 {IXGBE_TIC_DW(0), 4, 4, "IXGBE_TIC_DW"},
250 {IXGBE_TDPROBE, 1, 1, "IXGBE_TDPROBE"},
251 {IXGBE_TXBUFCTRL, 1, 1, "IXGBE_TXBUFCTRL"},
252 {IXGBE_TXBUFDATA0, 1, 1, "IXGBE_TXBUFDATA0"},
253 {IXGBE_TXBUFDATA1, 1, 1, "IXGBE_TXBUFDATA1"},
254 {IXGBE_TXBUFDATA2, 1, 1, "IXGBE_TXBUFDATA2"},
255 {IXGBE_TXBUFDATA3, 1, 1, "IXGBE_TXBUFDATA3"},
256 {IXGBE_RXBUFCTRL, 1, 1, "IXGBE_RXBUFCTRL"},
257 {IXGBE_RXBUFDATA0, 1, 1, "IXGBE_RXBUFDATA0"},
258 {IXGBE_RXBUFDATA1, 1, 1, "IXGBE_RXBUFDATA1"},
259 {IXGBE_RXBUFDATA2, 1, 1, "IXGBE_RXBUFDATA2"},
260 {IXGBE_RXBUFDATA3, 1, 1, "IXGBE_RXBUFDATA3"},
261 {IXGBE_PCIE_DIAG(0), 8, 4, ""},
262 {IXGBE_RFVAL, 1, 1, "IXGBE_RFVAL"},
263 {IXGBE_MDFTC1, 1, 1, "IXGBE_MDFTC1"},
264 {IXGBE_MDFTC2, 1, 1, "IXGBE_MDFTC2"},
265 {IXGBE_MDFTFIFO1, 1, 1, "IXGBE_MDFTFIFO1"},
266 {IXGBE_MDFTFIFO2, 1, 1, "IXGBE_MDFTFIFO2"},
267 {IXGBE_MDFTS, 1, 1, "IXGBE_MDFTS"},
268 {IXGBE_PCIEECCCTL, 1, 1, "IXGBE_PCIEECCCTL"},
269 {IXGBE_PBTXECC, 1, 1, "IXGBE_PBTXECC"},
270 {IXGBE_PBRXECC, 1, 1, "IXGBE_PBRXECC"},
271 {IXGBE_MFLCN, 1, 1, "IXGBE_MFLCN"},
272 {0, 0, 0, ""},
273 };
274
275 /* PF registers */
276 static const struct reg_info *ixgbe_regs_others[] = {
277 ixgbe_regs_general,
278 ixgbe_regs_nvm, ixgbe_regs_interrupt,
279 ixgbe_regs_fctl_others,
280 ixgbe_regs_rxdma,
281 ixgbe_regs_rx,
282 ixgbe_regs_tx,
283 ixgbe_regs_wakeup,
284 ixgbe_regs_dcb,
285 ixgbe_regs_mac,
286 ixgbe_regs_diagnostic,
287 NULL};
288
289 static const struct reg_info *ixgbe_regs_mac_82598EB[] = {
290 ixgbe_regs_general,
291 ixgbe_regs_nvm,
292 ixgbe_regs_interrupt,
293 ixgbe_regs_fctl_mac_82598EB,
294 ixgbe_regs_rxdma,
295 ixgbe_regs_rx,
296 ixgbe_regs_tx,
297 ixgbe_regs_wakeup,
298 ixgbe_regs_dcb,
299 ixgbe_regs_mac,
300 ixgbe_regs_diagnostic,
301 NULL};
302
303 /* VF registers */
304 static const struct reg_info *ixgbevf_regs[] = {
305 ixgbevf_regs_general,
306 ixgbevf_regs_interrupt,
307 ixgbevf_regs_rxdma,
308 ixgbevf_regs_tx,
309 NULL};
310
311 static inline int
ixgbe_read_regs(struct ixgbe_hw * hw,const struct reg_info * reg,uint32_t * reg_buf)312 ixgbe_read_regs(struct ixgbe_hw *hw, const struct reg_info *reg,
313 uint32_t *reg_buf)
314 {
315 unsigned int i;
316
317 for (i = 0; i < reg->count; i++)
318 reg_buf[i] = IXGBE_READ_REG(hw,
319 reg->base_addr + i * reg->stride);
320 return reg->count;
321 };
322
323 static inline int
ixgbe_regs_group_count(const struct reg_info * regs)324 ixgbe_regs_group_count(const struct reg_info *regs)
325 {
326 int count = 0;
327 int i = 0;
328
329 while (regs[i].count)
330 count += regs[i++].count;
331 return count;
332 };
333
334 static inline int
ixgbe_read_regs_group(struct rte_eth_dev * dev,uint32_t * reg_buf,const struct reg_info * regs)335 ixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,
336 const struct reg_info *regs)
337 {
338 int count = 0;
339 int i = 0;
340 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
341
342 while (regs[i].count)
343 count += ixgbe_read_regs(hw, ®s[i++], ®_buf[count]);
344 return count;
345 };
346
347 #endif /* _IXGBE_REGS_H_ */
348