1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2018 Intel Corporation 3 */ 4 5 #ifndef _IFPGA_RAWDEV_API_H_ 6 #define _IFPGA_RAWDEV_API_H_ 7 8 #include <rte_ether.h> 9 10 enum ifpga_rawdev_retimer_media_type { 11 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_UNKNOWN = 0, 12 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_LR4, 13 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_SR4, 14 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_CR4, 15 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_LR4, 16 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_400GBASE_SR4, 17 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_CR4, 18 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_SR, 19 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_CR, 20 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_LR, 21 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_SR, 22 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_DAC, 23 IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_DEFAULT 24 }; 25 26 enum ifpga_rawdev_retimer_mac_type { 27 IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN = 0, 28 IFPGA_RAWDEV_RETIMER_MAC_TYPE_100GE_CAUI, 29 IFPGA_RAWDEVG_RETIMER_MAC_TYPE_40GE_XLAUI, 30 IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI, 31 IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI, 32 IFPGA_RAWDEV_RETIMER_MAC_TYPE_DEFAULT 33 }; 34 35 #define IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT 0x0 36 #define IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT 0x1 37 #define IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT 0x2 38 39 enum ifpga_rawdev_link_speed { 40 IFPGA_RAWDEV_LINK_SPEED_UNKNOWN = 0, 41 IFPGA_RAWDEV_LINK_SPEED_10GB = 42 (1 << IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT), 43 IFPGA_RAWDEV_LINK_SPEED_40GB = 44 (1 << IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT), 45 IFPGA_RAWDEV_LINK_SPEED_25GB = 46 (1 << IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT), 47 }; 48 49 struct ifpga_rawdevg_retimer_info { 50 int retimer_num; 51 int port_num; 52 enum ifpga_rawdev_retimer_media_type media_type; 53 enum ifpga_rawdev_retimer_mac_type mac_type; 54 }; 55 56 struct ifpga_rawdevg_link_info { 57 int port; 58 int link_up; 59 enum ifpga_rawdev_link_speed link_speed; 60 }; 61 62 struct ipn3ke_pub_func { 63 struct ifpga_rawdev *(*get_ifpga_rawdev)(const struct rte_rawdev *rdv); 64 int (*set_i40e_sw_dev)(uint16_t port_id, struct rte_eth_dev *sw_dev); 65 }; 66 67 /** 68 * @internal 69 * The publid functions of bridge PAC N3000 FPGA and I40e. 70 */ 71 extern struct ipn3ke_pub_func ipn3ke_bridge_func; 72 73 74 #endif /* _IFPGA_RAWDEV_H_ */ 75