1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_BASE_H_ 6 #define _IGC_BASE_H_ 7 8 /* forward declaration */ 9 s32 igc_init_hw_base(struct igc_hw *hw); 10 void igc_power_down_phy_copper_base(struct igc_hw *hw); 11 void igc_rx_fifo_flush_base(struct igc_hw *hw); 12 s32 igc_acquire_phy_base(struct igc_hw *hw); 13 void igc_release_phy_base(struct igc_hw *hw); 14 15 /* Transmit Descriptor - Advanced */ 16 union igc_adv_tx_desc { 17 struct { 18 __le64 buffer_addr; /* Address of descriptor's data buf */ 19 __le32 cmd_type_len; 20 __le32 olinfo_status; 21 } read; 22 struct { 23 __le64 rsvd; /* Reserved */ 24 __le32 nxtseq_seed; 25 __le32 status; 26 } wb; 27 }; 28 29 /* Context descriptors */ 30 struct igc_adv_tx_context_desc { 31 __le32 vlan_macip_lens; 32 union { 33 __le32 launch_time; 34 __le32 seqnum_seed; 35 } u; 36 __le32 type_tucmd_mlhl; 37 __le32 mss_l4len_idx; 38 }; 39 40 /* Adv Transmit Descriptor Config Masks */ 41 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 42 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 43 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 44 #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 45 #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 46 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 47 #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 48 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 49 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 50 #define IGC_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 51 #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 52 #define IGC_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 53 #define IGC_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 54 #define IGC_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 55 #define IGC_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 56 #define IGC_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 57 /* 1st & Last TSO-full iSCSI PDU*/ 58 #define IGC_ADVTXD_POPTS_ISCO_FULL 0x00001800 59 #define IGC_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 60 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 61 62 /* Advanced Transmit Context Descriptor Config */ 63 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 64 #define IGC_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 65 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 66 #define IGC_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 67 #define IGC_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 68 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 69 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 70 #define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 71 /* IPSec Encrypt Enable for ESP */ 72 #define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 73 /* Req requires Markers and CRC */ 74 #define IGC_ADVTXD_TUCMD_MKRREQ 0x00002000 75 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 76 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 77 /* Adv ctxt IPSec SA IDX mask */ 78 #define IGC_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 79 /* Adv ctxt IPSec ESP len mask */ 80 #define IGC_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 81 82 #define IGC_RAR_ENTRIES_BASE 16 83 84 /* Receive Descriptor - Advanced */ 85 union igc_adv_rx_desc { 86 struct { 87 __le64 pkt_addr; /* Packet buffer address */ 88 __le64 hdr_addr; /* Header buffer address */ 89 } read; 90 struct { 91 struct { 92 union { 93 __le32 data; 94 struct { 95 __le16 pkt_info; /*RSS type, Pkt type*/ 96 /* Split Header, header buffer len */ 97 __le16 hdr_info; 98 } hs_rss; 99 } lo_dword; 100 union { 101 __le32 rss; /* RSS Hash */ 102 struct { 103 __le16 ip_id; /* IP id */ 104 __le16 csum; /* Packet Checksum */ 105 } csum_ip; 106 } hi_dword; 107 } lower; 108 struct { 109 __le32 status_error; /* ext status/error */ 110 __le16 length; /* Packet length */ 111 __le16 vlan; /* VLAN tag */ 112 } upper; 113 } wb; /* writeback */ 114 }; 115 116 /* Additional Transmit Descriptor Control definitions */ 117 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 118 119 /* Additional Receive Descriptor Control definitions */ 120 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 121 122 /* SRRCTL bit definitions */ 123 #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 124 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 125 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 126 127 #endif /* _IGC_BASE_H_ */ 128