1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015 Intel Corporation
3 */
4 #ifndef _IGB_REGS_H_
5 #define _IGB_REGS_H_
6
7 #include "e1000_ethdev.h"
8
9 struct reg_info {
10 uint32_t base_addr;
11 uint32_t count;
12 uint32_t stride;
13 const char *name;
14 };
15
16 static const struct reg_info igb_regs_general[] = {
17 {E1000_CTRL, 1, 1, "E1000_CTRL"},
18 {E1000_STATUS, 1, 1, "E1000_STATUS"},
19 {E1000_CTRL_EXT, 1, 1, "E1000_CTRL_EXT"},
20 {E1000_MDIC, 1, 1, "E1000_MDIC"},
21 {E1000_SCTL, 1, 1, "E1000_SCTL"},
22 {E1000_CONNSW, 1, 1, "E1000_CONNSW"},
23 {E1000_VET, 1, 1, "E1000_VET"},
24 {E1000_LEDCTL, 1, 1, "E1000_LEDCTL"},
25 {E1000_PBA, 1, 1, "E1000_PBA"},
26 {E1000_PBS, 1, 1, "E1000_PBS"},
27 {E1000_FRTIMER, 1, 1, "E1000_FRTIMER"},
28 {E1000_TCPTIMER, 1, 1, "E1000_TCPTIMER"},
29 {0, 0, 0, ""}
30 };
31
32 static const struct reg_info igb_regs_nvm[] = {
33 {E1000_EECD, 1, 1, "E1000_EECD"},
34 {0, 0, 0, ""}
35 };
36
37 static const struct reg_info igb_regs_interrupt[] = {
38 {E1000_EICS, 1, 1, "E1000_EICS"},
39 {E1000_EIMS, 1, 1, "E1000_EIMS"},
40 {E1000_EIMC, 1, 1, "E1000_EIMC"},
41 {E1000_EIAC, 1, 1, "E1000_EIAC"},
42 {E1000_EIAM, 1, 1, "E1000_EIAM"},
43 {E1000_ICS, 1, 1, "E1000_ICS"},
44 {E1000_IMS, 1, 1, "E1000_IMS"},
45 {E1000_IMC, 1, 1, "E1000_IMC"},
46 {E1000_IAC, 1, 1, "E1000_IAC"},
47 {E1000_IAM, 1, 1, "E1000_IAM"},
48 {E1000_IMIRVP, 1, 1, "E1000_IMIRVP"},
49 {E1000_EITR(0), 10, 4, "E1000_EITR"},
50 {E1000_IMIR(0), 8, 4, "E1000_IMIR"},
51 {E1000_IMIREXT(0), 8, 4, "E1000_IMIREXT"},
52 {0, 0, 0, ""}
53 };
54
55 static const struct reg_info igb_regs_fctl[] = {
56 {E1000_FCAL, 1, 1, "E1000_FCAL"},
57 {E1000_FCAH, 1, 1, "E1000_FCAH"},
58 {E1000_FCTTV, 1, 1, "E1000_FCTTV"},
59 {E1000_FCRTL, 1, 1, "E1000_FCRTL"},
60 {E1000_FCRTH, 1, 1, "E1000_FCRTH"},
61 {E1000_FCRTV, 1, 1, "E1000_FCRTV"},
62 {0, 0, 0, ""}
63 };
64
65 static const struct reg_info igb_regs_rxdma[] = {
66 {E1000_RDBAL(0), 4, 0x100, "E1000_RDBAL"},
67 {E1000_RDBAH(0), 4, 0x100, "E1000_RDBAH"},
68 {E1000_RDLEN(0), 4, 0x100, "E1000_RDLEN"},
69 {E1000_RDH(0), 4, 0x100, "E1000_RDH"},
70 {E1000_RDT(0), 4, 0x100, "E1000_RDT"},
71 {E1000_RXCTL(0), 4, 0x100, "E1000_RXCTL"},
72 {E1000_SRRCTL(0), 4, 0x100, "E1000_SRRCTL"},
73 {E1000_DCA_RXCTRL(0), 4, 0x100, "E1000_DCA_RXCTRL"},
74 {0, 0, 0, ""}
75 };
76
77 static const struct reg_info igb_regs_rx[] = {
78 {E1000_RCTL, 1, 1, "E1000_RCTL"},
79 {E1000_RXCSUM, 1, 1, "E1000_RXCSUM"},
80 {E1000_RLPML, 1, 1, "E1000_RLPML"},
81 {E1000_RFCTL, 1, 1, "E1000_RFCTL"},
82 {E1000_MRQC, 1, 1, "E1000_MRQC"},
83 {E1000_VT_CTL, 1, 1, "E1000_VT_CTL"},
84 {E1000_RAL(0), 16, 8, "E1000_RAL"},
85 {E1000_RAH(0), 16, 8, "E1000_RAH"},
86 {0, 0, 0, ""}
87 };
88
89 static const struct reg_info igb_regs_tx[] = {
90 {E1000_TCTL, 1, 1, "E1000_TCTL"},
91 {E1000_TCTL_EXT, 1, 1, "E1000_TCTL_EXT"},
92 {E1000_TIPG, 1, 1, "E1000_TIPG"},
93 {E1000_DTXCTL, 1, 1, "E1000_DTXCTL"},
94 {E1000_TDBAL(0), 4, 0x100, "E1000_TDBAL"},
95 {E1000_TDBAH(0), 4, 0x100, "E1000_TDBAH"},
96 {E1000_TDLEN(0), 4, 0x100, "E1000_TDLEN"},
97 {E1000_TDH(0), 4, 0x100, "E1000_TDLEN"},
98 {E1000_TDT(0), 4, 0x100, "E1000_TDT"},
99 {E1000_TXDCTL(0), 4, 0x100, "E1000_TXDCTL"},
100 {E1000_TDWBAL(0), 4, 0x100, "E1000_TDWBAL"},
101 {E1000_TDWBAH(0), 4, 0x100, "E1000_TDWBAH"},
102 {E1000_DCA_TXCTRL(0), 4, 0x100, "E1000_DCA_TXCTRL"},
103 {E1000_TDFH, 1, 1, "E1000_TDFH"},
104 {E1000_TDFT, 1, 1, "E1000_TDFT"},
105 {E1000_TDFHS, 1, 1, "E1000_TDFHS"},
106 {E1000_TDFPC, 1, 1, "E1000_TDFPC"},
107 {0, 0, 0, ""}
108 };
109
110 static const struct reg_info igb_regs_wakeup[] = {
111 {E1000_WUC, 1, 1, "E1000_WUC"},
112 {E1000_WUFC, 1, 1, "E1000_WUFC"},
113 {E1000_WUS, 1, 1, "E1000_WUS"},
114 {E1000_IPAV, 1, 1, "E1000_IPAV"},
115 {E1000_WUPL, 1, 1, "E1000_WUPL"},
116 {E1000_IP4AT_REG(0), 4, 8, "E1000_IP4AT_REG"},
117 {E1000_IP6AT_REG(0), 4, 4, "E1000_IP6AT_REG"},
118 {E1000_WUPM_REG(0), 4, 4, "E1000_WUPM_REG"},
119 {E1000_FFMT_REG(0), 4, 8, "E1000_FFMT_REG"},
120 {E1000_FFVT_REG(0), 4, 8, "E1000_FFVT_REG"},
121 {E1000_FFLT_REG(0), 4, 8, "E1000_FFLT_REG"},
122 {0, 0, 0, ""}
123 };
124
125 static const struct reg_info igb_regs_mac[] = {
126 {E1000_PCS_CFG0, 1, 1, "E1000_PCS_CFG0"},
127 {E1000_PCS_LCTL, 1, 1, "E1000_PCS_LCTL"},
128 {E1000_PCS_LSTAT, 1, 1, "E1000_PCS_LSTAT"},
129 {E1000_PCS_ANADV, 1, 1, "E1000_PCS_ANADV"},
130 {E1000_PCS_LPAB, 1, 1, "E1000_PCS_LPAB"},
131 {E1000_PCS_NPTX, 1, 1, "E1000_PCS_NPTX"},
132 {E1000_PCS_LPABNP, 1, 1, "E1000_PCS_LPABNP"},
133 {0, 0, 0, ""}
134 };
135
136 static const struct reg_info *igb_regs[] = {
137 igb_regs_general,
138 igb_regs_nvm,
139 igb_regs_interrupt,
140 igb_regs_fctl,
141 igb_regs_rxdma,
142 igb_regs_rx,
143 igb_regs_tx,
144 igb_regs_wakeup,
145 igb_regs_mac,
146 NULL};
147
148 /* FIXME: reading igb_regs_interrupt results side-effect which doesn't
149 * work with VFIO; re-install igb_regs_interrupt once issue is resolved.
150 */
151 static const struct reg_info *igbvf_regs[] = {
152 igb_regs_general,
153 igb_regs_rxdma,
154 igb_regs_tx,
155 NULL};
156
157 static inline int
igb_read_regs(struct e1000_hw * hw,const struct reg_info * reg,uint32_t * reg_buf)158 igb_read_regs(struct e1000_hw *hw, const struct reg_info *reg,
159 uint32_t *reg_buf)
160 {
161 unsigned int i;
162
163 for (i = 0; i < reg->count; i++) {
164 reg_buf[i] = E1000_READ_REG(hw,
165 reg->base_addr + i * reg->stride);
166 }
167 return reg->count;
168 };
169
170 static inline int
igb_reg_group_count(const struct reg_info * regs)171 igb_reg_group_count(const struct reg_info *regs)
172 {
173 int count = 0;
174 int i = 0;
175
176 while (regs[i].count)
177 count += regs[i++].count;
178 return count;
179 };
180
181 static inline int
igb_read_regs_group(struct rte_eth_dev * dev,uint32_t * reg_buf,const struct reg_info * regs)182 igb_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,
183 const struct reg_info *regs)
184 {
185 int count = 0;
186 int i = 0;
187 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
188
189 while (regs[i].count)
190 count += igb_read_regs(hw, ®s[i++], ®_buf[count]);
191 return count;
192 };
193
194 #endif /* _IGB_REGS_H_ */
195