1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
3 */
4
5 #include "iavf_rxtx_vec_common.h"
6
7 #include <rte_vect.h>
8
9 #ifndef __INTEL_COMPILER
10 #pragma GCC diagnostic ignored "-Wcast-qual"
11 #endif
12
13 static __rte_always_inline void
iavf_rxq_rearm(struct iavf_rx_queue * rxq)14 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
15 {
16 return iavf_rxq_rearm_common(rxq, false);
17 }
18
19 #define PKTLEN_SHIFT 10
20
21 static inline uint16_t
_iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts,uint8_t * split_packet)22 _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
23 struct rte_mbuf **rx_pkts,
24 uint16_t nb_pkts, uint8_t *split_packet)
25 {
26 #define IAVF_DESCS_PER_LOOP_AVX 8
27
28 /* const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; */
29 const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
30
31 const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
32 0, rxq->mbuf_initializer);
33 /* struct iavf_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail]; */
34 struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
35 volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
36 const int avx_aligned = ((rxq->rx_tail & 1) == 0);
37
38 rte_prefetch0(rxdp);
39
40 /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
41 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
42
43 /* See if we need to rearm the RX queue - gives the prefetch a bit
44 * of time to act
45 */
46 if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
47 iavf_rxq_rearm(rxq);
48
49 /* Before we start moving massive data around, check to see if
50 * there is actually a packet available
51 */
52 if (!(rxdp->wb.qword1.status_error_len &
53 rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
54 return 0;
55
56 /* constants used in processing loop */
57 const __m256i crc_adjust =
58 _mm256_set_epi16
59 (/* first descriptor */
60 0, 0, 0, /* ignore non-length fields */
61 -rxq->crc_len, /* sub crc on data_len */
62 0, /* ignore high-16bits of pkt_len */
63 -rxq->crc_len, /* sub crc on pkt_len */
64 0, 0, /* ignore pkt_type field */
65 /* second descriptor */
66 0, 0, 0, /* ignore non-length fields */
67 -rxq->crc_len, /* sub crc on data_len */
68 0, /* ignore high-16bits of pkt_len */
69 -rxq->crc_len, /* sub crc on pkt_len */
70 0, 0 /* ignore pkt_type field */
71 );
72
73 /* 8 packets DD mask, LSB in each 32-bit value */
74 const __m256i dd_check = _mm256_set1_epi32(1);
75
76 /* 8 packets EOP mask, second-LSB in each 32-bit value */
77 const __m256i eop_check = _mm256_slli_epi32(dd_check,
78 IAVF_RX_DESC_STATUS_EOF_SHIFT);
79
80 /* mask to shuffle from desc. to mbuf (2 descriptors)*/
81 const __m256i shuf_msk =
82 _mm256_set_epi8
83 (/* first descriptor */
84 7, 6, 5, 4, /* octet 4~7, 32bits rss */
85 3, 2, /* octet 2~3, low 16 bits vlan_macip */
86 15, 14, /* octet 15~14, 16 bits data_len */
87 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
88 15, 14, /* octet 15~14, low 16 bits pkt_len */
89 0xFF, 0xFF, /* pkt_type set as unknown */
90 0xFF, 0xFF, /*pkt_type set as unknown */
91 /* second descriptor */
92 7, 6, 5, 4, /* octet 4~7, 32bits rss */
93 3, 2, /* octet 2~3, low 16 bits vlan_macip */
94 15, 14, /* octet 15~14, 16 bits data_len */
95 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
96 15, 14, /* octet 15~14, low 16 bits pkt_len */
97 0xFF, 0xFF, /* pkt_type set as unknown */
98 0xFF, 0xFF /*pkt_type set as unknown */
99 );
100 /**
101 * compile-time check the above crc and shuffle layout is correct.
102 * NOTE: the first field (lowest address) is given last in set_epi
103 * calls above.
104 */
105 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
106 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
107 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
108 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
109 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
110 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
111 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
112 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
113
114 /* Status/Error flag masks */
115 /**
116 * mask everything except RSS, flow director and VLAN flags
117 * bit2 is for VLAN tag, bit11 for flow director indication
118 * bit13:12 for RSS indication. Bits 3-5 of error
119 * field (bits 22-24) are for IP/L4 checksum errors
120 */
121 const __m256i flags_mask =
122 _mm256_set1_epi32((1 << 2) | (1 << 11) |
123 (3 << 12) | (7 << 22));
124 /**
125 * data to be shuffled by result of flag mask. If VLAN bit is set,
126 * (bit 2), then position 4 in this array will be used in the
127 * destination
128 */
129 const __m256i vlan_flags_shuf =
130 _mm256_set_epi32(0, 0, RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0,
131 0, 0, RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0);
132 /**
133 * data to be shuffled by result of flag mask, shifted down 11.
134 * If RSS/FDIR bits are set, shuffle moves appropriate flags in
135 * place.
136 */
137 const __m256i rss_flags_shuf =
138 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
139 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR, RTE_MBUF_F_RX_RSS_HASH,
140 0, 0, 0, 0, RTE_MBUF_F_RX_FDIR, 0,/* end up 128-bits */
141 0, 0, 0, 0, 0, 0, 0, 0,
142 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR, RTE_MBUF_F_RX_RSS_HASH,
143 0, 0, 0, 0, RTE_MBUF_F_RX_FDIR, 0);
144
145 /**
146 * data to be shuffled by the result of the flags mask shifted by 22
147 * bits. This gives use the l3_l4 flags.
148 */
149 const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
150 /* shift right 1 bit to make sure it not exceed 255 */
151 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
152 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
153 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
154 RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
155 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
156 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
157 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
158 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
159 RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
160 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
161 /* second 128-bits */
162 0, 0, 0, 0, 0, 0, 0, 0,
163 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
164 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
165 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
166 RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
167 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
168 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
169 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
170 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
171 RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
172 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1);
173
174 const __m256i cksum_mask =
175 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
176 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
177 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
178
179 RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
180
181 uint16_t i, received;
182
183 for (i = 0, received = 0; i < nb_pkts;
184 i += IAVF_DESCS_PER_LOOP_AVX,
185 rxdp += IAVF_DESCS_PER_LOOP_AVX) {
186 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
187 _mm256_storeu_si256((void *)&rx_pkts[i],
188 _mm256_loadu_si256((void *)&sw_ring[i]));
189 #ifdef RTE_ARCH_X86_64
190 _mm256_storeu_si256
191 ((void *)&rx_pkts[i + 4],
192 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
193 #endif
194
195 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
196 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
197 /* for AVX we need alignment otherwise loads are not atomic */
198 if (avx_aligned) {
199 /* load in descriptors, 2 at a time, in reverse order */
200 raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
201 rte_compiler_barrier();
202 raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
203 rte_compiler_barrier();
204 raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
205 rte_compiler_barrier();
206 raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
207 } else
208 #endif
209 {
210 const __m128i raw_desc7 =
211 _mm_load_si128((void *)(rxdp + 7));
212 rte_compiler_barrier();
213 const __m128i raw_desc6 =
214 _mm_load_si128((void *)(rxdp + 6));
215 rte_compiler_barrier();
216 const __m128i raw_desc5 =
217 _mm_load_si128((void *)(rxdp + 5));
218 rte_compiler_barrier();
219 const __m128i raw_desc4 =
220 _mm_load_si128((void *)(rxdp + 4));
221 rte_compiler_barrier();
222 const __m128i raw_desc3 =
223 _mm_load_si128((void *)(rxdp + 3));
224 rte_compiler_barrier();
225 const __m128i raw_desc2 =
226 _mm_load_si128((void *)(rxdp + 2));
227 rte_compiler_barrier();
228 const __m128i raw_desc1 =
229 _mm_load_si128((void *)(rxdp + 1));
230 rte_compiler_barrier();
231 const __m128i raw_desc0 =
232 _mm_load_si128((void *)(rxdp + 0));
233
234 raw_desc6_7 =
235 _mm256_inserti128_si256
236 (_mm256_castsi128_si256(raw_desc6),
237 raw_desc7, 1);
238 raw_desc4_5 =
239 _mm256_inserti128_si256
240 (_mm256_castsi128_si256(raw_desc4),
241 raw_desc5, 1);
242 raw_desc2_3 =
243 _mm256_inserti128_si256
244 (_mm256_castsi128_si256(raw_desc2),
245 raw_desc3, 1);
246 raw_desc0_1 =
247 _mm256_inserti128_si256
248 (_mm256_castsi128_si256(raw_desc0),
249 raw_desc1, 1);
250 }
251
252 if (split_packet) {
253 int j;
254
255 for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
256 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
257 }
258
259 /**
260 * convert descriptors 4-7 into mbufs, adjusting length and
261 * re-arranging fields. Then write into the mbuf
262 */
263 const __m256i len6_7 = _mm256_slli_epi32(raw_desc6_7,
264 PKTLEN_SHIFT);
265 const __m256i len4_5 = _mm256_slli_epi32(raw_desc4_5,
266 PKTLEN_SHIFT);
267 const __m256i desc6_7 = _mm256_blend_epi16(raw_desc6_7,
268 len6_7, 0x80);
269 const __m256i desc4_5 = _mm256_blend_epi16(raw_desc4_5,
270 len4_5, 0x80);
271 __m256i mb6_7 = _mm256_shuffle_epi8(desc6_7, shuf_msk);
272 __m256i mb4_5 = _mm256_shuffle_epi8(desc4_5, shuf_msk);
273
274 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
275 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
276 /**
277 * to get packet types, shift 64-bit values down 30 bits
278 * and so ptype is in lower 8-bits in each
279 */
280 const __m256i ptypes6_7 = _mm256_srli_epi64(desc6_7, 30);
281 const __m256i ptypes4_5 = _mm256_srli_epi64(desc4_5, 30);
282 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
283 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
284 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
285 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
286
287 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
288 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
289 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
290 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
291 /* merge the status bits into one register */
292 const __m256i status4_7 = _mm256_unpackhi_epi32(desc6_7,
293 desc4_5);
294
295 /**
296 * convert descriptors 0-3 into mbufs, adjusting length and
297 * re-arranging fields. Then write into the mbuf
298 */
299 const __m256i len2_3 = _mm256_slli_epi32(raw_desc2_3,
300 PKTLEN_SHIFT);
301 const __m256i len0_1 = _mm256_slli_epi32(raw_desc0_1,
302 PKTLEN_SHIFT);
303 const __m256i desc2_3 = _mm256_blend_epi16(raw_desc2_3,
304 len2_3, 0x80);
305 const __m256i desc0_1 = _mm256_blend_epi16(raw_desc0_1,
306 len0_1, 0x80);
307 __m256i mb2_3 = _mm256_shuffle_epi8(desc2_3, shuf_msk);
308 __m256i mb0_1 = _mm256_shuffle_epi8(desc0_1, shuf_msk);
309
310 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
311 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
312 /* get the packet types */
313 const __m256i ptypes2_3 = _mm256_srli_epi64(desc2_3, 30);
314 const __m256i ptypes0_1 = _mm256_srli_epi64(desc0_1, 30);
315 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
316 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
317 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
318 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
319
320 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
321 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
322 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
323 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
324 /* merge the status bits into one register */
325 const __m256i status0_3 = _mm256_unpackhi_epi32(desc2_3,
326 desc0_1);
327
328 /**
329 * take the two sets of status bits and merge to one
330 * After merge, the packets status flags are in the
331 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
332 */
333 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
334 status0_3);
335
336 /* now do flag manipulation */
337
338 /* get only flag/error bits we want */
339 const __m256i flag_bits =
340 _mm256_and_si256(status0_7, flags_mask);
341 /* set vlan and rss flags */
342 const __m256i vlan_flags =
343 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
344 const __m256i rss_flags =
345 _mm256_shuffle_epi8(rss_flags_shuf,
346 _mm256_srli_epi32(flag_bits, 11));
347 /**
348 * l3_l4_error flags, shuffle, then shift to correct adjustment
349 * of flags in flags_shuf, and finally mask out extra bits
350 */
351 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
352 _mm256_srli_epi32(flag_bits, 22));
353 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
354 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
355
356 /* merge flags */
357 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
358 _mm256_or_si256(rss_flags, vlan_flags));
359 /**
360 * At this point, we have the 8 sets of flags in the low 16-bits
361 * of each 32-bit value in vlan0.
362 * We want to extract these, and merge them with the mbuf init
363 * data so we can do a single write to the mbuf to set the flags
364 * and all the other initialization fields. Extracting the
365 * appropriate flags means that we have to do a shift and blend
366 * for each mbuf before we do the write. However, we can also
367 * add in the previously computed rx_descriptor fields to
368 * make a single 256-bit write per mbuf
369 */
370 /* check the structure matches expectations */
371 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
372 offsetof(struct rte_mbuf, rearm_data) + 8);
373 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
374 RTE_ALIGN(offsetof(struct rte_mbuf,
375 rearm_data),
376 16));
377 /* build up data and do writes */
378 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
379 rearm6, rearm7;
380 rearm6 = _mm256_blend_epi32(mbuf_init,
381 _mm256_slli_si256(mbuf_flags, 8),
382 0x04);
383 rearm4 = _mm256_blend_epi32(mbuf_init,
384 _mm256_slli_si256(mbuf_flags, 4),
385 0x04);
386 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
387 rearm0 = _mm256_blend_epi32(mbuf_init,
388 _mm256_srli_si256(mbuf_flags, 4),
389 0x04);
390 /* permute to add in the rx_descriptor e.g. rss fields */
391 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
392 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
393 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
394 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
395 /* write to mbuf */
396 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
397 rearm6);
398 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
399 rearm4);
400 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
401 rearm2);
402 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
403 rearm0);
404
405 /* repeat for the odd mbufs */
406 const __m256i odd_flags =
407 _mm256_castsi128_si256
408 (_mm256_extracti128_si256(mbuf_flags, 1));
409 rearm7 = _mm256_blend_epi32(mbuf_init,
410 _mm256_slli_si256(odd_flags, 8),
411 0x04);
412 rearm5 = _mm256_blend_epi32(mbuf_init,
413 _mm256_slli_si256(odd_flags, 4),
414 0x04);
415 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
416 rearm1 = _mm256_blend_epi32(mbuf_init,
417 _mm256_srli_si256(odd_flags, 4),
418 0x04);
419 /* since odd mbufs are already in hi 128-bits use blend */
420 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
421 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
422 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
423 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
424 /* again write to mbufs */
425 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
426 rearm7);
427 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
428 rearm5);
429 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
430 rearm3);
431 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
432 rearm1);
433
434 /* extract and record EOP bit */
435 if (split_packet) {
436 const __m128i eop_mask =
437 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
438 const __m256i eop_bits256 = _mm256_and_si256(status0_7,
439 eop_check);
440 /* pack status bits into a single 128-bit register */
441 const __m128i eop_bits =
442 _mm_packus_epi32
443 (_mm256_castsi256_si128(eop_bits256),
444 _mm256_extractf128_si256(eop_bits256,
445 1));
446 /**
447 * flip bits, and mask out the EOP bit, which is now
448 * a split-packet bit i.e. !EOP, rather than EOP one.
449 */
450 __m128i split_bits = _mm_andnot_si128(eop_bits,
451 eop_mask);
452 /**
453 * eop bits are out of order, so we need to shuffle them
454 * back into order again. In doing so, only use low 8
455 * bits, which acts like another pack instruction
456 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
457 * [Since we use epi8, the 16-bit positions are
458 * multiplied by 2 in the eop_shuffle value.]
459 */
460 __m128i eop_shuffle =
461 _mm_set_epi8(/* zero hi 64b */
462 0xFF, 0xFF, 0xFF, 0xFF,
463 0xFF, 0xFF, 0xFF, 0xFF,
464 /* move values to lo 64b */
465 8, 0, 10, 2,
466 12, 4, 14, 6);
467 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
468 *(uint64_t *)split_packet =
469 _mm_cvtsi128_si64(split_bits);
470 split_packet += IAVF_DESCS_PER_LOOP_AVX;
471 }
472
473 /* perform dd_check */
474 status0_7 = _mm256_and_si256(status0_7, dd_check);
475 status0_7 = _mm256_packs_epi32(status0_7,
476 _mm256_setzero_si256());
477
478 uint64_t burst = __builtin_popcountll
479 (_mm_cvtsi128_si64
480 (_mm256_extracti128_si256
481 (status0_7, 1)));
482 burst += __builtin_popcountll
483 (_mm_cvtsi128_si64
484 (_mm256_castsi256_si128(status0_7)));
485 received += burst;
486 if (burst != IAVF_DESCS_PER_LOOP_AVX)
487 break;
488 }
489
490 /* update tail pointers */
491 rxq->rx_tail += received;
492 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
493 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
494 rxq->rx_tail--;
495 received--;
496 }
497 rxq->rxrearm_nb += received;
498 return received;
499 }
500
501 static inline __m256i
flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)502 flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)
503 {
504 #define FDID_MIS_MAGIC 0xFFFFFFFF
505 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR != (1 << 2));
506 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));
507 const __m256i pkt_fdir_bit = _mm256_set1_epi32(RTE_MBUF_F_RX_FDIR |
508 RTE_MBUF_F_RX_FDIR_ID);
509 /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
510 const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
511 __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
512 fdir_mis_mask);
513 /* this XOR op results to bit-reverse the fdir_mask */
514 fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
515 const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
516
517 return fdir_flags;
518 }
519
520 static inline uint16_t
_iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts,uint8_t * split_packet)521 _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
522 struct rte_mbuf **rx_pkts,
523 uint16_t nb_pkts, uint8_t *split_packet)
524 {
525 #define IAVF_DESCS_PER_LOOP_AVX 8
526
527 struct iavf_adapter *adapter = rxq->vsi->adapter;
528
529 uint64_t offloads = adapter->dev_data->dev_conf.rxmode.offloads;
530 const uint32_t *type_table = adapter->ptype_tbl;
531
532 const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
533 0, rxq->mbuf_initializer);
534 struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
535 volatile union iavf_rx_flex_desc *rxdp =
536 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
537
538 rte_prefetch0(rxdp);
539
540 /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
541 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
542
543 /* See if we need to rearm the RX queue - gives the prefetch a bit
544 * of time to act
545 */
546 if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
547 iavf_rxq_rearm(rxq);
548
549 /* Before we start moving massive data around, check to see if
550 * there is actually a packet available
551 */
552 if (!(rxdp->wb.status_error0 &
553 rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
554 return 0;
555
556 /* constants used in processing loop */
557 const __m256i crc_adjust =
558 _mm256_set_epi16
559 (/* first descriptor */
560 0, 0, 0, /* ignore non-length fields */
561 -rxq->crc_len, /* sub crc on data_len */
562 0, /* ignore high-16bits of pkt_len */
563 -rxq->crc_len, /* sub crc on pkt_len */
564 0, 0, /* ignore pkt_type field */
565 /* second descriptor */
566 0, 0, 0, /* ignore non-length fields */
567 -rxq->crc_len, /* sub crc on data_len */
568 0, /* ignore high-16bits of pkt_len */
569 -rxq->crc_len, /* sub crc on pkt_len */
570 0, 0 /* ignore pkt_type field */
571 );
572
573 /* 8 packets DD mask, LSB in each 32-bit value */
574 const __m256i dd_check = _mm256_set1_epi32(1);
575
576 /* 8 packets EOP mask, second-LSB in each 32-bit value */
577 const __m256i eop_check = _mm256_slli_epi32(dd_check,
578 IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
579
580 /* mask to shuffle from desc. to mbuf (2 descriptors)*/
581 const __m256i shuf_msk =
582 _mm256_set_epi8
583 (/* first descriptor */
584 0xFF, 0xFF,
585 0xFF, 0xFF, /* rss hash parsed separately */
586 11, 10, /* octet 10~11, 16 bits vlan_macip */
587 5, 4, /* octet 4~5, 16 bits data_len */
588 0xFF, 0xFF, /* skip hi 16 bits pkt_len, zero out */
589 5, 4, /* octet 4~5, 16 bits pkt_len */
590 0xFF, 0xFF, /* pkt_type set as unknown */
591 0xFF, 0xFF, /*pkt_type set as unknown */
592 /* second descriptor */
593 0xFF, 0xFF,
594 0xFF, 0xFF, /* rss hash parsed separately */
595 11, 10, /* octet 10~11, 16 bits vlan_macip */
596 5, 4, /* octet 4~5, 16 bits data_len */
597 0xFF, 0xFF, /* skip hi 16 bits pkt_len, zero out */
598 5, 4, /* octet 4~5, 16 bits pkt_len */
599 0xFF, 0xFF, /* pkt_type set as unknown */
600 0xFF, 0xFF /*pkt_type set as unknown */
601 );
602 /**
603 * compile-time check the above crc and shuffle layout is correct.
604 * NOTE: the first field (lowest address) is given last in set_epi
605 * calls above.
606 */
607 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
608 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
609 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
610 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
611 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
612 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
613 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
614 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
615
616 /* Status/Error flag masks */
617 /**
618 * mask everything except Checksum Reports, RSS indication
619 * and VLAN indication.
620 * bit6:4 for IP/L4 checksum errors.
621 * bit12 is for RSS indication.
622 * bit13 is for VLAN indication.
623 */
624 const __m256i flags_mask =
625 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
626 /**
627 * data to be shuffled by the result of the flags mask shifted by 4
628 * bits. This gives use the l3_l4 flags.
629 */
630 const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
631 /* shift right 1 bit to make sure it not exceed 255 */
632 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
633 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
634 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
635 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
636 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
637 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
638 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
639 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
640 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
641 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
642 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
643 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
644 /* second 128-bits */
645 0, 0, 0, 0, 0, 0, 0, 0,
646 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
647 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
648 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
649 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
650 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
651 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
652 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
653 RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
654 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
655 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
656 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
657 (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1);
658 const __m256i cksum_mask =
659 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
660 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
661 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
662 /**
663 * data to be shuffled by result of flag mask, shifted down 12.
664 * If RSS(bit12)/VLAN(bit13) are set,
665 * shuffle moves appropriate flags in place.
666 */
667 const __m256i rss_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
668 0, 0, 0, 0,
669 0, 0, 0, 0,
670 RTE_MBUF_F_RX_RSS_HASH, 0,
671 RTE_MBUF_F_RX_RSS_HASH, 0,
672 /* end up 128-bits */
673 0, 0, 0, 0,
674 0, 0, 0, 0,
675 0, 0, 0, 0,
676 RTE_MBUF_F_RX_RSS_HASH, 0,
677 RTE_MBUF_F_RX_RSS_HASH, 0);
678
679 const __m256i vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
680 0, 0, 0, 0,
681 0, 0, 0, 0,
682 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
683 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
684 0, 0,
685 /* end up 128-bits */
686 0, 0, 0, 0,
687 0, 0, 0, 0,
688 0, 0, 0, 0,
689 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
690 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
691 0, 0);
692
693 uint16_t i, received;
694
695 for (i = 0, received = 0; i < nb_pkts;
696 i += IAVF_DESCS_PER_LOOP_AVX,
697 rxdp += IAVF_DESCS_PER_LOOP_AVX) {
698 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
699 _mm256_storeu_si256((void *)&rx_pkts[i],
700 _mm256_loadu_si256((void *)&sw_ring[i]));
701 #ifdef RTE_ARCH_X86_64
702 _mm256_storeu_si256
703 ((void *)&rx_pkts[i + 4],
704 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
705 #endif
706
707 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
708
709 const __m128i raw_desc7 =
710 _mm_load_si128((void *)(rxdp + 7));
711 rte_compiler_barrier();
712 const __m128i raw_desc6 =
713 _mm_load_si128((void *)(rxdp + 6));
714 rte_compiler_barrier();
715 const __m128i raw_desc5 =
716 _mm_load_si128((void *)(rxdp + 5));
717 rte_compiler_barrier();
718 const __m128i raw_desc4 =
719 _mm_load_si128((void *)(rxdp + 4));
720 rte_compiler_barrier();
721 const __m128i raw_desc3 =
722 _mm_load_si128((void *)(rxdp + 3));
723 rte_compiler_barrier();
724 const __m128i raw_desc2 =
725 _mm_load_si128((void *)(rxdp + 2));
726 rte_compiler_barrier();
727 const __m128i raw_desc1 =
728 _mm_load_si128((void *)(rxdp + 1));
729 rte_compiler_barrier();
730 const __m128i raw_desc0 =
731 _mm_load_si128((void *)(rxdp + 0));
732
733 raw_desc6_7 =
734 _mm256_inserti128_si256
735 (_mm256_castsi128_si256(raw_desc6),
736 raw_desc7, 1);
737 raw_desc4_5 =
738 _mm256_inserti128_si256
739 (_mm256_castsi128_si256(raw_desc4),
740 raw_desc5, 1);
741 raw_desc2_3 =
742 _mm256_inserti128_si256
743 (_mm256_castsi128_si256(raw_desc2),
744 raw_desc3, 1);
745 raw_desc0_1 =
746 _mm256_inserti128_si256
747 (_mm256_castsi128_si256(raw_desc0),
748 raw_desc1, 1);
749
750 if (split_packet) {
751 int j;
752
753 for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
754 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
755 }
756
757 /**
758 * convert descriptors 4-7 into mbufs, re-arrange fields.
759 * Then write into the mbuf.
760 */
761 __m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);
762 __m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);
763
764 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
765 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
766 /**
767 * to get packet types, ptype is located in bit16-25
768 * of each 128bits
769 */
770 const __m256i ptype_mask =
771 _mm256_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
772 const __m256i ptypes6_7 =
773 _mm256_and_si256(raw_desc6_7, ptype_mask);
774 const __m256i ptypes4_5 =
775 _mm256_and_si256(raw_desc4_5, ptype_mask);
776 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
777 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
778 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
779 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
780
781 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
782 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
783 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
784 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
785 /* merge the status bits into one register */
786 const __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,
787 raw_desc4_5);
788
789 /**
790 * convert descriptors 0-3 into mbufs, re-arrange fields.
791 * Then write into the mbuf.
792 */
793 __m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);
794 __m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);
795
796 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
797 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
798 /**
799 * to get packet types, ptype is located in bit16-25
800 * of each 128bits
801 */
802 const __m256i ptypes2_3 =
803 _mm256_and_si256(raw_desc2_3, ptype_mask);
804 const __m256i ptypes0_1 =
805 _mm256_and_si256(raw_desc0_1, ptype_mask);
806 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
807 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
808 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
809 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
810
811 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
812 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
813 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
814 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
815 /* merge the status bits into one register */
816 const __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,
817 raw_desc0_1);
818
819 /**
820 * take the two sets of status bits and merge to one
821 * After merge, the packets status flags are in the
822 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
823 */
824 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
825 status0_3);
826
827 /* now do flag manipulation */
828
829 /* get only flag/error bits we want */
830 const __m256i flag_bits =
831 _mm256_and_si256(status0_7, flags_mask);
832 /**
833 * l3_l4_error flags, shuffle, then shift to correct adjustment
834 * of flags in flags_shuf, and finally mask out extra bits
835 */
836 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
837 _mm256_srli_epi32(flag_bits, 4));
838 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
839 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
840
841 /* set rss and vlan flags */
842 const __m256i rss_vlan_flag_bits =
843 _mm256_srli_epi32(flag_bits, 12);
844 const __m256i rss_flags =
845 _mm256_shuffle_epi8(rss_flags_shuf,
846 rss_vlan_flag_bits);
847
848 __m256i vlan_flags = _mm256_setzero_si256();
849
850 if (rxq->rx_flags == IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1)
851 vlan_flags =
852 _mm256_shuffle_epi8(vlan_flags_shuf,
853 rss_vlan_flag_bits);
854
855 const __m256i rss_vlan_flags =
856 _mm256_or_si256(rss_flags, vlan_flags);
857
858 /* merge flags */
859 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
860 rss_vlan_flags);
861
862 if (rxq->fdir_enabled) {
863 const __m256i fdir_id4_7 =
864 _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
865
866 const __m256i fdir_id0_3 =
867 _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
868
869 const __m256i fdir_id0_7 =
870 _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
871
872 const __m256i fdir_flags =
873 flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7);
874
875 /* merge with fdir_flags */
876 mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
877
878 /* write to mbuf: have to use scalar store here */
879 rx_pkts[i + 0]->hash.fdir.hi =
880 _mm256_extract_epi32(fdir_id0_7, 3);
881
882 rx_pkts[i + 1]->hash.fdir.hi =
883 _mm256_extract_epi32(fdir_id0_7, 7);
884
885 rx_pkts[i + 2]->hash.fdir.hi =
886 _mm256_extract_epi32(fdir_id0_7, 2);
887
888 rx_pkts[i + 3]->hash.fdir.hi =
889 _mm256_extract_epi32(fdir_id0_7, 6);
890
891 rx_pkts[i + 4]->hash.fdir.hi =
892 _mm256_extract_epi32(fdir_id0_7, 1);
893
894 rx_pkts[i + 5]->hash.fdir.hi =
895 _mm256_extract_epi32(fdir_id0_7, 5);
896
897 rx_pkts[i + 6]->hash.fdir.hi =
898 _mm256_extract_epi32(fdir_id0_7, 0);
899
900 rx_pkts[i + 7]->hash.fdir.hi =
901 _mm256_extract_epi32(fdir_id0_7, 4);
902 } /* if() on fdir_enabled */
903
904 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
905 /**
906 * needs to load 2nd 16B of each desc for RSS hash parsing,
907 * will cause performance drop to get into this context.
908 */
909 if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH ||
910 rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
911 /* load bottom half of every 32B desc */
912 const __m128i raw_desc_bh7 =
913 _mm_load_si128
914 ((void *)(&rxdp[7].wb.status_error1));
915 rte_compiler_barrier();
916 const __m128i raw_desc_bh6 =
917 _mm_load_si128
918 ((void *)(&rxdp[6].wb.status_error1));
919 rte_compiler_barrier();
920 const __m128i raw_desc_bh5 =
921 _mm_load_si128
922 ((void *)(&rxdp[5].wb.status_error1));
923 rte_compiler_barrier();
924 const __m128i raw_desc_bh4 =
925 _mm_load_si128
926 ((void *)(&rxdp[4].wb.status_error1));
927 rte_compiler_barrier();
928 const __m128i raw_desc_bh3 =
929 _mm_load_si128
930 ((void *)(&rxdp[3].wb.status_error1));
931 rte_compiler_barrier();
932 const __m128i raw_desc_bh2 =
933 _mm_load_si128
934 ((void *)(&rxdp[2].wb.status_error1));
935 rte_compiler_barrier();
936 const __m128i raw_desc_bh1 =
937 _mm_load_si128
938 ((void *)(&rxdp[1].wb.status_error1));
939 rte_compiler_barrier();
940 const __m128i raw_desc_bh0 =
941 _mm_load_si128
942 ((void *)(&rxdp[0].wb.status_error1));
943
944 __m256i raw_desc_bh6_7 =
945 _mm256_inserti128_si256
946 (_mm256_castsi128_si256(raw_desc_bh6),
947 raw_desc_bh7, 1);
948 __m256i raw_desc_bh4_5 =
949 _mm256_inserti128_si256
950 (_mm256_castsi128_si256(raw_desc_bh4),
951 raw_desc_bh5, 1);
952 __m256i raw_desc_bh2_3 =
953 _mm256_inserti128_si256
954 (_mm256_castsi128_si256(raw_desc_bh2),
955 raw_desc_bh3, 1);
956 __m256i raw_desc_bh0_1 =
957 _mm256_inserti128_si256
958 (_mm256_castsi128_si256(raw_desc_bh0),
959 raw_desc_bh1, 1);
960
961 if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH) {
962 /**
963 * to shift the 32b RSS hash value to the
964 * highest 32b of each 128b before mask
965 */
966 __m256i rss_hash6_7 =
967 _mm256_slli_epi64(raw_desc_bh6_7, 32);
968 __m256i rss_hash4_5 =
969 _mm256_slli_epi64(raw_desc_bh4_5, 32);
970 __m256i rss_hash2_3 =
971 _mm256_slli_epi64(raw_desc_bh2_3, 32);
972 __m256i rss_hash0_1 =
973 _mm256_slli_epi64(raw_desc_bh0_1, 32);
974
975 const __m256i rss_hash_msk =
976 _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
977 0xFFFFFFFF, 0, 0, 0);
978
979 rss_hash6_7 = _mm256_and_si256
980 (rss_hash6_7, rss_hash_msk);
981 rss_hash4_5 = _mm256_and_si256
982 (rss_hash4_5, rss_hash_msk);
983 rss_hash2_3 = _mm256_and_si256
984 (rss_hash2_3, rss_hash_msk);
985 rss_hash0_1 = _mm256_and_si256
986 (rss_hash0_1, rss_hash_msk);
987
988 mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
989 mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
990 mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
991 mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
992 }
993
994 if (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
995 /* merge the status/error-1 bits into one register */
996 const __m256i status1_4_7 =
997 _mm256_unpacklo_epi32(raw_desc_bh6_7,
998 raw_desc_bh4_5);
999 const __m256i status1_0_3 =
1000 _mm256_unpacklo_epi32(raw_desc_bh2_3,
1001 raw_desc_bh0_1);
1002
1003 const __m256i status1_0_7 =
1004 _mm256_unpacklo_epi64(status1_4_7,
1005 status1_0_3);
1006
1007 const __m256i l2tag2p_flag_mask =
1008 _mm256_set1_epi32
1009 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1010
1011 __m256i l2tag2p_flag_bits =
1012 _mm256_and_si256
1013 (status1_0_7, l2tag2p_flag_mask);
1014
1015 l2tag2p_flag_bits =
1016 _mm256_srli_epi32(l2tag2p_flag_bits,
1017 IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1018
1019 const __m256i l2tag2_flags_shuf =
1020 _mm256_set_epi8(0, 0, 0, 0,
1021 0, 0, 0, 0,
1022 0, 0, 0, 0,
1023 0, 0, 0, 0,
1024 /* end up 128-bits */
1025 0, 0, 0, 0,
1026 0, 0, 0, 0,
1027 0, 0, 0, 0,
1028 0, 0,
1029 RTE_MBUF_F_RX_VLAN |
1030 RTE_MBUF_F_RX_VLAN_STRIPPED,
1031 0);
1032
1033 vlan_flags =
1034 _mm256_shuffle_epi8(l2tag2_flags_shuf,
1035 l2tag2p_flag_bits);
1036
1037 /* merge with vlan_flags */
1038 mbuf_flags = _mm256_or_si256
1039 (mbuf_flags, vlan_flags);
1040
1041 /* L2TAG2_2 */
1042 __m256i vlan_tci6_7 =
1043 _mm256_slli_si256(raw_desc_bh6_7, 4);
1044 __m256i vlan_tci4_5 =
1045 _mm256_slli_si256(raw_desc_bh4_5, 4);
1046 __m256i vlan_tci2_3 =
1047 _mm256_slli_si256(raw_desc_bh2_3, 4);
1048 __m256i vlan_tci0_1 =
1049 _mm256_slli_si256(raw_desc_bh0_1, 4);
1050
1051 const __m256i vlan_tci_msk =
1052 _mm256_set_epi32(0, 0xFFFF0000, 0, 0,
1053 0, 0xFFFF0000, 0, 0);
1054
1055 vlan_tci6_7 = _mm256_and_si256
1056 (vlan_tci6_7, vlan_tci_msk);
1057 vlan_tci4_5 = _mm256_and_si256
1058 (vlan_tci4_5, vlan_tci_msk);
1059 vlan_tci2_3 = _mm256_and_si256
1060 (vlan_tci2_3, vlan_tci_msk);
1061 vlan_tci0_1 = _mm256_and_si256
1062 (vlan_tci0_1, vlan_tci_msk);
1063
1064 mb6_7 = _mm256_or_si256(mb6_7, vlan_tci6_7);
1065 mb4_5 = _mm256_or_si256(mb4_5, vlan_tci4_5);
1066 mb2_3 = _mm256_or_si256(mb2_3, vlan_tci2_3);
1067 mb0_1 = _mm256_or_si256(mb0_1, vlan_tci0_1);
1068 }
1069 } /* if() on RSS hash parsing */
1070 #endif
1071
1072 /**
1073 * At this point, we have the 8 sets of flags in the low 16-bits
1074 * of each 32-bit value in vlan0.
1075 * We want to extract these, and merge them with the mbuf init
1076 * data so we can do a single write to the mbuf to set the flags
1077 * and all the other initialization fields. Extracting the
1078 * appropriate flags means that we have to do a shift and blend
1079 * for each mbuf before we do the write. However, we can also
1080 * add in the previously computed rx_descriptor fields to
1081 * make a single 256-bit write per mbuf
1082 */
1083 /* check the structure matches expectations */
1084 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1085 offsetof(struct rte_mbuf, rearm_data) + 8);
1086 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1087 RTE_ALIGN(offsetof(struct rte_mbuf,
1088 rearm_data),
1089 16));
1090 /* build up data and do writes */
1091 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1092 rearm6, rearm7;
1093 rearm6 = _mm256_blend_epi32(mbuf_init,
1094 _mm256_slli_si256(mbuf_flags, 8),
1095 0x04);
1096 rearm4 = _mm256_blend_epi32(mbuf_init,
1097 _mm256_slli_si256(mbuf_flags, 4),
1098 0x04);
1099 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1100 rearm0 = _mm256_blend_epi32(mbuf_init,
1101 _mm256_srli_si256(mbuf_flags, 4),
1102 0x04);
1103 /* permute to add in the rx_descriptor e.g. rss fields */
1104 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1105 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1106 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1107 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1108 /* write to mbuf */
1109 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1110 rearm6);
1111 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1112 rearm4);
1113 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1114 rearm2);
1115 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1116 rearm0);
1117
1118 /* repeat for the odd mbufs */
1119 const __m256i odd_flags =
1120 _mm256_castsi128_si256
1121 (_mm256_extracti128_si256(mbuf_flags, 1));
1122 rearm7 = _mm256_blend_epi32(mbuf_init,
1123 _mm256_slli_si256(odd_flags, 8),
1124 0x04);
1125 rearm5 = _mm256_blend_epi32(mbuf_init,
1126 _mm256_slli_si256(odd_flags, 4),
1127 0x04);
1128 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1129 rearm1 = _mm256_blend_epi32(mbuf_init,
1130 _mm256_srli_si256(odd_flags, 4),
1131 0x04);
1132 /* since odd mbufs are already in hi 128-bits use blend */
1133 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1134 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1135 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1136 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1137 /* again write to mbufs */
1138 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1139 rearm7);
1140 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1141 rearm5);
1142 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1143 rearm3);
1144 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1145 rearm1);
1146
1147 /* extract and record EOP bit */
1148 if (split_packet) {
1149 const __m128i eop_mask =
1150 _mm_set1_epi16(1 <<
1151 IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1152 const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1153 eop_check);
1154 /* pack status bits into a single 128-bit register */
1155 const __m128i eop_bits =
1156 _mm_packus_epi32
1157 (_mm256_castsi256_si128(eop_bits256),
1158 _mm256_extractf128_si256(eop_bits256,
1159 1));
1160 /**
1161 * flip bits, and mask out the EOP bit, which is now
1162 * a split-packet bit i.e. !EOP, rather than EOP one.
1163 */
1164 __m128i split_bits = _mm_andnot_si128(eop_bits,
1165 eop_mask);
1166 /**
1167 * eop bits are out of order, so we need to shuffle them
1168 * back into order again. In doing so, only use low 8
1169 * bits, which acts like another pack instruction
1170 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1171 * [Since we use epi8, the 16-bit positions are
1172 * multiplied by 2 in the eop_shuffle value.]
1173 */
1174 __m128i eop_shuffle =
1175 _mm_set_epi8(/* zero hi 64b */
1176 0xFF, 0xFF, 0xFF, 0xFF,
1177 0xFF, 0xFF, 0xFF, 0xFF,
1178 /* move values to lo 64b */
1179 8, 0, 10, 2,
1180 12, 4, 14, 6);
1181 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1182 *(uint64_t *)split_packet =
1183 _mm_cvtsi128_si64(split_bits);
1184 split_packet += IAVF_DESCS_PER_LOOP_AVX;
1185 }
1186
1187 /* perform dd_check */
1188 status0_7 = _mm256_and_si256(status0_7, dd_check);
1189 status0_7 = _mm256_packs_epi32(status0_7,
1190 _mm256_setzero_si256());
1191
1192 uint64_t burst = __builtin_popcountll
1193 (_mm_cvtsi128_si64
1194 (_mm256_extracti128_si256
1195 (status0_7, 1)));
1196 burst += __builtin_popcountll
1197 (_mm_cvtsi128_si64
1198 (_mm256_castsi256_si128(status0_7)));
1199 received += burst;
1200 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1201 break;
1202 }
1203
1204 /* update tail pointers */
1205 rxq->rx_tail += received;
1206 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1207 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
1208 rxq->rx_tail--;
1209 received--;
1210 }
1211 rxq->rxrearm_nb += received;
1212 return received;
1213 }
1214
1215 /**
1216 * Notice:
1217 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1218 */
1219 uint16_t
iavf_recv_pkts_vec_avx2(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1220 iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1221 uint16_t nb_pkts)
1222 {
1223 return _iavf_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
1224 }
1225
1226 /**
1227 * Notice:
1228 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1229 */
1230 uint16_t
iavf_recv_pkts_vec_avx2_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1231 iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1232 uint16_t nb_pkts)
1233 {
1234 return _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rx_queue, rx_pkts,
1235 nb_pkts, NULL);
1236 }
1237
1238 /**
1239 * vPMD receive routine that reassembles single burst of 32 scattered packets
1240 * Notice:
1241 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1242 */
1243 static uint16_t
iavf_recv_scattered_burst_vec_avx2(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1244 iavf_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1245 uint16_t nb_pkts)
1246 {
1247 struct iavf_rx_queue *rxq = rx_queue;
1248 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1249
1250 /* get some new buffers */
1251 uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
1252 split_flags);
1253 if (nb_bufs == 0)
1254 return 0;
1255
1256 /* happy day case, full burst + no packets to be joined */
1257 const uint64_t *split_fl64 = (uint64_t *)split_flags;
1258
1259 if (!rxq->pkt_first_seg &&
1260 split_fl64[0] == 0 && split_fl64[1] == 0 &&
1261 split_fl64[2] == 0 && split_fl64[3] == 0)
1262 return nb_bufs;
1263
1264 /* reassemble any packets that need reassembly*/
1265 unsigned int i = 0;
1266
1267 if (!rxq->pkt_first_seg) {
1268 /* find the first split flag, and only reassemble then*/
1269 while (i < nb_bufs && !split_flags[i])
1270 i++;
1271 if (i == nb_bufs)
1272 return nb_bufs;
1273 rxq->pkt_first_seg = rx_pkts[i];
1274 }
1275 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1276 &split_flags[i]);
1277 }
1278
1279 /**
1280 * vPMD receive routine that reassembles scattered packets.
1281 * Main receive routine that can handle arbitrary burst sizes
1282 * Notice:
1283 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1284 */
1285 uint16_t
iavf_recv_scattered_pkts_vec_avx2(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1286 iavf_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
1287 uint16_t nb_pkts)
1288 {
1289 uint16_t retval = 0;
1290
1291 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1292 uint16_t burst = iavf_recv_scattered_burst_vec_avx2(rx_queue,
1293 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
1294 retval += burst;
1295 nb_pkts -= burst;
1296 if (burst < IAVF_VPMD_RX_MAX_BURST)
1297 return retval;
1298 }
1299 return retval + iavf_recv_scattered_burst_vec_avx2(rx_queue,
1300 rx_pkts + retval, nb_pkts);
1301 }
1302
1303 /**
1304 * vPMD receive routine that reassembles single burst of
1305 * 32 scattered packets for flex RxD
1306 * Notice:
1307 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1308 */
1309 static uint16_t
iavf_recv_scattered_burst_vec_avx2_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1310 iavf_recv_scattered_burst_vec_avx2_flex_rxd(void *rx_queue,
1311 struct rte_mbuf **rx_pkts,
1312 uint16_t nb_pkts)
1313 {
1314 struct iavf_rx_queue *rxq = rx_queue;
1315 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1316
1317 /* get some new buffers */
1318 uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2_flex_rxd(rxq,
1319 rx_pkts, nb_pkts, split_flags);
1320 if (nb_bufs == 0)
1321 return 0;
1322
1323 /* happy day case, full burst + no packets to be joined */
1324 const uint64_t *split_fl64 = (uint64_t *)split_flags;
1325
1326 if (!rxq->pkt_first_seg &&
1327 split_fl64[0] == 0 && split_fl64[1] == 0 &&
1328 split_fl64[2] == 0 && split_fl64[3] == 0)
1329 return nb_bufs;
1330
1331 /* reassemble any packets that need reassembly*/
1332 unsigned int i = 0;
1333
1334 if (!rxq->pkt_first_seg) {
1335 /* find the first split flag, and only reassemble then*/
1336 while (i < nb_bufs && !split_flags[i])
1337 i++;
1338 if (i == nb_bufs)
1339 return nb_bufs;
1340 rxq->pkt_first_seg = rx_pkts[i];
1341 }
1342 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1343 &split_flags[i]);
1344 }
1345
1346 /**
1347 * vPMD receive routine that reassembles scattered packets for flex RxD.
1348 * Main receive routine that can handle arbitrary burst sizes
1349 * Notice:
1350 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1351 */
1352 uint16_t
iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)1353 iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
1354 struct rte_mbuf **rx_pkts,
1355 uint16_t nb_pkts)
1356 {
1357 uint16_t retval = 0;
1358
1359 while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1360 uint16_t burst =
1361 iavf_recv_scattered_burst_vec_avx2_flex_rxd
1362 (rx_queue, rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
1363 retval += burst;
1364 nb_pkts -= burst;
1365 if (burst < IAVF_VPMD_RX_MAX_BURST)
1366 return retval;
1367 }
1368 return retval + iavf_recv_scattered_burst_vec_avx2_flex_rxd(rx_queue,
1369 rx_pkts + retval, nb_pkts);
1370 }
1371
1372 static inline void
iavf_vtx1(volatile struct iavf_tx_desc * txdp,struct rte_mbuf * pkt,uint64_t flags)1373 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1374 struct rte_mbuf *pkt, uint64_t flags)
1375 {
1376 uint64_t high_qw =
1377 (IAVF_TX_DESC_DTYPE_DATA |
1378 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |
1379 ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1380
1381 __m128i descriptor = _mm_set_epi64x(high_qw,
1382 pkt->buf_iova + pkt->data_off);
1383 _mm_store_si128((__m128i *)txdp, descriptor);
1384 }
1385
1386 static inline void
iavf_vtx(volatile struct iavf_tx_desc * txdp,struct rte_mbuf ** pkt,uint16_t nb_pkts,uint64_t flags)1387 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1388 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
1389 {
1390 const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1391 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));
1392
1393 /* if unaligned on 32-bit boundary, do one to align */
1394 if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1395 iavf_vtx1(txdp, *pkt, flags);
1396 nb_pkts--, txdp++, pkt++;
1397 }
1398
1399 /* do two at a time while possible, in bursts */
1400 for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1401 uint64_t hi_qw3 =
1402 hi_qw_tmpl |
1403 ((uint64_t)pkt[3]->data_len <<
1404 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1405 uint64_t hi_qw2 =
1406 hi_qw_tmpl |
1407 ((uint64_t)pkt[2]->data_len <<
1408 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1409 uint64_t hi_qw1 =
1410 hi_qw_tmpl |
1411 ((uint64_t)pkt[1]->data_len <<
1412 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1413 uint64_t hi_qw0 =
1414 hi_qw_tmpl |
1415 ((uint64_t)pkt[0]->data_len <<
1416 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1417
1418 __m256i desc2_3 =
1419 _mm256_set_epi64x
1420 (hi_qw3,
1421 pkt[3]->buf_iova + pkt[3]->data_off,
1422 hi_qw2,
1423 pkt[2]->buf_iova + pkt[2]->data_off);
1424 __m256i desc0_1 =
1425 _mm256_set_epi64x
1426 (hi_qw1,
1427 pkt[1]->buf_iova + pkt[1]->data_off,
1428 hi_qw0,
1429 pkt[0]->buf_iova + pkt[0]->data_off);
1430 _mm256_store_si256((void *)(txdp + 2), desc2_3);
1431 _mm256_store_si256((void *)txdp, desc0_1);
1432 }
1433
1434 /* do any last ones */
1435 while (nb_pkts) {
1436 iavf_vtx1(txdp, *pkt, flags);
1437 txdp++, pkt++, nb_pkts--;
1438 }
1439 }
1440
1441 static inline uint16_t
iavf_xmit_fixed_burst_vec_avx2(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1442 iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
1443 uint16_t nb_pkts)
1444 {
1445 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1446 volatile struct iavf_tx_desc *txdp;
1447 struct iavf_tx_entry *txep;
1448 uint16_t n, nb_commit, tx_id;
1449 /* bit2 is reserved and must be set to 1 according to Spec */
1450 uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1451 uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1452
1453 if (txq->nb_free < txq->free_thresh)
1454 iavf_tx_free_bufs(txq);
1455
1456 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1457 if (unlikely(nb_pkts == 0))
1458 return 0;
1459
1460 tx_id = txq->tx_tail;
1461 txdp = &txq->tx_ring[tx_id];
1462 txep = &txq->sw_ring[tx_id];
1463
1464 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1465
1466 n = (uint16_t)(txq->nb_tx_desc - tx_id);
1467 if (nb_commit >= n) {
1468 tx_backlog_entry(txep, tx_pkts, n);
1469
1470 iavf_vtx(txdp, tx_pkts, n - 1, flags);
1471 tx_pkts += (n - 1);
1472 txdp += (n - 1);
1473
1474 iavf_vtx1(txdp, *tx_pkts++, rs);
1475
1476 nb_commit = (uint16_t)(nb_commit - n);
1477
1478 tx_id = 0;
1479 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1480
1481 /* avoid reach the end of ring */
1482 txdp = &txq->tx_ring[tx_id];
1483 txep = &txq->sw_ring[tx_id];
1484 }
1485
1486 tx_backlog_entry(txep, tx_pkts, nb_commit);
1487
1488 iavf_vtx(txdp, tx_pkts, nb_commit, flags);
1489
1490 tx_id = (uint16_t)(tx_id + nb_commit);
1491 if (tx_id > txq->next_rs) {
1492 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1493 rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1494 IAVF_TXD_QW1_CMD_SHIFT);
1495 txq->next_rs =
1496 (uint16_t)(txq->next_rs + txq->rs_thresh);
1497 }
1498
1499 txq->tx_tail = tx_id;
1500
1501 IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1502
1503 return nb_pkts;
1504 }
1505
1506 uint16_t
iavf_xmit_pkts_vec_avx2(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)1507 iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
1508 uint16_t nb_pkts)
1509 {
1510 uint16_t nb_tx = 0;
1511 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1512
1513 while (nb_pkts) {
1514 uint16_t ret, num;
1515
1516 /* cross rs_thresh boundary is not allowed */
1517 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1518 ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
1519 num);
1520 nb_tx += ret;
1521 nb_pkts -= ret;
1522 if (ret < num)
1523 break;
1524 }
1525
1526 return nb_tx;
1527 }
1528