1; SPDX-License-Identifier: BSD-3-Clause 2; Copyright(c) 2020 Intel Corporation 3 4mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 5 6link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 7link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 8link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 9link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 10 11pipeline PIPELINE0 create 0 12 13pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32 14pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32 15pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32 16pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32 17 18pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 19pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 20pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 21pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 22pipeline PIPELINE0 port out 4 sink none 23 24pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec 25pipeline PIPELINE0 table vxlan_table update ./examples/pipeline/examples/vxlan_table.txt none none 26 27thread 1 pipeline PIPELINE0 enable 28