1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 */
5
6 #include "enic_compat.h"
7 #include "rte_ethdev_driver.h"
8 #include "wq_enet_desc.h"
9 #include "rq_enet_desc.h"
10 #include "cq_enet_desc.h"
11 #include "vnic_resource.h"
12 #include "vnic_enet.h"
13 #include "vnic_dev.h"
14 #include "vnic_wq.h"
15 #include "vnic_rq.h"
16 #include "vnic_cq.h"
17 #include "vnic_intr.h"
18 #include "vnic_stats.h"
19 #include "vnic_nic.h"
20 #include "vnic_rss.h"
21 #include "enic_res.h"
22 #include "enic.h"
23
enic_get_vnic_config(struct enic * enic)24 int enic_get_vnic_config(struct enic *enic)
25 {
26 struct vnic_enet_config *c = &enic->config;
27 int err;
28
29 err = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);
30 if (err) {
31 dev_err(enic_get_dev(enic),
32 "Error getting MAC addr, %d\n", err);
33 return err;
34 }
35
36
37 #define GET_CONFIG(m) \
38 do { \
39 err = vnic_dev_spec(enic->vdev, \
40 offsetof(struct vnic_enet_config, m), \
41 sizeof(c->m), &c->m); \
42 if (err) { \
43 dev_err(enic_get_dev(enic), \
44 "Error getting %s, %d\n", #m, err); \
45 return err; \
46 } \
47 } while (0)
48
49 GET_CONFIG(flags);
50 GET_CONFIG(wq_desc_count);
51 GET_CONFIG(rq_desc_count);
52 GET_CONFIG(mtu);
53 GET_CONFIG(intr_timer_type);
54 GET_CONFIG(intr_mode);
55 GET_CONFIG(intr_timer_usec);
56 GET_CONFIG(loop_tag);
57 GET_CONFIG(num_arfs);
58 GET_CONFIG(max_pkt_size);
59
60 /* max packet size is only defined in newer VIC firmware
61 * and will be 0 for legacy firmware and VICs
62 */
63 if (c->max_pkt_size > ENIC_DEFAULT_RX_MAX_PKT_SIZE)
64 enic->max_mtu = c->max_pkt_size - RTE_ETHER_HDR_LEN;
65 else
66 enic->max_mtu = ENIC_DEFAULT_RX_MAX_PKT_SIZE -
67 RTE_ETHER_HDR_LEN;
68 if (c->mtu == 0)
69 c->mtu = 1500;
70
71 enic->rte_dev->data->mtu = RTE_MIN(enic->max_mtu,
72 RTE_MAX((uint16_t)ENIC_MIN_MTU, c->mtu));
73
74 enic->adv_filters = vnic_dev_capable_adv_filters(enic->vdev);
75 dev_info(enic, "Advanced Filters %savailable\n", ((enic->adv_filters)
76 ? "" : "not "));
77
78 err = vnic_dev_capable_filter_mode(enic->vdev, &enic->flow_filter_mode,
79 &enic->filter_actions);
80 if (err) {
81 dev_err(enic_get_dev(enic),
82 "Error getting filter modes, %d\n", err);
83 return err;
84 }
85 vnic_dev_capable_udp_rss_weak(enic->vdev, &enic->nic_cfg_chk,
86 &enic->udp_rss_weak);
87
88 dev_info(enic, "Flow api filter mode: %s Actions: %s%s%s%s\n",
89 ((enic->flow_filter_mode == FILTER_FLOWMAN) ? "FLOWMAN" :
90 ((enic->flow_filter_mode == FILTER_DPDK_1) ? "DPDK" :
91 ((enic->flow_filter_mode == FILTER_USNIC_IP) ? "USNIC" :
92 ((enic->flow_filter_mode == FILTER_IPV4_5TUPLE) ? "5TUPLE" :
93 "NONE")))),
94 ((enic->filter_actions & FILTER_ACTION_RQ_STEERING_FLAG) ?
95 "steer " : ""),
96 ((enic->filter_actions & FILTER_ACTION_FILTER_ID_FLAG) ?
97 "tag " : ""),
98 ((enic->filter_actions & FILTER_ACTION_DROP_FLAG) ?
99 "drop " : ""),
100 ((enic->filter_actions & FILTER_ACTION_COUNTER_FLAG) ?
101 "count " : ""));
102
103 c->wq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_WQ_DESCS,
104 RTE_MAX((uint32_t)ENIC_MIN_WQ_DESCS, c->wq_desc_count));
105 c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
106
107 c->rq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_RQ_DESCS,
108 RTE_MAX((uint32_t)ENIC_MIN_RQ_DESCS, c->rq_desc_count));
109 c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
110
111 c->intr_timer_usec = RTE_MIN(c->intr_timer_usec,
112 vnic_dev_get_intr_coal_timer_max(enic->vdev));
113
114 dev_info(enic_get_dev(enic),
115 "vNIC MAC addr %02x:%02x:%02x:%02x:%02x:%02x "
116 "wq/rq %d/%d mtu %d, max mtu:%d\n",
117 enic->mac_addr[0], enic->mac_addr[1], enic->mac_addr[2],
118 enic->mac_addr[3], enic->mac_addr[4], enic->mac_addr[5],
119 c->wq_desc_count, c->rq_desc_count,
120 enic->rte_dev->data->mtu, enic->max_mtu);
121 dev_info(enic_get_dev(enic), "vNIC csum tx/rx %s/%s "
122 "rss %s intr mode %s type %s timer %d usec "
123 "loopback tag 0x%04x\n",
124 ENIC_SETTING(enic, TXCSUM) ? "yes" : "no",
125 ENIC_SETTING(enic, RXCSUM) ? "yes" : "no",
126 ENIC_SETTING(enic, RSS) ?
127 (ENIC_SETTING(enic, RSSHASH_UDPIPV4) ? "+UDP" :
128 ((enic->udp_rss_weak ? "+udp" :
129 "yes"))) : "no",
130 c->intr_mode == VENET_INTR_MODE_INTX ? "INTx" :
131 c->intr_mode == VENET_INTR_MODE_MSI ? "MSI" :
132 c->intr_mode == VENET_INTR_MODE_ANY ? "any" :
133 "unknown",
134 c->intr_timer_type == VENET_INTR_TYPE_MIN ? "min" :
135 c->intr_timer_type == VENET_INTR_TYPE_IDLE ? "idle" :
136 "unknown",
137 c->intr_timer_usec,
138 c->loop_tag);
139
140 /* RSS settings from vNIC */
141 enic->reta_size = ENIC_RSS_RETA_SIZE;
142 enic->hash_key_size = ENIC_RSS_HASH_KEY_SIZE;
143 enic->flow_type_rss_offloads = 0;
144 if (ENIC_SETTING(enic, RSSHASH_IPV4))
145 /*
146 * IPV4 hash type handles both non-frag and frag packet types.
147 * TCP/UDP is controlled via a separate flag below.
148 */
149 enic->flow_type_rss_offloads |= ETH_RSS_IPV4 |
150 ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER;
151 if (ENIC_SETTING(enic, RSSHASH_TCPIPV4))
152 enic->flow_type_rss_offloads |= ETH_RSS_NONFRAG_IPV4_TCP;
153 if (ENIC_SETTING(enic, RSSHASH_IPV6))
154 /*
155 * The VIC adapter can perform RSS on IPv6 packets with and
156 * without extension headers. An IPv6 "fragment" is an IPv6
157 * packet with the fragment extension header.
158 */
159 enic->flow_type_rss_offloads |= ETH_RSS_IPV6 |
160 ETH_RSS_IPV6_EX | ETH_RSS_FRAG_IPV6 |
161 ETH_RSS_NONFRAG_IPV6_OTHER;
162 if (ENIC_SETTING(enic, RSSHASH_TCPIPV6))
163 enic->flow_type_rss_offloads |= ETH_RSS_NONFRAG_IPV6_TCP |
164 ETH_RSS_IPV6_TCP_EX;
165 if (enic->udp_rss_weak)
166 enic->flow_type_rss_offloads |=
167 ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP |
168 ETH_RSS_IPV6_UDP_EX;
169 if (ENIC_SETTING(enic, RSSHASH_UDPIPV4))
170 enic->flow_type_rss_offloads |= ETH_RSS_NONFRAG_IPV4_UDP;
171 if (ENIC_SETTING(enic, RSSHASH_UDPIPV6))
172 enic->flow_type_rss_offloads |= ETH_RSS_NONFRAG_IPV6_UDP |
173 ETH_RSS_IPV6_UDP_EX;
174
175 /* Zero offloads if RSS is not enabled */
176 if (!ENIC_SETTING(enic, RSS))
177 enic->flow_type_rss_offloads = 0;
178
179 enic->vxlan = ENIC_SETTING(enic, VXLAN) &&
180 vnic_dev_capable_vxlan(enic->vdev);
181 if (vnic_dev_capable_geneve(enic->vdev)) {
182 dev_info(NULL, "Geneve with options offload available\n");
183 enic->geneve_opt_avail = 1;
184 }
185 /*
186 * Default hardware capabilities. enic_dev_init() may add additional
187 * flags if it enables overlay offloads.
188 */
189 enic->tx_queue_offload_capa = 0;
190 enic->tx_offload_capa =
191 enic->tx_queue_offload_capa |
192 DEV_TX_OFFLOAD_MULTI_SEGS |
193 DEV_TX_OFFLOAD_VLAN_INSERT |
194 DEV_TX_OFFLOAD_IPV4_CKSUM |
195 DEV_TX_OFFLOAD_UDP_CKSUM |
196 DEV_TX_OFFLOAD_TCP_CKSUM |
197 DEV_TX_OFFLOAD_TCP_TSO;
198 enic->rx_offload_capa =
199 DEV_RX_OFFLOAD_SCATTER |
200 DEV_RX_OFFLOAD_JUMBO_FRAME |
201 DEV_RX_OFFLOAD_VLAN_STRIP |
202 DEV_RX_OFFLOAD_IPV4_CKSUM |
203 DEV_RX_OFFLOAD_UDP_CKSUM |
204 DEV_RX_OFFLOAD_TCP_CKSUM |
205 DEV_RX_OFFLOAD_RSS_HASH;
206 enic->tx_offload_mask =
207 PKT_TX_IPV6 |
208 PKT_TX_IPV4 |
209 PKT_TX_VLAN |
210 PKT_TX_IP_CKSUM |
211 PKT_TX_L4_MASK |
212 PKT_TX_TCP_SEG;
213
214 return 0;
215 }
216
enic_set_nic_cfg(struct enic * enic,uint8_t rss_default_cpu,uint8_t rss_hash_type,uint8_t rss_hash_bits,uint8_t rss_base_cpu,uint8_t rss_enable,uint8_t tso_ipid_split_en,uint8_t ig_vlan_strip_en)217 int enic_set_nic_cfg(struct enic *enic, uint8_t rss_default_cpu,
218 uint8_t rss_hash_type, uint8_t rss_hash_bits,
219 uint8_t rss_base_cpu, uint8_t rss_enable,
220 uint8_t tso_ipid_split_en, uint8_t ig_vlan_strip_en)
221 {
222 enum vnic_devcmd_cmd cmd;
223 uint64_t a0, a1;
224 uint32_t nic_cfg;
225 int wait = 1000;
226
227 vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
228 rss_hash_type, rss_hash_bits, rss_base_cpu,
229 rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
230
231 a0 = nic_cfg;
232 a1 = 0;
233 cmd = enic->nic_cfg_chk ? CMD_NIC_CFG_CHK : CMD_NIC_CFG;
234 return vnic_dev_cmd(enic->vdev, cmd, &a0, &a1, wait);
235 }
236
enic_set_rss_key(struct enic * enic,dma_addr_t key_pa,uint64_t len)237 int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, uint64_t len)
238 {
239 uint64_t a0 = (uint64_t)key_pa, a1 = len;
240 int wait = 1000;
241
242 return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
243 }
244
enic_set_rss_cpu(struct enic * enic,dma_addr_t cpu_pa,uint64_t len)245 int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, uint64_t len)
246 {
247 uint64_t a0 = (uint64_t)cpu_pa, a1 = len;
248 int wait = 1000;
249
250 return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
251 }
252
enic_free_vnic_resources(struct enic * enic)253 void enic_free_vnic_resources(struct enic *enic)
254 {
255 unsigned int i;
256
257 for (i = 0; i < enic->wq_count; i++)
258 vnic_wq_free(&enic->wq[i]);
259 for (i = 0; i < enic_vnic_rq_count(enic); i++)
260 if (enic->rq[i].in_use)
261 vnic_rq_free(&enic->rq[i]);
262 for (i = 0; i < enic->cq_count; i++)
263 vnic_cq_free(&enic->cq[i]);
264 for (i = 0; i < enic->intr_count; i++)
265 vnic_intr_free(&enic->intr[i]);
266 }
267
enic_get_res_counts(struct enic * enic)268 void enic_get_res_counts(struct enic *enic)
269 {
270 enic->conf_wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
271 enic->conf_rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
272 enic->conf_cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
273 enic->conf_intr_count = vnic_dev_get_res_count(enic->vdev,
274 RES_TYPE_INTR_CTRL);
275
276 dev_info(enic_get_dev(enic),
277 "vNIC resources avail: wq %d rq %d cq %d intr %d\n",
278 enic->conf_wq_count, enic->conf_rq_count,
279 enic->conf_cq_count, enic->conf_intr_count);
280 }
281