1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_I210_H_ 6 #define _E1000_I210_H_ 7 8 bool e1000_get_flash_presence_i210(struct e1000_hw *hw); 9 s32 e1000_update_flash_i210(struct e1000_hw *hw); 10 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw); 11 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw); 12 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, 13 u16 words, u16 *data); 14 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, 15 u16 words, u16 *data); 16 s32 e1000_read_invm_version(struct e1000_hw *hw, 17 struct e1000_fw_version *invm_ver); 18 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask); 19 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask); 20 s32 e1000_init_hw_i210(struct e1000_hw *hw); 21 22 #define E1000_STM_OPCODE 0xDB00 23 #define E1000_EEPROM_FLASH_SIZE_WORD 0x11 24 25 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \ 26 (u8)((invm_dword) & 0x7) 27 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \ 28 (u8)(((invm_dword) & 0x0000FE00) >> 9) 29 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \ 30 (u16)(((invm_dword) & 0xFFFF0000) >> 16) 31 32 enum E1000_INVM_STRUCTURE_TYPE { 33 E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00, 34 E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01, 35 E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02, 36 E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03, 37 E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04, 38 E1000_INVM_INVALIDATED_STRUCTURE = 0x0F, 39 }; 40 41 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 42 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 43 #define E1000_INVM_ULT_BYTES_SIZE 8 44 #define E1000_INVM_RECORD_SIZE_IN_BYTES 4 45 #define E1000_INVM_VER_FIELD_ONE 0x1FF8 46 #define E1000_INVM_VER_FIELD_TWO 0x7FE000 47 #define E1000_INVM_IMGTYPE_FIELD 0x1F800000 48 49 #define E1000_INVM_MAJOR_MASK 0x3F0 50 #define E1000_INVM_MINOR_MASK 0xF 51 #define E1000_INVM_MAJOR_SHIFT 4 52 53 #define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \ 54 (ID_LED_DEF1_DEF2 << 4) | \ 55 (ID_LED_OFF1_OFF2)) 56 #define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \ 57 (ID_LED_DEF1_DEF2 << 4) | \ 58 (ID_LED_OFF1_ON2)) 59 60 /* NVM offset defaults for I211 devices */ 61 #define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243 62 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1 63 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 64 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C 65 66 /* PLL Defines */ 67 #define E1000_PCI_PMCSR 0x44 68 #define E1000_PCI_PMCSR_D3 0x03 69 #define E1000_MAX_PLL_TRIES 5 70 #define E1000_PHY_PLL_UNCONF 0xFF 71 #define E1000_PHY_PLL_FREQ_PAGE 0xFC0000 72 #define E1000_PHY_PLL_FREQ_REG 0x000E 73 #define E1000_INVM_DEFAULT_AL 0x202F 74 #define E1000_INVM_AUTOLOAD 0x0A 75 #define E1000_INVM_PLL_WO_VAL 0x0010 76 77 #endif 78