1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_80003ES2LAN_H_ 6 #define _E1000_80003ES2LAN_H_ 7 8 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 9 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 10 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 11 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 12 13 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 14 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 15 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 16 17 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 18 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 19 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 20 21 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 22 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 23 24 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 25 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 26 27 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 28 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 29 30 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 31 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 32 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 33 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 34 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 35 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 36 37 /* PHY Specific Control Register 2 (Page 0, Register 26) */ 38 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 39 40 /* MAC Specific Control Register (Page 2, Register 21) */ 41 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 42 #define GG82563_MSCR_TX_CLK_MASK 0x0007 43 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 44 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 45 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 46 47 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 48 49 /* DSP Distance Register (Page 5, Register 26) 50 * 0 = <50M 51 * 1 = 50-80M 52 * 2 = 80-100M 53 * 3 = 110-140M 54 * 4 = >140M 55 */ 56 #define GG82563_DSPD_CABLE_LENGTH 0x0007 57 58 /* Kumeran Mode Control Register (Page 193, Register 16) */ 59 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 60 61 /* Max number of times Kumeran read/write should be validated */ 62 #define GG82563_MAX_KMRN_RETRY 0x5 63 64 /* Power Management Control Register (Page 193, Register 20) */ 65 /* 1=Enable SERDES Electrical Idle */ 66 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 67 68 /* In-Band Control Register (Page 194, Register 18) */ 69 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 70 71 #endif 72