1 /* $FreeBSD$ */
2 /*-
3 * Copyright (c) 2014 Hans Petter Selasky <[email protected]>
4 * All rights reserved.
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /*
33 * This file contains the driver for the SAF1761 series USB OTG
34 * controller.
35 *
36 * Datasheet is available from:
37 * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
38 */
39
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
42 #else
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/bus.h>
51 #include <sys/module.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
56 #include <sys/sx.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
60 #include <sys/priv.h>
61 #include <sys/libkern.h>
62
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
65
66 #define USB_DEBUG_VAR saf1761_otg_debug
67
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
76
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #endif /* USB_GLOBAL_INCLUDE_FILE */
80
81 #include <dev/usb/controller/saf1761_otg.h>
82 #include <dev/usb/controller/saf1761_otg_reg.h>
83
84 #define SAF1761_OTG_BUS2SC(bus) \
85 ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
86 ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
87
88 #define SAF1761_OTG_PC2UDEV(pc) \
89 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
90
91 #define SAF1761_DCINTERRUPT_THREAD_IRQ \
92 (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST | \
93 SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
94
95 #ifdef USB_DEBUG
96 static int saf1761_otg_debug = 0;
97 static int saf1761_otg_forcefs = 0;
98
99 static
100 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
101 "USB SAF1761 DCI");
102
103 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
104 &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
105 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RWTUN,
106 &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
107 #endif
108
109 #define SAF1761_OTG_INTR_ENDPT 1
110
111 /* prototypes */
112
113 static const struct usb_bus_methods saf1761_otg_bus_methods;
114 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
115 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
116 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods;
117
118 static saf1761_otg_cmd_t saf1761_host_setup_tx;
119 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
120 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
121 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
122 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
123 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
124 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
125 static saf1761_otg_cmd_t saf1761_device_setup_rx;
126 static saf1761_otg_cmd_t saf1761_device_data_rx;
127 static saf1761_otg_cmd_t saf1761_device_data_tx;
128 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
129 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
130 static void saf1761_otg_do_poll(struct usb_bus *);
131 static void saf1761_otg_standard_done(struct usb_xfer *);
132 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
133 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
134 static void saf1761_otg_enable_psof(struct saf1761_otg_softc *, uint8_t);
135
136 /*
137 * Here is a list of what the SAF1761 chip can support. The main
138 * limitation is that the sum of the buffer sizes must be less than
139 * 8192 bytes.
140 */
141 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
142 [0] = {
143 .max_in_frame_size = 64,
144 .max_out_frame_size = 64,
145 .is_simplex = 0,
146 .support_control = 1,
147 },
148 [1] = {
149 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
150 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
151 .is_simplex = 0,
152 .support_interrupt = 1,
153 .support_bulk = 1,
154 .support_isochronous = 1,
155 .support_in = 1,
156 .support_out = 1,
157 },
158 };
159
160 static void
saf1761_otg_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)161 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
162 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
163 {
164 if (ep_addr == 0) {
165 *ppf = saf1761_otg_ep_profile + 0;
166 } else if (ep_addr < 8) {
167 *ppf = saf1761_otg_ep_profile + 1;
168 } else {
169 *ppf = NULL;
170 }
171 }
172
173 static void
saf1761_otg_pull_up(struct saf1761_otg_softc * sc)174 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
175 {
176 /* activate pullup on D+, if possible */
177
178 if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
179 DPRINTF("\n");
180
181 sc->sc_flags.d_pulled_up = 1;
182 }
183 }
184
185 static void
saf1761_otg_pull_down(struct saf1761_otg_softc * sc)186 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
187 {
188 /* release pullup on D+, if possible */
189
190 if (sc->sc_flags.d_pulled_up) {
191 DPRINTF("\n");
192
193 sc->sc_flags.d_pulled_up = 0;
194 }
195 }
196
197 static void
saf1761_otg_wakeup_peer(struct saf1761_otg_softc * sc)198 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
199 {
200 uint16_t temp;
201
202 if (!(sc->sc_flags.status_suspend))
203 return;
204
205 DPRINTFN(5, "\n");
206
207 temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
208 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
209 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
210
211 /* Wait 8ms for remote wakeup to complete. */
212 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
213 }
214
215 static uint8_t
saf1761_host_channel_alloc(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)216 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
217 {
218 uint32_t map;
219 int x;
220
221 if (td->channel < SOTG_HOST_CHANNEL_MAX)
222 return (0);
223
224 /* check if device is suspended */
225 if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
226 return (1); /* busy - cannot transfer data */
227
228 switch (td->ep_type) {
229 case UE_INTERRUPT:
230 map = ~(sc->sc_host_intr_map |
231 sc->sc_host_intr_busy_map[0] |
232 sc->sc_host_intr_busy_map[1]);
233 /* find first set bit */
234 x = ffs(map) - 1;
235 if (x < 0 || x > 31)
236 break;
237 sc->sc_host_intr_map |= (1U << x);
238 td->channel = 32 + x;
239 return (0);
240 case UE_ISOCHRONOUS:
241 map = ~(sc->sc_host_isoc_map |
242 sc->sc_host_isoc_busy_map[0] |
243 sc->sc_host_isoc_busy_map[1]);
244 /* find first set bit */
245 x = ffs(map) - 1;
246 if (x < 0 || x > 31)
247 break;
248 sc->sc_host_isoc_map |= (1U << x);
249 td->channel = x;
250 return (0);
251 default:
252 map = ~(sc->sc_host_async_map |
253 sc->sc_host_async_busy_map[0] |
254 sc->sc_host_async_busy_map[1]);
255 /* find first set bit */
256 x = ffs(map) - 1;
257 if (x < 0 || x > 31)
258 break;
259 sc->sc_host_async_map |= (1U << x);
260 td->channel = 64 + x;
261 return (0);
262 }
263 return (1);
264 }
265
266 static void
saf1761_host_channel_free(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)267 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
268 {
269 uint32_t x;
270
271 if (td->channel >= SOTG_HOST_CHANNEL_MAX)
272 return;
273
274 switch (td->ep_type) {
275 case UE_INTERRUPT:
276 x = td->channel - 32;
277 td->channel = SOTG_HOST_CHANNEL_MAX;
278 sc->sc_host_intr_map &= ~(1U << x);
279 sc->sc_host_intr_suspend_map &= ~(1U << x);
280 sc->sc_host_intr_busy_map[0] |= (1U << x);
281 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
282 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
283 break;
284 case UE_ISOCHRONOUS:
285 x = td->channel;
286 td->channel = SOTG_HOST_CHANNEL_MAX;
287 sc->sc_host_isoc_map &= ~(1U << x);
288 sc->sc_host_isoc_suspend_map &= ~(1U << x);
289 sc->sc_host_isoc_busy_map[0] |= (1U << x);
290 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
291 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
292 break;
293 default:
294 x = td->channel - 64;
295 td->channel = SOTG_HOST_CHANNEL_MAX;
296 sc->sc_host_async_map &= ~(1U << x);
297 sc->sc_host_async_suspend_map &= ~(1U << x);
298 sc->sc_host_async_busy_map[0] |= (1U << x);
299 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
300 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
301 break;
302 }
303 saf1761_otg_enable_psof(sc, 1);
304 }
305
306 static uint32_t
saf1761_peek_host_status_le_4(struct saf1761_otg_softc * sc,uint32_t offset)307 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
308 {
309 uint32_t x = 0;
310 while (1) {
311 uint32_t retval;
312
313 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
314 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
315 retval = SAF1761_READ_LE_4(sc, offset);
316 if (retval != 0)
317 return (retval);
318 if (++x == 8) {
319 DPRINTF("STAUS is zero at offset 0x%x\n", offset);
320 break;
321 }
322 }
323 return (0);
324 }
325
326 static void
saf1761_read_host_memory(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)327 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
328 struct saf1761_otg_td *td, uint32_t len)
329 {
330 struct usb_page_search buf_res;
331 uint32_t offset;
332 uint32_t count;
333
334 if (len == 0)
335 return;
336
337 offset = SOTG_DATA_ADDR(td->channel);
338 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
339 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
340
341 /* optimised read first */
342 while (len > 0) {
343 usbd_get_page(td->pc, td->offset, &buf_res);
344
345 /* get correct length */
346 if (buf_res.length > len)
347 buf_res.length = len;
348
349 /* check buffer alignment */
350 if (((uintptr_t)buf_res.buffer) & 3)
351 break;
352
353 count = buf_res.length & ~3;
354 if (count == 0)
355 break;
356
357 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
358 offset, buf_res.buffer, count / 4);
359
360 len -= count;
361 offset += count;
362
363 /* update remainder and offset */
364 td->remainder -= count;
365 td->offset += count;
366 }
367
368 if (len > 0) {
369 /* use bounce buffer */
370 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
371 offset, sc->sc_bounce_buffer, (len + 3) / 4);
372 usbd_copy_in(td->pc, td->offset,
373 sc->sc_bounce_buffer, len);
374
375 /* update remainder and offset */
376 td->remainder -= len;
377 td->offset += len;
378 }
379 }
380
381 static void
saf1761_write_host_memory(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)382 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
383 struct saf1761_otg_td *td, uint32_t len)
384 {
385 struct usb_page_search buf_res;
386 uint32_t offset;
387 uint32_t count;
388
389 if (len == 0)
390 return;
391
392 offset = SOTG_DATA_ADDR(td->channel);
393
394 /* optimised write first */
395 while (len > 0) {
396 usbd_get_page(td->pc, td->offset, &buf_res);
397
398 /* get correct length */
399 if (buf_res.length > len)
400 buf_res.length = len;
401
402 /* check buffer alignment */
403 if (((uintptr_t)buf_res.buffer) & 3)
404 break;
405
406 count = buf_res.length & ~3;
407 if (count == 0)
408 break;
409
410 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
411 offset, buf_res.buffer, count / 4);
412
413 len -= count;
414 offset += count;
415
416 /* update remainder and offset */
417 td->remainder -= count;
418 td->offset += count;
419 }
420 if (len > 0) {
421 /* use bounce buffer */
422 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
423 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
424 offset, sc->sc_bounce_buffer, (len + 3) / 4);
425
426 /* update remainder and offset */
427 td->remainder -= len;
428 td->offset += len;
429 }
430 }
431
432 static uint8_t
saf1761_host_setup_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)433 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
434 {
435 uint32_t pdt_addr;
436 uint32_t status;
437 uint32_t count;
438 uint32_t temp;
439
440 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
441 pdt_addr = SOTG_PTD(td->channel);
442
443 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
444
445 DPRINTFN(5, "STATUS=0x%08x\n", status);
446
447 if (status & SOTG_PTD_DW3_ACTIVE) {
448 goto busy;
449 } else if (status & SOTG_PTD_DW3_HALTED) {
450 td->error_any = 1;
451 }
452 goto complete;
453 }
454 if (saf1761_host_channel_alloc(sc, td))
455 goto busy;
456
457 count = 8;
458
459 if (count != td->remainder) {
460 td->error_any = 1;
461 goto complete;
462 }
463
464 saf1761_write_host_memory(sc, td, count);
465
466 pdt_addr = SOTG_PTD(td->channel);
467
468 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
469 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
470 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
471 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
472
473 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
474 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
475
476 temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
477 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
478
479 temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
480 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
481
482 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
483 (td->max_packet_size << 18) /* wMaxPacketSize */ |
484 (count << 3) /* transfer count */ |
485 SOTG_PTD_DW0_VALID;
486 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
487
488 /* activate PTD */
489 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
490 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
491
492 td->toggle = 1;
493 busy:
494 return (1); /* busy */
495 complete:
496 saf1761_host_channel_free(sc, td);
497 return (0); /* complete */
498 }
499
500 static uint8_t
saf1761_host_bulk_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)501 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
502 {
503 uint32_t pdt_addr;
504 uint32_t temp;
505
506 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
507 uint32_t status;
508 uint32_t count;
509 uint8_t got_short;
510
511 pdt_addr = SOTG_PTD(td->channel);
512
513 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
514
515 DPRINTFN(5, "STATUS=0x%08x\n", status);
516
517 if (status & SOTG_PTD_DW3_ACTIVE) {
518 temp = saf1761_peek_host_status_le_4(sc,
519 pdt_addr + SOTG_PTD_DW0);
520 if (temp & SOTG_PTD_DW0_VALID) {
521 goto busy;
522 } else {
523 status = saf1761_peek_host_status_le_4(sc,
524 pdt_addr + SOTG_PTD_DW3);
525
526 /* check if still active */
527 if (status & SOTG_PTD_DW3_ACTIVE) {
528 saf1761_host_channel_free(sc, td);
529 goto retry;
530 } else if (status & SOTG_PTD_DW3_HALTED) {
531 if (!(status & SOTG_PTD_DW3_ERRORS))
532 td->error_stall = 1;
533 td->error_any = 1;
534 goto complete;
535 }
536 }
537 } else if (status & SOTG_PTD_DW3_HALTED) {
538 if (!(status & SOTG_PTD_DW3_ERRORS))
539 td->error_stall = 1;
540 td->error_any = 1;
541 goto complete;
542 }
543 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
544 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
545 else
546 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
547 got_short = 0;
548
549 /* verify the packet byte count */
550 if (count != td->max_packet_size) {
551 if (count < td->max_packet_size) {
552 /* we have a short packet */
553 td->short_pkt = 1;
554 got_short = 1;
555 } else {
556 /* invalid USB packet */
557 td->error_any = 1;
558 goto complete;
559 }
560 }
561 td->toggle ^= 1;
562
563 /* verify the packet byte count */
564 if (count > td->remainder) {
565 /* invalid USB packet */
566 td->error_any = 1;
567 goto complete;
568 }
569
570 saf1761_read_host_memory(sc, td, count);
571
572 /* check if we are complete */
573 if ((td->remainder == 0) || got_short) {
574 if (td->short_pkt)
575 goto complete;
576 /* else need to receive a zero length packet */
577 }
578 saf1761_host_channel_free(sc, td);
579 }
580 retry:
581 if (saf1761_host_channel_alloc(sc, td))
582 goto busy;
583
584 /* set toggle, if any */
585 if (td->set_toggle) {
586 td->set_toggle = 0;
587 td->toggle = 1;
588 }
589
590 /* receive one more packet */
591
592 pdt_addr = SOTG_PTD(td->channel);
593
594 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
595 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
596 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
597 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
598
599 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
600 SOTG_PTD_DW3_CERR_2;
601 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
602
603 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
604 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
605
606 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
607 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
608
609 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
610 (td->max_packet_size << 18) /* wMaxPacketSize */ |
611 (td->max_packet_size << 3) /* transfer count */ |
612 SOTG_PTD_DW0_VALID;
613 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
614
615 /* activate PTD */
616 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
617 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
618 busy:
619 return (1); /* busy */
620 complete:
621 saf1761_host_channel_free(sc, td);
622 return (0); /* complete */
623 }
624
625 static uint8_t
saf1761_host_bulk_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)626 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
627 {
628 uint32_t pdt_addr;
629 uint32_t temp;
630 uint32_t count;
631
632 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
633 uint32_t status;
634
635 pdt_addr = SOTG_PTD(td->channel);
636
637 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
638
639 DPRINTFN(5, "STATUS=0x%08x\n", status);
640
641 if (status & SOTG_PTD_DW3_ACTIVE) {
642 goto busy;
643 } else if (status & SOTG_PTD_DW3_HALTED) {
644 if (!(status & SOTG_PTD_DW3_ERRORS))
645 td->error_stall = 1;
646 td->error_any = 1;
647 goto complete;
648 }
649 /* check remainder */
650 if (td->remainder == 0) {
651 if (td->short_pkt)
652 goto complete;
653 /* else we need to transmit a short packet */
654 }
655 saf1761_host_channel_free(sc, td);
656 }
657 if (saf1761_host_channel_alloc(sc, td))
658 goto busy;
659
660 count = td->max_packet_size;
661 if (td->remainder < count) {
662 /* we have a short packet */
663 td->short_pkt = 1;
664 count = td->remainder;
665 }
666
667 saf1761_write_host_memory(sc, td, count);
668
669 /* set toggle, if any */
670 if (td->set_toggle) {
671 td->set_toggle = 0;
672 td->toggle = 1;
673 }
674
675 /* send one more packet */
676
677 pdt_addr = SOTG_PTD(td->channel);
678
679 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
680 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
681 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
682 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
683
684 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
685 SOTG_PTD_DW3_CERR_2;
686 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
687
688 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
689 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
690
691 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
692 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
693
694 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
695 (td->max_packet_size << 18) /* wMaxPacketSize */ |
696 (count << 3) /* transfer count */ |
697 SOTG_PTD_DW0_VALID;
698 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
699
700 /* activate PTD */
701 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
702 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
703
704 td->toggle ^= 1;
705 busy:
706 return (1); /* busy */
707 complete:
708 saf1761_host_channel_free(sc, td);
709 return (0); /* complete */
710 }
711
712 static uint8_t
saf1761_host_intr_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)713 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
714 {
715 uint32_t pdt_addr;
716 uint32_t temp;
717
718 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
719 uint32_t status;
720 uint32_t count;
721 uint8_t got_short;
722
723 pdt_addr = SOTG_PTD(td->channel);
724
725 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
726
727 DPRINTFN(5, "STATUS=0x%08x\n", status);
728
729 if (status & SOTG_PTD_DW3_ACTIVE) {
730 goto busy;
731 } else if (status & SOTG_PTD_DW3_HALTED) {
732 if (!(status & SOTG_PTD_DW3_ERRORS))
733 td->error_stall = 1;
734 td->error_any = 1;
735 goto complete;
736 }
737 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
738 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
739 else
740 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
741 got_short = 0;
742
743 /* verify the packet byte count */
744 if (count != td->max_packet_size) {
745 if (count < td->max_packet_size) {
746 /* we have a short packet */
747 td->short_pkt = 1;
748 got_short = 1;
749 } else {
750 /* invalid USB packet */
751 td->error_any = 1;
752 goto complete;
753 }
754 }
755 td->toggle ^= 1;
756
757 /* verify the packet byte count */
758 if (count > td->remainder) {
759 /* invalid USB packet */
760 td->error_any = 1;
761 goto complete;
762 }
763
764 saf1761_read_host_memory(sc, td, count);
765
766 /* check if we are complete */
767 if ((td->remainder == 0) || got_short) {
768 if (td->short_pkt)
769 goto complete;
770 /* else need to receive a zero length packet */
771 }
772 saf1761_host_channel_free(sc, td);
773 }
774 if (saf1761_host_channel_alloc(sc, td))
775 goto busy;
776
777 /* set toggle, if any */
778 if (td->set_toggle) {
779 td->set_toggle = 0;
780 td->toggle = 1;
781 }
782
783 /* receive one more packet */
784
785 pdt_addr = SOTG_PTD(td->channel);
786
787 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
788 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
789
790 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
791 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
792 } else {
793 temp = 0;
794 }
795 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
796
797 temp = (1U << td->uframe); /* start mask or start split */
798 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
799
800 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
801 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
802
803 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
804 (td->interval & 0xF8);
805 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
806
807 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
808 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
809
810 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
811 (td->max_packet_size << 18) /* wMaxPacketSize */ |
812 (td->max_packet_size << 3) /* transfer count */ |
813 SOTG_PTD_DW0_VALID;
814 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
815
816 /* activate PTD */
817 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
818 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
819 busy:
820 return (1); /* busy */
821 complete:
822 saf1761_host_channel_free(sc, td);
823 return (0); /* complete */
824 }
825
826 static uint8_t
saf1761_host_intr_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)827 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
828 {
829 uint32_t pdt_addr;
830 uint32_t temp;
831 uint32_t count;
832
833 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
834 uint32_t status;
835
836 pdt_addr = SOTG_PTD(td->channel);
837
838 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
839
840 DPRINTFN(5, "STATUS=0x%08x\n", status);
841
842 if (status & SOTG_PTD_DW3_ACTIVE) {
843 goto busy;
844 } else if (status & SOTG_PTD_DW3_HALTED) {
845 if (!(status & SOTG_PTD_DW3_ERRORS))
846 td->error_stall = 1;
847 td->error_any = 1;
848 goto complete;
849 }
850
851 /* check remainder */
852 if (td->remainder == 0) {
853 if (td->short_pkt)
854 goto complete;
855 /* else we need to transmit a short packet */
856 }
857 saf1761_host_channel_free(sc, td);
858 }
859 if (saf1761_host_channel_alloc(sc, td))
860 goto busy;
861
862 count = td->max_packet_size;
863 if (td->remainder < count) {
864 /* we have a short packet */
865 td->short_pkt = 1;
866 count = td->remainder;
867 }
868
869 saf1761_write_host_memory(sc, td, count);
870
871 /* set toggle, if any */
872 if (td->set_toggle) {
873 td->set_toggle = 0;
874 td->toggle = 1;
875 }
876
877 /* send one more packet */
878
879 pdt_addr = SOTG_PTD(td->channel);
880
881 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
882 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
883
884 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
885 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
886 } else {
887 temp = 0;
888 }
889 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
890
891 temp = (1U << td->uframe); /* start mask or start split */
892 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
893
894 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
895 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
896
897 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
898 (td->interval & 0xF8);
899 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
900
901 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
902 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
903
904 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
905 (td->max_packet_size << 18) /* wMaxPacketSize */ |
906 (count << 3) /* transfer count */ |
907 SOTG_PTD_DW0_VALID;
908 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
909
910 /* activate PTD */
911 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
912 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
913
914 td->toggle ^= 1;
915 busy:
916 return (1); /* busy */
917 complete:
918 saf1761_host_channel_free(sc, td);
919 return (0); /* complete */
920 }
921
922 static uint8_t
saf1761_host_isoc_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)923 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
924 {
925 uint32_t pdt_addr;
926 uint32_t temp;
927
928 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
929 uint32_t status;
930 uint32_t count;
931
932 pdt_addr = SOTG_PTD(td->channel);
933
934 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
935
936 DPRINTFN(5, "STATUS=0x%08x\n", status);
937
938 if (status & SOTG_PTD_DW3_ACTIVE) {
939 goto busy;
940 } else if (status & SOTG_PTD_DW3_HALTED) {
941 goto complete;
942 }
943 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
944 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
945 else
946 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
947
948 /* verify the packet byte count */
949 if (count != td->max_packet_size) {
950 if (count < td->max_packet_size) {
951 /* we have a short packet */
952 td->short_pkt = 1;
953 } else {
954 /* invalid USB packet */
955 td->error_any = 1;
956 goto complete;
957 }
958 }
959
960 /* verify the packet byte count */
961 if (count > td->remainder) {
962 /* invalid USB packet */
963 td->error_any = 1;
964 goto complete;
965 }
966
967 saf1761_read_host_memory(sc, td, count);
968 goto complete;
969 }
970
971 if (saf1761_host_channel_alloc(sc, td))
972 goto busy;
973
974 /* receive one more packet */
975
976 pdt_addr = SOTG_PTD(td->channel);
977
978 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
979 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
980
981 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
982 temp = (0xFC << (td->uframe & 7)) & 0xFF; /* complete split */
983 } else {
984 temp = 0;
985 }
986 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
987
988 temp = (1U << (td->uframe & 7)); /* start mask or start split */
989 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
990
991 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
992 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
993
994 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
995 (td->uframe & 0xF8);
996 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
997
998 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
999 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1000
1001 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1002 (td->max_packet_size << 18) /* wMaxPacketSize */ |
1003 (td->max_packet_size << 3) /* transfer count */ |
1004 SOTG_PTD_DW0_VALID;
1005 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1006
1007 /* activate PTD */
1008 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1009 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1010 busy:
1011 return (1); /* busy */
1012 complete:
1013 saf1761_host_channel_free(sc, td);
1014 return (0); /* complete */
1015 }
1016
1017 static uint8_t
saf1761_host_isoc_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1018 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1019 {
1020 uint32_t pdt_addr;
1021 uint32_t temp;
1022 uint32_t count;
1023
1024 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
1025 uint32_t status;
1026
1027 pdt_addr = SOTG_PTD(td->channel);
1028
1029 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
1030
1031 DPRINTFN(5, "STATUS=0x%08x\n", status);
1032
1033 if (status & SOTG_PTD_DW3_ACTIVE) {
1034 goto busy;
1035 } else if (status & SOTG_PTD_DW3_HALTED) {
1036 goto complete;
1037 }
1038 goto complete;
1039 }
1040 if (saf1761_host_channel_alloc(sc, td))
1041 goto busy;
1042
1043 count = td->max_packet_size;
1044 if (td->remainder < count) {
1045 /* we have a short packet */
1046 td->short_pkt = 1;
1047 count = td->remainder;
1048 }
1049
1050 saf1761_write_host_memory(sc, td, count);
1051
1052 /* send one more packet */
1053
1054 pdt_addr = SOTG_PTD(td->channel);
1055
1056 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
1057 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
1058 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
1059
1060 temp = (1U << (td->uframe & 7)); /* start mask or start split */
1061 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
1062
1063 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
1064 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
1065
1066 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
1067 (td->uframe & 0xF8);
1068 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
1069
1070 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
1071 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1072
1073 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1074 (count << 18) /* wMaxPacketSize */ |
1075 (count << 3) /* transfer count */ |
1076 SOTG_PTD_DW0_VALID;
1077 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1078
1079 /* activate PTD */
1080 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1081 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1082 busy:
1083 return (1); /* busy */
1084 complete:
1085 saf1761_host_channel_free(sc, td);
1086 return (0); /* complete */
1087 }
1088
1089 static void
saf1761_otg_set_address(struct saf1761_otg_softc * sc,uint8_t addr)1090 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
1091 {
1092 DPRINTFN(5, "addr=%d\n", addr);
1093
1094 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
1095 }
1096
1097 static void
saf1761_read_device_fifo(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)1098 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
1099 struct saf1761_otg_td *td, uint32_t len)
1100 {
1101 struct usb_page_search buf_res;
1102 uint32_t count;
1103
1104 /* optimised read first */
1105 while (len > 0) {
1106 usbd_get_page(td->pc, td->offset, &buf_res);
1107
1108 /* get correct length */
1109 if (buf_res.length > len)
1110 buf_res.length = len;
1111
1112 /* check buffer alignment */
1113 if (((uintptr_t)buf_res.buffer) & 3)
1114 break;
1115
1116 count = buf_res.length & ~3;
1117 if (count == 0)
1118 break;
1119
1120 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1121 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1122
1123 len -= count;
1124
1125 /* update remainder and offset */
1126 td->remainder -= count;
1127 td->offset += count;
1128 }
1129
1130 if (len > 0) {
1131 /* use bounce buffer */
1132 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1133 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1134 usbd_copy_in(td->pc, td->offset,
1135 sc->sc_bounce_buffer, len);
1136
1137 /* update remainder and offset */
1138 td->remainder -= len;
1139 td->offset += len;
1140 }
1141 }
1142
1143 static void
saf1761_write_device_fifo(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)1144 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
1145 struct saf1761_otg_td *td, uint32_t len)
1146 {
1147 struct usb_page_search buf_res;
1148 uint32_t count;
1149
1150 /* optimised write first */
1151 while (len > 0) {
1152 usbd_get_page(td->pc, td->offset, &buf_res);
1153
1154 /* get correct length */
1155 if (buf_res.length > len)
1156 buf_res.length = len;
1157
1158 /* check buffer alignment */
1159 if (((uintptr_t)buf_res.buffer) & 3)
1160 break;
1161
1162 count = buf_res.length & ~3;
1163 if (count == 0)
1164 break;
1165
1166 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1167 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1168
1169 len -= count;
1170
1171 /* update remainder and offset */
1172 td->remainder -= count;
1173 td->offset += count;
1174 }
1175 if (len > 0) {
1176 /* use bounce buffer */
1177 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
1178 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1179 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1180
1181 /* update remainder and offset */
1182 td->remainder -= len;
1183 td->offset += len;
1184 }
1185 }
1186
1187 static uint8_t
saf1761_device_setup_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1188 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1189 {
1190 struct usb_device_request req;
1191 uint32_t count;
1192
1193 /* select the correct endpoint */
1194 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1195
1196 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1197
1198 /* check buffer status */
1199 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1200 goto busy;
1201
1202 /* get buffer length */
1203 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1204
1205 DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1206
1207 /* clear did stall */
1208 td->did_stall = 0;
1209
1210 /* clear stall */
1211 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1212
1213 /* verify data length */
1214 if (count != td->remainder) {
1215 DPRINTFN(0, "Invalid SETUP packet "
1216 "length, %d bytes\n", count);
1217 goto busy;
1218 }
1219 if (count != sizeof(req)) {
1220 DPRINTFN(0, "Unsupported SETUP packet "
1221 "length, %d bytes\n", count);
1222 goto busy;
1223 }
1224 /* receive data */
1225 saf1761_read_device_fifo(sc, td, sizeof(req));
1226
1227 /* extract SETUP packet again */
1228 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1229
1230 /* sneak peek the set address request */
1231 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1232 (req.bRequest == UR_SET_ADDRESS)) {
1233 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1234 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1235 } else {
1236 sc->sc_dv_addr = 0xFF;
1237 }
1238 return (0); /* complete */
1239
1240 busy:
1241 /* abort any ongoing transfer */
1242 if (!td->did_stall) {
1243 DPRINTFN(5, "stalling\n");
1244
1245 /* set stall */
1246 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1247
1248 td->did_stall = 1;
1249 }
1250 return (1); /* not complete */
1251 }
1252
1253 static uint8_t
saf1761_device_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1254 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1255 {
1256 uint32_t count;
1257 uint8_t got_short = 0;
1258
1259 if (td->ep_index == 0) {
1260 /* select the correct endpoint */
1261 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1262
1263 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1264
1265 /* check buffer status */
1266 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1267 if (td->remainder == 0) {
1268 /*
1269 * We are actually complete and have
1270 * received the next SETUP:
1271 */
1272 DPRINTFN(5, "faking complete\n");
1273 return (0); /* complete */
1274 }
1275 DPRINTFN(5, "SETUP packet while receiving data\n");
1276 /*
1277 * USB Host Aborted the transfer.
1278 */
1279 td->error_any = 1;
1280 return (0); /* complete */
1281 }
1282 }
1283 /* select the correct endpoint */
1284 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1285 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1286 SOTG_EP_INDEX_DIR_OUT);
1287
1288 /* enable data stage */
1289 if (td->set_toggle) {
1290 td->set_toggle = 0;
1291 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1292 }
1293
1294 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1295
1296 /* check buffer status */
1297 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1298 return (1); /* not complete */
1299
1300 /* get buffer length */
1301 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1302
1303 DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1304
1305 /* verify the packet byte count */
1306 if (count != td->max_packet_size) {
1307 if (count < td->max_packet_size) {
1308 /* we have a short packet */
1309 td->short_pkt = 1;
1310 got_short = 1;
1311 } else {
1312 /* invalid USB packet */
1313 td->error_any = 1;
1314 return (0); /* we are complete */
1315 }
1316 }
1317 /* verify the packet byte count */
1318 if (count > td->remainder) {
1319 /* invalid USB packet */
1320 td->error_any = 1;
1321 return (0); /* we are complete */
1322 }
1323 /* receive data */
1324 saf1761_read_device_fifo(sc, td, count);
1325
1326 /* check if we are complete */
1327 if ((td->remainder == 0) || got_short) {
1328 if (td->short_pkt) {
1329 /* we are complete */
1330 return (0);
1331 }
1332 /* else need to receive a zero length packet */
1333 }
1334 return (1); /* not complete */
1335 }
1336
1337 static uint8_t
saf1761_device_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1338 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1339 {
1340 uint32_t count;
1341
1342 if (td->ep_index == 0) {
1343 /* select the correct endpoint */
1344 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1345
1346 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1347
1348 /* check buffer status */
1349 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1350 DPRINTFN(5, "SETUP abort\n");
1351 /*
1352 * USB Host Aborted the transfer.
1353 */
1354 td->error_any = 1;
1355 return (0); /* complete */
1356 }
1357 }
1358 /* select the correct endpoint */
1359 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1360 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1361 SOTG_EP_INDEX_DIR_IN);
1362
1363 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1364
1365 /* check buffer status */
1366 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1367 return (1); /* not complete */
1368
1369 /* enable data stage */
1370 if (td->set_toggle) {
1371 td->set_toggle = 0;
1372 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1373 }
1374
1375 DPRINTFN(5, "rem=%u\n", td->remainder);
1376
1377 count = td->max_packet_size;
1378 if (td->remainder < count) {
1379 /* we have a short packet */
1380 td->short_pkt = 1;
1381 count = td->remainder;
1382 }
1383 /* transmit data */
1384 saf1761_write_device_fifo(sc, td, count);
1385
1386 if (td->ep_index == 0) {
1387 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1388 /* set end of packet */
1389 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1390 }
1391 } else {
1392 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1393 /* set end of packet */
1394 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1395 }
1396 }
1397
1398 /* check remainder */
1399 if (td->remainder == 0) {
1400 if (td->short_pkt) {
1401 return (0); /* complete */
1402 }
1403 /* else we need to transmit a short packet */
1404 }
1405 return (1); /* not complete */
1406 }
1407
1408 static uint8_t
saf1761_device_data_tx_sync(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1409 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1410 {
1411 uint32_t count;
1412
1413 if (td->ep_index == 0) {
1414 /* select the correct endpoint */
1415 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1416
1417 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1418
1419 /* check buffer status */
1420 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1421 DPRINTFN(5, "Faking complete\n");
1422 return (0); /* complete */
1423 }
1424 }
1425 /* select the correct endpoint */
1426 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1427 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1428 SOTG_EP_INDEX_DIR_IN);
1429
1430 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1431
1432 /* check buffer status */
1433 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1434 return (1); /* busy */
1435
1436 if (sc->sc_dv_addr != 0xFF) {
1437 /* write function address */
1438 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1439 }
1440 return (0); /* complete */
1441 }
1442
1443 static void
saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc * sc,struct usb_xfer * xfer)1444 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1445 {
1446 struct saf1761_otg_td *td;
1447 uint8_t toggle;
1448
1449 DPRINTFN(9, "\n");
1450
1451 td = xfer->td_transfer_cache;
1452 if (td == NULL)
1453 return;
1454
1455 while (1) {
1456 if ((td->func) (sc, td)) {
1457 /* operation in progress */
1458 break;
1459 }
1460 if (((void *)td) == xfer->td_transfer_last) {
1461 goto done;
1462 }
1463 if (td->error_any) {
1464 goto done;
1465 } else if (td->remainder > 0) {
1466 /*
1467 * We had a short transfer. If there is no alternate
1468 * next, stop processing !
1469 */
1470 if (!td->alt_next) {
1471 goto done;
1472 }
1473 }
1474 /*
1475 * Fetch the next transfer descriptor.
1476 */
1477 toggle = td->toggle;
1478 td = td->obj_next;
1479 td->toggle = toggle;
1480 xfer->td_transfer_cache = td;
1481 }
1482 return;
1483
1484 done:
1485 /* compute all actual lengths */
1486 xfer->td_transfer_cache = NULL;
1487 sc->sc_xfer_complete = 1;
1488 }
1489
1490 static uint8_t
saf1761_otg_xfer_do_complete(struct saf1761_otg_softc * sc,struct usb_xfer * xfer)1491 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1492 {
1493 struct saf1761_otg_td *td;
1494
1495 DPRINTFN(9, "\n");
1496
1497 td = xfer->td_transfer_cache;
1498 if (td == NULL) {
1499 /* compute all actual lengths */
1500 saf1761_otg_standard_done(xfer);
1501 return (1);
1502 }
1503 return (0);
1504 }
1505
1506 static void
saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc * sc)1507 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1508 {
1509 struct usb_xfer *xfer;
1510
1511 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1512 saf1761_otg_xfer_do_fifo(sc, xfer);
1513 }
1514
1515 static void
saf1761_otg_enable_psof(struct saf1761_otg_softc * sc,uint8_t on)1516 saf1761_otg_enable_psof(struct saf1761_otg_softc *sc, uint8_t on)
1517 {
1518 if (on) {
1519 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IEPSOF;
1520 } else {
1521 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IEPSOF;
1522 }
1523 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1524 }
1525
1526 static void
saf1761_otg_wait_suspend(struct saf1761_otg_softc * sc,uint8_t on)1527 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1528 {
1529 if (on) {
1530 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1531 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1532 } else {
1533 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1534 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1535 }
1536 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1537 }
1538
1539 static void
saf1761_otg_update_vbus(struct saf1761_otg_softc * sc)1540 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1541 {
1542 uint16_t status;
1543
1544 /* read fresh status */
1545 status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1546
1547 DPRINTFN(4, "STATUS=0x%04x\n", status);
1548
1549 if ((status & SOTG_STATUS_VBUS_VLD) &&
1550 (status & SOTG_STATUS_ID)) {
1551 /* VBUS present and device mode */
1552 if (!sc->sc_flags.status_vbus) {
1553 sc->sc_flags.status_vbus = 1;
1554
1555 /* complete root HUB interrupt endpoint */
1556 saf1761_otg_root_intr(sc);
1557 }
1558 } else {
1559 /* VBUS not-present or host mode */
1560 if (sc->sc_flags.status_vbus) {
1561 sc->sc_flags.status_vbus = 0;
1562 sc->sc_flags.status_bus_reset = 0;
1563 sc->sc_flags.status_suspend = 0;
1564 sc->sc_flags.change_suspend = 0;
1565 sc->sc_flags.change_connect = 1;
1566
1567 /* complete root HUB interrupt endpoint */
1568 saf1761_otg_root_intr(sc);
1569 }
1570 }
1571 }
1572
1573 static void
saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc * sc)1574 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1575 {
1576 struct usb_xfer *xfer;
1577 repeat:
1578 /* scan for completion events */
1579 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1580 if (saf1761_otg_xfer_do_complete(sc, xfer))
1581 goto repeat;
1582 }
1583 }
1584
1585 int
saf1761_otg_filter_interrupt(void * arg)1586 saf1761_otg_filter_interrupt(void *arg)
1587 {
1588 struct saf1761_otg_softc *sc = arg;
1589 int retval = FILTER_HANDLED;
1590 uint32_t hcstat;
1591 uint32_t status;
1592
1593 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1594
1595 hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1596 /* acknowledge all host controller interrupts */
1597 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1598
1599 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1600 /* acknowledge all device controller interrupts */
1601 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1602 status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1603
1604 (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1605 (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1606 (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1607
1608 DPRINTFN(9, "HCINTERRUPT=0x%08x DCINTERRUPT=0x%08x\n", hcstat, status);
1609
1610 if (status & SOTG_DCINTERRUPT_IEPSOF) {
1611 if ((sc->sc_host_async_busy_map[1] | sc->sc_host_async_busy_map[0] |
1612 sc->sc_host_intr_busy_map[1] | sc->sc_host_intr_busy_map[0] |
1613 sc->sc_host_isoc_busy_map[1] | sc->sc_host_isoc_busy_map[0]) != 0) {
1614 /* busy waiting is active */
1615 retval = FILTER_SCHEDULE_THREAD;
1616
1617 sc->sc_host_async_busy_map[1] = sc->sc_host_async_busy_map[0];
1618 sc->sc_host_async_busy_map[0] = 0;
1619
1620 sc->sc_host_intr_busy_map[1] = sc->sc_host_intr_busy_map[0];
1621 sc->sc_host_intr_busy_map[0] = 0;
1622
1623 sc->sc_host_isoc_busy_map[1] = sc->sc_host_isoc_busy_map[0];
1624 sc->sc_host_isoc_busy_map[0] = 0;
1625 } else {
1626 /* busy waiting is not active */
1627 saf1761_otg_enable_psof(sc, 0);
1628 }
1629 }
1630
1631 if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1632 retval = FILTER_SCHEDULE_THREAD;
1633
1634 /* poll FIFOs, if any */
1635 saf1761_otg_interrupt_poll_locked(sc);
1636
1637 if (sc->sc_xfer_complete != 0)
1638 retval = FILTER_SCHEDULE_THREAD;
1639
1640 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1641
1642 return (retval);
1643 }
1644
1645 void
saf1761_otg_interrupt(void * arg)1646 saf1761_otg_interrupt(void *arg)
1647 {
1648 struct saf1761_otg_softc *sc = arg;
1649 uint32_t status;
1650
1651 USB_BUS_LOCK(&sc->sc_bus);
1652 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1653
1654 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1655 SAF1761_DCINTERRUPT_THREAD_IRQ;
1656
1657 /* acknowledge all device controller interrupts */
1658 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1659
1660 DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1661 "FRINDEX=0x%08x\n", status,
1662 SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1663 SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1664
1665 /* update VBUS and ID bits, if any */
1666 if (status & SOTG_DCINTERRUPT_IEVBUS)
1667 saf1761_otg_update_vbus(sc);
1668
1669 if (status & SOTG_DCINTERRUPT_IEBRST) {
1670 /* unlock device */
1671 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1672 SOTG_UNLOCK_DEVICE_CODE);
1673
1674 /* Enable device address */
1675 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1676 SOTG_ADDRESS_ENABLE);
1677
1678 sc->sc_flags.status_bus_reset = 1;
1679 sc->sc_flags.status_suspend = 0;
1680 sc->sc_flags.change_suspend = 0;
1681 sc->sc_flags.change_connect = 1;
1682
1683 /* disable resume interrupt */
1684 saf1761_otg_wait_suspend(sc, 1);
1685 /* complete root HUB interrupt endpoint */
1686 saf1761_otg_root_intr(sc);
1687 }
1688 /*
1689 * If "RESUME" and "SUSPEND" is set at the same time we
1690 * interpret that like "RESUME". Resume is set when there is
1691 * at least 3 milliseconds of inactivity on the USB BUS:
1692 */
1693 if (status & SOTG_DCINTERRUPT_IERESM) {
1694 /* unlock device */
1695 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1696 SOTG_UNLOCK_DEVICE_CODE);
1697
1698 if (sc->sc_flags.status_suspend) {
1699 sc->sc_flags.status_suspend = 0;
1700 sc->sc_flags.change_suspend = 1;
1701 /* disable resume interrupt */
1702 saf1761_otg_wait_suspend(sc, 1);
1703 /* complete root HUB interrupt endpoint */
1704 saf1761_otg_root_intr(sc);
1705 }
1706 } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1707 if (!sc->sc_flags.status_suspend) {
1708 sc->sc_flags.status_suspend = 1;
1709 sc->sc_flags.change_suspend = 1;
1710 /* enable resume interrupt */
1711 saf1761_otg_wait_suspend(sc, 0);
1712 /* complete root HUB interrupt endpoint */
1713 saf1761_otg_root_intr(sc);
1714 }
1715 }
1716
1717 if (sc->sc_xfer_complete != 0) {
1718 sc->sc_xfer_complete = 0;
1719
1720 /* complete FIFOs, if any */
1721 saf1761_otg_interrupt_complete_locked(sc);
1722 }
1723 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1724 USB_BUS_UNLOCK(&sc->sc_bus);
1725 }
1726
1727 static void
saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp * temp)1728 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1729 {
1730 struct saf1761_otg_td *td;
1731
1732 /* get current Transfer Descriptor */
1733 td = temp->td_next;
1734 temp->td = td;
1735
1736 /* prepare for next TD */
1737 temp->td_next = td->obj_next;
1738
1739 /* fill out the Transfer Descriptor */
1740 td->func = temp->func;
1741 td->pc = temp->pc;
1742 td->offset = temp->offset;
1743 td->remainder = temp->len;
1744 td->error_any = 0;
1745 td->error_stall = 0;
1746 td->set_toggle = 0;
1747 td->did_stall = temp->did_stall;
1748 td->short_pkt = temp->short_pkt;
1749 td->alt_next = temp->setup_alt_next;
1750 td->channel = SOTG_HOST_CHANNEL_MAX;
1751 }
1752
1753 static void
saf1761_otg_setup_standard_chain(struct usb_xfer * xfer)1754 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1755 {
1756 struct saf1761_otg_std_temp temp;
1757 struct saf1761_otg_softc *sc;
1758 struct saf1761_otg_td *td;
1759 uint32_t x;
1760 uint8_t ep_no;
1761 uint8_t ep_type;
1762 uint8_t need_sync;
1763 uint8_t is_host;
1764 uint8_t uframe_start;
1765 uint8_t uframe_interval;
1766
1767 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1768 xfer->address, UE_GET_ADDR(xfer->endpointno),
1769 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1770
1771 temp.max_frame_size = xfer->max_frame_size;
1772
1773 td = xfer->td_start[0];
1774 xfer->td_transfer_first = td;
1775 xfer->td_transfer_cache = td;
1776
1777 /* setup temp */
1778
1779 temp.pc = NULL;
1780 temp.td = NULL;
1781 temp.td_next = xfer->td_start[0];
1782 temp.offset = 0;
1783 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1784 xfer->flags_int.isochronous_xfr;
1785 temp.did_stall = !xfer->flags_int.control_stall;
1786
1787 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1788
1789 sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1790 ep_no = (xfer->endpointno & UE_ADDR);
1791 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1792
1793 /* check if we should prepend a setup message */
1794
1795 if (xfer->flags_int.control_xfr) {
1796 if (xfer->flags_int.control_hdr) {
1797 if (is_host)
1798 temp.func = &saf1761_host_setup_tx;
1799 else
1800 temp.func = &saf1761_device_setup_rx;
1801
1802 temp.len = xfer->frlengths[0];
1803 temp.pc = xfer->frbuffers + 0;
1804 temp.short_pkt = temp.len ? 1 : 0;
1805 /* check for last frame */
1806 if (xfer->nframes == 1) {
1807 /* no STATUS stage yet, SETUP is last */
1808 if (xfer->flags_int.control_act)
1809 temp.setup_alt_next = 0;
1810 }
1811 saf1761_otg_setup_standard_chain_sub(&temp);
1812 }
1813 x = 1;
1814 } else {
1815 x = 0;
1816 }
1817
1818 uframe_start = 0;
1819 uframe_interval = 0;
1820
1821 if (x != xfer->nframes) {
1822 if (xfer->endpointno & UE_DIR_IN) {
1823 if (is_host) {
1824 if (ep_type == UE_INTERRUPT) {
1825 temp.func = &saf1761_host_intr_data_rx;
1826 } else if (ep_type == UE_ISOCHRONOUS) {
1827 temp.func = &saf1761_host_isoc_data_rx;
1828 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1829 (SOTG_FRINDEX_MASK & ~7);
1830 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1831 uframe_interval = 1U << xfer->fps_shift;
1832 else
1833 uframe_interval = 8U;
1834 } else {
1835 temp.func = &saf1761_host_bulk_data_rx;
1836 }
1837 need_sync = 0;
1838 } else {
1839 temp.func = &saf1761_device_data_tx;
1840 need_sync = 1;
1841 }
1842 } else {
1843 if (is_host) {
1844 if (ep_type == UE_INTERRUPT) {
1845 temp.func = &saf1761_host_intr_data_tx;
1846 } else if (ep_type == UE_ISOCHRONOUS) {
1847 temp.func = &saf1761_host_isoc_data_tx;
1848 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1849 (SOTG_FRINDEX_MASK & ~7);
1850 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1851 uframe_interval = 1U << xfer->fps_shift;
1852 else
1853 uframe_interval = 8U;
1854 } else {
1855 temp.func = &saf1761_host_bulk_data_tx;
1856 }
1857 need_sync = 0;
1858 } else {
1859 temp.func = &saf1761_device_data_rx;
1860 need_sync = 0;
1861 }
1862 }
1863
1864 /* setup "pc" pointer */
1865 temp.pc = xfer->frbuffers + x;
1866 } else {
1867 need_sync = 0;
1868 }
1869
1870 while (x != xfer->nframes) {
1871 /* DATA0 / DATA1 message */
1872
1873 temp.len = xfer->frlengths[x];
1874
1875 x++;
1876
1877 if (x == xfer->nframes) {
1878 if (xfer->flags_int.control_xfr) {
1879 if (xfer->flags_int.control_act) {
1880 temp.setup_alt_next = 0;
1881 }
1882 } else {
1883 temp.setup_alt_next = 0;
1884 }
1885 }
1886 if (temp.len == 0) {
1887 /* make sure that we send an USB packet */
1888
1889 temp.short_pkt = 0;
1890
1891 } else {
1892 /* regular data transfer */
1893
1894 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1895 }
1896
1897 saf1761_otg_setup_standard_chain_sub(&temp);
1898
1899 if (xfer->flags_int.isochronous_xfr) {
1900 temp.offset += temp.len;
1901
1902 /* stamp the starting point for this transaction */
1903 temp.td->uframe = uframe_start;
1904
1905 /* advance to next */
1906 uframe_start += uframe_interval;
1907 } else {
1908 /* get next Page Cache pointer */
1909 temp.pc = xfer->frbuffers + x;
1910 }
1911 }
1912
1913 /* check for control transfer */
1914 if (xfer->flags_int.control_xfr) {
1915 /* always setup a valid "pc" pointer for status and sync */
1916 temp.pc = xfer->frbuffers + 0;
1917 temp.len = 0;
1918 temp.short_pkt = 0;
1919 temp.setup_alt_next = 0;
1920
1921 /* check if we should append a status stage */
1922 if (!xfer->flags_int.control_act) {
1923 /*
1924 * Send a DATA1 message and invert the current
1925 * endpoint direction.
1926 */
1927 if (xfer->endpointno & UE_DIR_IN) {
1928 if (is_host) {
1929 temp.func = &saf1761_host_bulk_data_tx;
1930 need_sync = 0;
1931 } else {
1932 temp.func = &saf1761_device_data_rx;
1933 need_sync = 0;
1934 }
1935 } else {
1936 if (is_host) {
1937 temp.func = &saf1761_host_bulk_data_rx;
1938 need_sync = 0;
1939 } else {
1940 temp.func = &saf1761_device_data_tx;
1941 need_sync = 1;
1942 }
1943 }
1944 temp.len = 0;
1945 temp.short_pkt = 0;
1946
1947 saf1761_otg_setup_standard_chain_sub(&temp);
1948
1949 /* data toggle should be DATA1 */
1950 td = temp.td;
1951 td->set_toggle = 1;
1952
1953 if (need_sync) {
1954 /* we need a SYNC point after TX */
1955 temp.func = &saf1761_device_data_tx_sync;
1956 saf1761_otg_setup_standard_chain_sub(&temp);
1957 }
1958 }
1959 } else {
1960 if (need_sync) {
1961 temp.pc = xfer->frbuffers + 0;
1962 temp.len = 0;
1963 temp.short_pkt = 0;
1964 temp.setup_alt_next = 0;
1965
1966 /* we need a SYNC point after TX */
1967 temp.func = &saf1761_device_data_tx_sync;
1968 saf1761_otg_setup_standard_chain_sub(&temp);
1969 }
1970 }
1971
1972 /* must have at least one frame! */
1973 td = temp.td;
1974 xfer->td_transfer_last = td;
1975
1976 if (is_host) {
1977 /* get first again */
1978 td = xfer->td_transfer_first;
1979 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1980 }
1981 }
1982
1983 static void
saf1761_otg_timeout(void * arg)1984 saf1761_otg_timeout(void *arg)
1985 {
1986 struct usb_xfer *xfer = arg;
1987
1988 DPRINTF("xfer=%p\n", xfer);
1989
1990 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1991
1992 /* transfer is transferred */
1993 saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1994 }
1995
1996 static void
saf1761_otg_intr_set(struct usb_xfer * xfer,uint8_t set)1997 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1998 {
1999 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2000 uint8_t ep_no = (xfer->endpointno & UE_ADDR);
2001 uint32_t mask;
2002
2003 DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
2004
2005 if (ep_no == 0) {
2006 mask = SOTG_DCINTERRUPT_IEPRX(0) |
2007 SOTG_DCINTERRUPT_IEPTX(0) |
2008 SOTG_DCINTERRUPT_IEP0SETUP;
2009 } else if (xfer->endpointno & UE_DIR_IN) {
2010 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
2011 } else {
2012 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
2013 }
2014
2015 if (set)
2016 sc->sc_intr_enable |= mask;
2017 else
2018 sc->sc_intr_enable &= ~mask;
2019
2020 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2021 }
2022
2023 static void
saf1761_otg_start_standard_chain(struct usb_xfer * xfer)2024 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
2025 {
2026 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2027
2028 DPRINTFN(9, "\n");
2029
2030 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2031
2032 /* poll one time */
2033 saf1761_otg_xfer_do_fifo(sc, xfer);
2034
2035 if (saf1761_otg_xfer_do_complete(sc, xfer) == 0) {
2036 /*
2037 * Only enable the endpoint interrupt when we are
2038 * actually waiting for data, hence we are dealing
2039 * with level triggered interrupts !
2040 */
2041 saf1761_otg_intr_set(xfer, 1);
2042
2043 /* put transfer on interrupt queue */
2044 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2045
2046 /* start timeout, if any */
2047 if (xfer->timeout != 0) {
2048 usbd_transfer_timeout_ms(xfer,
2049 &saf1761_otg_timeout, xfer->timeout);
2050 }
2051 }
2052 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2053 }
2054
2055 static void
saf1761_otg_root_intr(struct saf1761_otg_softc * sc)2056 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
2057 {
2058 DPRINTFN(9, "\n");
2059
2060 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2061
2062 /* set port bit - we only have one port */
2063 sc->sc_hub_idata[0] = 0x02;
2064
2065 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2066 sizeof(sc->sc_hub_idata));
2067 }
2068
2069 static usb_error_t
saf1761_otg_standard_done_sub(struct usb_xfer * xfer)2070 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
2071 {
2072 struct saf1761_otg_td *td;
2073 uint32_t len;
2074 usb_error_t error;
2075
2076 DPRINTFN(9, "\n");
2077
2078 td = xfer->td_transfer_cache;
2079
2080 do {
2081 len = td->remainder;
2082
2083 /* store last data toggle */
2084 xfer->endpoint->toggle_next = td->toggle;
2085
2086 if (xfer->aframes != xfer->nframes) {
2087 /*
2088 * Verify the length and subtract
2089 * the remainder from "frlengths[]":
2090 */
2091 if (len > xfer->frlengths[xfer->aframes]) {
2092 td->error_any = 1;
2093 } else {
2094 xfer->frlengths[xfer->aframes] -= len;
2095 }
2096 }
2097 /* Check for transfer error */
2098 if (td->error_any) {
2099 /* the transfer is finished */
2100 error = (td->error_stall ?
2101 USB_ERR_STALLED : USB_ERR_IOERROR);
2102 td = NULL;
2103 break;
2104 }
2105 /* Check for short transfer */
2106 if (len > 0) {
2107 if (xfer->flags_int.short_frames_ok ||
2108 xfer->flags_int.isochronous_xfr) {
2109 /* follow alt next */
2110 if (td->alt_next) {
2111 td = td->obj_next;
2112 } else {
2113 td = NULL;
2114 }
2115 } else {
2116 /* the transfer is finished */
2117 td = NULL;
2118 }
2119 error = 0;
2120 break;
2121 }
2122 td = td->obj_next;
2123
2124 /* this USB frame is complete */
2125 error = 0;
2126 break;
2127
2128 } while (0);
2129
2130 /* update transfer cache */
2131
2132 xfer->td_transfer_cache = td;
2133
2134 return (error);
2135 }
2136
2137 static void
saf1761_otg_standard_done(struct usb_xfer * xfer)2138 saf1761_otg_standard_done(struct usb_xfer *xfer)
2139 {
2140 usb_error_t err = 0;
2141
2142 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2143 xfer, xfer->endpoint);
2144
2145 /* reset scanner */
2146
2147 xfer->td_transfer_cache = xfer->td_transfer_first;
2148
2149 if (xfer->flags_int.control_xfr) {
2150 if (xfer->flags_int.control_hdr) {
2151 err = saf1761_otg_standard_done_sub(xfer);
2152 }
2153 xfer->aframes = 1;
2154
2155 if (xfer->td_transfer_cache == NULL) {
2156 goto done;
2157 }
2158 }
2159 while (xfer->aframes != xfer->nframes) {
2160 err = saf1761_otg_standard_done_sub(xfer);
2161 xfer->aframes++;
2162
2163 if (xfer->td_transfer_cache == NULL) {
2164 goto done;
2165 }
2166 }
2167
2168 if (xfer->flags_int.control_xfr &&
2169 !xfer->flags_int.control_act) {
2170 err = saf1761_otg_standard_done_sub(xfer);
2171 }
2172 done:
2173 saf1761_otg_device_done(xfer, err);
2174 }
2175
2176 /*------------------------------------------------------------------------*
2177 * saf1761_otg_device_done
2178 *
2179 * NOTE: this function can be called more than one time on the
2180 * same USB transfer!
2181 *------------------------------------------------------------------------*/
2182 static void
saf1761_otg_device_done(struct usb_xfer * xfer,usb_error_t error)2183 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
2184 {
2185 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2186
2187 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2188
2189 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2190 xfer, xfer->endpoint, error);
2191
2192 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2193
2194 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
2195 saf1761_otg_intr_set(xfer, 0);
2196 } else {
2197 struct saf1761_otg_td *td;
2198
2199 td = xfer->td_transfer_cache;
2200
2201 if (td != NULL)
2202 saf1761_host_channel_free(sc, td);
2203 }
2204
2205 /* dequeue transfer and start next transfer */
2206 usbd_transfer_done(xfer, error);
2207
2208 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2209 }
2210
2211 static void
saf1761_otg_xfer_stall(struct usb_xfer * xfer)2212 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
2213 {
2214 saf1761_otg_device_done(xfer, USB_ERR_STALLED);
2215 }
2216
2217 static void
saf1761_otg_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)2218 saf1761_otg_set_stall(struct usb_device *udev,
2219 struct usb_endpoint *ep, uint8_t *did_stall)
2220 {
2221 struct saf1761_otg_softc *sc;
2222 uint8_t ep_no;
2223 uint8_t ep_type;
2224 uint8_t ep_dir;
2225
2226 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2227
2228 /* check mode */
2229 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2230 /* not supported */
2231 return;
2232 }
2233
2234 DPRINTFN(5, "endpoint=%p\n", ep);
2235
2236 /* set STALL bit */
2237 sc = SAF1761_OTG_BUS2SC(udev->bus);
2238
2239 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2240 ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2241 ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2242
2243 if (ep_type == UE_CONTROL) {
2244 /* should not happen */
2245 return;
2246 }
2247 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2248
2249 /* select the correct endpoint */
2250 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2251 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2252 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2253 SOTG_EP_INDEX_DIR_OUT));
2254
2255 /* set stall */
2256 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2257
2258 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2259 }
2260
2261 static void
saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc * sc,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)2262 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2263 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2264 {
2265 if (ep_type == UE_CONTROL) {
2266 /* clearing stall is not needed */
2267 return;
2268 }
2269 /* select the correct endpoint */
2270 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2271 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2272 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2273 SOTG_EP_INDEX_DIR_OUT));
2274
2275 /* disable endpoint */
2276 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2277 /* enable endpoint again - will clear data toggle */
2278 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2279
2280 /* clear buffer */
2281 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2282 /* clear stall */
2283 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2284 }
2285
2286 static void
saf1761_otg_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)2287 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2288 {
2289 struct saf1761_otg_softc *sc;
2290 struct usb_endpoint_descriptor *ed;
2291
2292 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2293
2294 DPRINTFN(5, "endpoint=%p\n", ep);
2295
2296 /* check mode */
2297 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2298 /* not supported */
2299 return;
2300 }
2301 /* get softc */
2302 sc = SAF1761_OTG_BUS2SC(udev->bus);
2303
2304 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2305
2306 /* get endpoint descriptor */
2307 ed = ep->edesc;
2308
2309 /* reset endpoint */
2310 saf1761_otg_clear_stall_sub_locked(sc,
2311 (ed->bEndpointAddress & UE_ADDR),
2312 (ed->bmAttributes & UE_XFERTYPE),
2313 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2314
2315 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2316 }
2317
2318 usb_error_t
saf1761_otg_init(struct saf1761_otg_softc * sc)2319 saf1761_otg_init(struct saf1761_otg_softc *sc)
2320 {
2321 const struct usb_hw_ep_profile *pf;
2322 uint32_t x;
2323
2324 DPRINTF("\n");
2325
2326 /* set up the bus structure */
2327 sc->sc_bus.usbrev = USB_REV_2_0;
2328 sc->sc_bus.methods = &saf1761_otg_bus_methods;
2329
2330 USB_BUS_LOCK(&sc->sc_bus);
2331
2332 /* Reset Host controller, including HW mode */
2333 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2334
2335 DELAY(1000);
2336
2337 /* Reset Host controller, including HW mode */
2338 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2339
2340 /* wait a bit */
2341 DELAY(1000);
2342
2343 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2344
2345 /* wait a bit */
2346 DELAY(1000);
2347
2348 /* Enable interrupts */
2349 sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2350 SOTG_HW_MODE_CTRL_COMN_INT;
2351
2352 /* unlock device */
2353 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2354
2355 /*
2356 * Set correct hardware mode, must be written twice if bus
2357 * width is changed:
2358 */
2359 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2360 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2361
2362 SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2363 SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2364
2365 DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2366 SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2367 SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2368 SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2369 SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2370 SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2371
2372 /* reset device controller */
2373 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2374 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2375
2376 /* wait a bit */
2377 DELAY(1000);
2378
2379 /* reset host controller */
2380 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2381
2382 /* wait for reset to clear */
2383 for (x = 0; x != 10; x++) {
2384 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2385 break;
2386 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2387 }
2388
2389 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2390 SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2391
2392 /* wait a bit */
2393 DELAY(1000);
2394
2395 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2396
2397 /* wait a bit */
2398 DELAY(1000);
2399
2400 /* do a pulldown */
2401 saf1761_otg_pull_down(sc);
2402
2403 /* wait 10ms for pulldown to stabilise */
2404 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2405
2406 for (x = 1;; x++) {
2407 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2408 if (pf == NULL)
2409 break;
2410
2411 /* select the correct endpoint */
2412 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2413 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2414 SOTG_EP_INDEX_DIR_IN);
2415
2416 /* select the maximum packet size */
2417 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2418
2419 /* select the correct endpoint */
2420 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2421 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2422 SOTG_EP_INDEX_DIR_OUT);
2423
2424 /* select the maximum packet size */
2425 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2426 }
2427
2428 /* enable interrupts */
2429 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2430 SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2431
2432 sc->sc_interrupt_cfg |=
2433 SOTG_INTERRUPT_CFG_CDBGMOD |
2434 SOTG_INTERRUPT_CFG_DDBGMODIN |
2435 SOTG_INTERRUPT_CFG_DDBGMODOUT;
2436
2437 /* set default values */
2438 SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2439
2440 /* enable VBUS and ID interrupt */
2441 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2442 SOTG_IRQ_ENABLE_CLR(0xFFFF));
2443 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2444 SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2445
2446 /* enable interrupts */
2447 sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2448 SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2449 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2450
2451 /*
2452 * Connect ATX port 1 to device controller, select external
2453 * charge pump and driver VBUS to +5V:
2454 */
2455 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2456 SOTG_CTRL_CLR(0xFFFF));
2457 #ifdef __rtems__
2458 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2459 SOTG_CTRL_SET(SOTG_CTRL_SEL_CP_EXT | SOTG_CTRL_VBUS_DRV));
2460 #else
2461 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2462 SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2463 SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2464 SOTG_CTRL_VBUS_DRV));
2465 #endif
2466 /* disable device address */
2467 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2468
2469 /* enable host controller clock and preserve reserved bits */
2470 x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2471 SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2472
2473 /* wait 10ms for clock */
2474 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2475
2476 /* enable configuration flag */
2477 SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2478
2479 /* clear RAM block */
2480 for (x = 0x400; x != 0x10000; x += 4)
2481 SAF1761_WRITE_LE_4(sc, x, 0);
2482
2483 /* start the HC */
2484 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2485
2486 DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2487
2488 /* make HC scan all PTDs */
2489 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2490 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2491 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2492
2493 /* skip all PTDs by default */
2494 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2495 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2496 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2497
2498 /* activate all PTD types */
2499 SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2500 SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2501 SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2502 SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2503
2504 /* we don't use the AND mask */
2505 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2506 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2507 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2508
2509 /* enable all PTD OR interrupts by default */
2510 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2511 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2512 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2513
2514 /* enable HC interrupts */
2515 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2516 SOTG_HCINTERRUPT_OTG_IRQ |
2517 SOTG_HCINTERRUPT_ISO_IRQ |
2518 SOTG_HCINTERRUPT_ALT_IRQ |
2519 SOTG_HCINTERRUPT_INT_IRQ);
2520
2521 /* poll initial VBUS status */
2522 saf1761_otg_update_vbus(sc);
2523
2524 USB_BUS_UNLOCK(&sc->sc_bus);
2525
2526 /* catch any lost interrupts */
2527
2528 saf1761_otg_do_poll(&sc->sc_bus);
2529
2530 return (0); /* success */
2531 }
2532
2533 void
saf1761_otg_uninit(struct saf1761_otg_softc * sc)2534 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2535 {
2536 USB_BUS_LOCK(&sc->sc_bus);
2537
2538 /* disable all interrupts */
2539 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2540
2541 sc->sc_flags.port_powered = 0;
2542 sc->sc_flags.status_vbus = 0;
2543 sc->sc_flags.status_bus_reset = 0;
2544 sc->sc_flags.status_suspend = 0;
2545 sc->sc_flags.change_suspend = 0;
2546 sc->sc_flags.change_connect = 1;
2547
2548 saf1761_otg_pull_down(sc);
2549 USB_BUS_UNLOCK(&sc->sc_bus);
2550 }
2551
2552 static void
saf1761_otg_suspend(struct saf1761_otg_softc * sc)2553 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2554 {
2555 /* TODO */
2556 }
2557
2558 static void
saf1761_otg_resume(struct saf1761_otg_softc * sc)2559 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2560 {
2561 /* TODO */
2562 }
2563
2564 static void
saf1761_otg_do_poll(struct usb_bus * bus)2565 saf1761_otg_do_poll(struct usb_bus *bus)
2566 {
2567 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2568
2569 USB_BUS_LOCK(&sc->sc_bus);
2570 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2571 saf1761_otg_interrupt_poll_locked(sc);
2572 saf1761_otg_interrupt_complete_locked(sc);
2573 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2574 USB_BUS_UNLOCK(&sc->sc_bus);
2575 }
2576
2577 /*------------------------------------------------------------------------*
2578 * saf1761_otg control support
2579 * saf1761_otg interrupt support
2580 * saf1761_otg bulk support
2581 *------------------------------------------------------------------------*/
2582 static void
saf1761_otg_device_non_isoc_open(struct usb_xfer * xfer)2583 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2584 {
2585 return;
2586 }
2587
2588 static void
saf1761_otg_device_non_isoc_close(struct usb_xfer * xfer)2589 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2590 {
2591 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2592 }
2593
2594 static void
saf1761_otg_device_non_isoc_enter(struct usb_xfer * xfer)2595 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2596 {
2597 return;
2598 }
2599
2600 static void
saf1761_otg_device_non_isoc_start(struct usb_xfer * xfer)2601 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2602 {
2603 /* setup TDs */
2604 saf1761_otg_setup_standard_chain(xfer);
2605 saf1761_otg_start_standard_chain(xfer);
2606 }
2607
2608 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2609 {
2610 .open = saf1761_otg_device_non_isoc_open,
2611 .close = saf1761_otg_device_non_isoc_close,
2612 .enter = saf1761_otg_device_non_isoc_enter,
2613 .start = saf1761_otg_device_non_isoc_start,
2614 };
2615
2616 /*------------------------------------------------------------------------*
2617 * saf1761_otg device side isochronous support
2618 *------------------------------------------------------------------------*/
2619 static void
saf1761_otg_device_isoc_open(struct usb_xfer * xfer)2620 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2621 {
2622 return;
2623 }
2624
2625 static void
saf1761_otg_device_isoc_close(struct usb_xfer * xfer)2626 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2627 {
2628 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2629 }
2630
2631 static void
saf1761_otg_device_isoc_enter(struct usb_xfer * xfer)2632 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2633 {
2634 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2635 uint32_t nframes;
2636
2637 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2638 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2639
2640 /* get the current frame index - we don't need the high bits */
2641
2642 nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2643
2644 if (usbd_xfer_get_isochronous_start_frame(
2645 xfer, nframes, 0, 1, SOTG_FRAME_NUM_SOFR_MASK, NULL))
2646 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2647
2648 /* setup TDs */
2649 saf1761_otg_setup_standard_chain(xfer);
2650 }
2651
2652 static void
saf1761_otg_device_isoc_start(struct usb_xfer * xfer)2653 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2654 {
2655 /* start TD chain */
2656 saf1761_otg_start_standard_chain(xfer);
2657 }
2658
2659 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2660 {
2661 .open = saf1761_otg_device_isoc_open,
2662 .close = saf1761_otg_device_isoc_close,
2663 .enter = saf1761_otg_device_isoc_enter,
2664 .start = saf1761_otg_device_isoc_start,
2665 };
2666
2667 /*------------------------------------------------------------------------*
2668 * saf1761_otg host side isochronous support
2669 *------------------------------------------------------------------------*/
2670 static void
saf1761_otg_host_isoc_open(struct usb_xfer * xfer)2671 saf1761_otg_host_isoc_open(struct usb_xfer *xfer)
2672 {
2673 return;
2674 }
2675
2676 static void
saf1761_otg_host_isoc_close(struct usb_xfer * xfer)2677 saf1761_otg_host_isoc_close(struct usb_xfer *xfer)
2678 {
2679 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2680 }
2681
2682 static void
saf1761_otg_host_isoc_enter(struct usb_xfer * xfer)2683 saf1761_otg_host_isoc_enter(struct usb_xfer *xfer)
2684 {
2685 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2686 uint32_t nframes;
2687
2688 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2689 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2690
2691 /* get the current frame index - we don't need the high bits */
2692
2693 nframes = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) & SOTG_FRINDEX_MASK) >> 3;
2694
2695 if (usbd_xfer_get_isochronous_start_frame(
2696 xfer, nframes, 0, 1, SOTG_FRINDEX_MASK >> 3, NULL))
2697 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2698
2699 /* setup TDs */
2700 saf1761_otg_setup_standard_chain(xfer);
2701 }
2702
2703 static void
saf1761_otg_host_isoc_start(struct usb_xfer * xfer)2704 saf1761_otg_host_isoc_start(struct usb_xfer *xfer)
2705 {
2706 /* start TD chain */
2707 saf1761_otg_start_standard_chain(xfer);
2708 }
2709
2710 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods =
2711 {
2712 .open = saf1761_otg_host_isoc_open,
2713 .close = saf1761_otg_host_isoc_close,
2714 .enter = saf1761_otg_host_isoc_enter,
2715 .start = saf1761_otg_host_isoc_start,
2716 };
2717
2718 /*------------------------------------------------------------------------*
2719 * saf1761_otg root control support
2720 *------------------------------------------------------------------------*
2721 * Simulate a hardware HUB by handling all the necessary requests.
2722 *------------------------------------------------------------------------*/
2723 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2724
2725 static const struct usb_device_descriptor saf1761_otg_devd = {
2726 .bLength = sizeof(struct usb_device_descriptor),
2727 .bDescriptorType = UDESC_DEVICE,
2728 HSETW(.idVendor, 0x04cc),
2729 HSETW(.idProduct, 0x1761),
2730 .bcdUSB = {0x00, 0x02},
2731 .bDeviceClass = UDCLASS_HUB,
2732 .bDeviceSubClass = UDSUBCLASS_HUB,
2733 .bDeviceProtocol = UDPROTO_FSHUB,
2734 .bMaxPacketSize = 64,
2735 .bcdDevice = {0x00, 0x01},
2736 .iManufacturer = 1,
2737 .iProduct = 2,
2738 .bNumConfigurations = 1,
2739 };
2740
2741 static const struct usb_device_qualifier saf1761_otg_odevd = {
2742 .bLength = sizeof(struct usb_device_qualifier),
2743 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2744 .bcdUSB = {0x00, 0x02},
2745 .bDeviceClass = UDCLASS_HUB,
2746 .bDeviceSubClass = UDSUBCLASS_HUB,
2747 .bDeviceProtocol = UDPROTO_FSHUB,
2748 .bMaxPacketSize0 = 0,
2749 .bNumConfigurations = 0,
2750 };
2751
2752 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2753 .confd = {
2754 .bLength = sizeof(struct usb_config_descriptor),
2755 .bDescriptorType = UDESC_CONFIG,
2756 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2757 .bNumInterface = 1,
2758 .bConfigurationValue = 1,
2759 .iConfiguration = 0,
2760 .bmAttributes = UC_SELF_POWERED,
2761 .bMaxPower = 0,
2762 },
2763 .ifcd = {
2764 .bLength = sizeof(struct usb_interface_descriptor),
2765 .bDescriptorType = UDESC_INTERFACE,
2766 .bNumEndpoints = 1,
2767 .bInterfaceClass = UICLASS_HUB,
2768 .bInterfaceSubClass = UISUBCLASS_HUB,
2769 .bInterfaceProtocol = 0,
2770 },
2771
2772 .endpd = {
2773 .bLength = sizeof(struct usb_endpoint_descriptor),
2774 .bDescriptorType = UDESC_ENDPOINT,
2775 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2776 .bmAttributes = UE_INTERRUPT,
2777 .wMaxPacketSize[0] = 8,
2778 .bInterval = 255,
2779 },
2780 };
2781
2782 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2783 .bDescLength = sizeof(saf1761_otg_hubd),
2784 .bDescriptorType = UDESC_HUB,
2785 .bNbrPorts = SOTG_NUM_PORTS,
2786 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2787 .bPwrOn2PwrGood = 50,
2788 .bHubContrCurrent = 0,
2789 .DeviceRemovable = {0}, /* port is removable */
2790 };
2791
2792 #define STRING_VENDOR \
2793 "N\0X\0P"
2794
2795 #define STRING_PRODUCT \
2796 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2797
2798 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2799 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2800
2801 static usb_error_t
saf1761_otg_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)2802 saf1761_otg_roothub_exec(struct usb_device *udev,
2803 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2804 {
2805 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2806 const void *ptr;
2807 uint16_t len;
2808 uint16_t value;
2809 uint16_t index;
2810 uint32_t temp;
2811 uint32_t i;
2812 usb_error_t err;
2813
2814 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2815
2816 /* buffer reset */
2817 ptr = (const void *)&sc->sc_hub_temp;
2818 len = 0;
2819 err = 0;
2820
2821 value = UGETW(req->wValue);
2822 index = UGETW(req->wIndex);
2823
2824 /* demultiplex the control request */
2825
2826 switch (req->bmRequestType) {
2827 case UT_READ_DEVICE:
2828 switch (req->bRequest) {
2829 case UR_GET_DESCRIPTOR:
2830 goto tr_handle_get_descriptor;
2831 case UR_GET_CONFIG:
2832 goto tr_handle_get_config;
2833 case UR_GET_STATUS:
2834 goto tr_handle_get_status;
2835 default:
2836 goto tr_stalled;
2837 }
2838 break;
2839
2840 case UT_WRITE_DEVICE:
2841 switch (req->bRequest) {
2842 case UR_SET_ADDRESS:
2843 goto tr_handle_set_address;
2844 case UR_SET_CONFIG:
2845 goto tr_handle_set_config;
2846 case UR_CLEAR_FEATURE:
2847 goto tr_valid; /* nop */
2848 case UR_SET_DESCRIPTOR:
2849 goto tr_valid; /* nop */
2850 case UR_SET_FEATURE:
2851 default:
2852 goto tr_stalled;
2853 }
2854 break;
2855
2856 case UT_WRITE_ENDPOINT:
2857 switch (req->bRequest) {
2858 case UR_CLEAR_FEATURE:
2859 switch (UGETW(req->wValue)) {
2860 case UF_ENDPOINT_HALT:
2861 goto tr_handle_clear_halt;
2862 case UF_DEVICE_REMOTE_WAKEUP:
2863 goto tr_handle_clear_wakeup;
2864 default:
2865 goto tr_stalled;
2866 }
2867 break;
2868 case UR_SET_FEATURE:
2869 switch (UGETW(req->wValue)) {
2870 case UF_ENDPOINT_HALT:
2871 goto tr_handle_set_halt;
2872 case UF_DEVICE_REMOTE_WAKEUP:
2873 goto tr_handle_set_wakeup;
2874 default:
2875 goto tr_stalled;
2876 }
2877 break;
2878 case UR_SYNCH_FRAME:
2879 goto tr_valid; /* nop */
2880 default:
2881 goto tr_stalled;
2882 }
2883 break;
2884
2885 case UT_READ_ENDPOINT:
2886 switch (req->bRequest) {
2887 case UR_GET_STATUS:
2888 goto tr_handle_get_ep_status;
2889 default:
2890 goto tr_stalled;
2891 }
2892 break;
2893
2894 case UT_WRITE_INTERFACE:
2895 switch (req->bRequest) {
2896 case UR_SET_INTERFACE:
2897 goto tr_handle_set_interface;
2898 case UR_CLEAR_FEATURE:
2899 goto tr_valid; /* nop */
2900 case UR_SET_FEATURE:
2901 default:
2902 goto tr_stalled;
2903 }
2904 break;
2905
2906 case UT_READ_INTERFACE:
2907 switch (req->bRequest) {
2908 case UR_GET_INTERFACE:
2909 goto tr_handle_get_interface;
2910 case UR_GET_STATUS:
2911 goto tr_handle_get_iface_status;
2912 default:
2913 goto tr_stalled;
2914 }
2915 break;
2916
2917 case UT_WRITE_CLASS_INTERFACE:
2918 case UT_WRITE_VENDOR_INTERFACE:
2919 /* XXX forward */
2920 break;
2921
2922 case UT_READ_CLASS_INTERFACE:
2923 case UT_READ_VENDOR_INTERFACE:
2924 /* XXX forward */
2925 break;
2926
2927 case UT_WRITE_CLASS_DEVICE:
2928 switch (req->bRequest) {
2929 case UR_CLEAR_FEATURE:
2930 goto tr_valid;
2931 case UR_SET_DESCRIPTOR:
2932 case UR_SET_FEATURE:
2933 break;
2934 default:
2935 goto tr_stalled;
2936 }
2937 break;
2938
2939 case UT_WRITE_CLASS_OTHER:
2940 switch (req->bRequest) {
2941 case UR_CLEAR_FEATURE:
2942 if (index == SOTG_HOST_PORT_NUM)
2943 goto tr_handle_clear_port_feature_host;
2944 else if (index == SOTG_DEVICE_PORT_NUM)
2945 goto tr_handle_clear_port_feature_device;
2946 else
2947 goto tr_stalled;
2948 case UR_SET_FEATURE:
2949 if (index == SOTG_HOST_PORT_NUM)
2950 goto tr_handle_set_port_feature_host;
2951 else if (index == SOTG_DEVICE_PORT_NUM)
2952 goto tr_handle_set_port_feature_device;
2953 else
2954 goto tr_stalled;
2955 case UR_CLEAR_TT_BUFFER:
2956 case UR_RESET_TT:
2957 case UR_STOP_TT:
2958 goto tr_valid;
2959
2960 default:
2961 goto tr_stalled;
2962 }
2963 break;
2964
2965 case UT_READ_CLASS_OTHER:
2966 switch (req->bRequest) {
2967 case UR_GET_TT_STATE:
2968 goto tr_handle_get_tt_state;
2969 case UR_GET_STATUS:
2970 if (index == SOTG_HOST_PORT_NUM)
2971 goto tr_handle_get_port_status_host;
2972 else if (index == SOTG_DEVICE_PORT_NUM)
2973 goto tr_handle_get_port_status_device;
2974 else
2975 goto tr_stalled;
2976 default:
2977 goto tr_stalled;
2978 }
2979 break;
2980
2981 case UT_READ_CLASS_DEVICE:
2982 switch (req->bRequest) {
2983 case UR_GET_DESCRIPTOR:
2984 goto tr_handle_get_class_descriptor;
2985 case UR_GET_STATUS:
2986 goto tr_handle_get_class_status;
2987
2988 default:
2989 goto tr_stalled;
2990 }
2991 break;
2992 default:
2993 goto tr_stalled;
2994 }
2995 goto tr_valid;
2996
2997 tr_handle_get_descriptor:
2998 switch (value >> 8) {
2999 case UDESC_DEVICE:
3000 if (value & 0xff)
3001 goto tr_stalled;
3002 len = sizeof(saf1761_otg_devd);
3003 ptr = (const void *)&saf1761_otg_devd;
3004 goto tr_valid;
3005 case UDESC_DEVICE_QUALIFIER:
3006 if (value & 0xff)
3007 goto tr_stalled;
3008 len = sizeof(saf1761_otg_odevd);
3009 ptr = (const void *)&saf1761_otg_odevd;
3010 goto tr_valid;
3011 case UDESC_CONFIG:
3012 if (value & 0xff)
3013 goto tr_stalled;
3014 len = sizeof(saf1761_otg_confd);
3015 ptr = (const void *)&saf1761_otg_confd;
3016 goto tr_valid;
3017 case UDESC_STRING:
3018 switch (value & 0xff) {
3019 case 0: /* Language table */
3020 len = sizeof(usb_string_lang_en);
3021 ptr = (const void *)&usb_string_lang_en;
3022 goto tr_valid;
3023
3024 case 1: /* Vendor */
3025 len = sizeof(saf1761_otg_vendor);
3026 ptr = (const void *)&saf1761_otg_vendor;
3027 goto tr_valid;
3028
3029 case 2: /* Product */
3030 len = sizeof(saf1761_otg_product);
3031 ptr = (const void *)&saf1761_otg_product;
3032 goto tr_valid;
3033 default:
3034 break;
3035 }
3036 break;
3037 default:
3038 goto tr_stalled;
3039 }
3040 goto tr_stalled;
3041
3042 tr_handle_get_config:
3043 len = 1;
3044 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3045 goto tr_valid;
3046
3047 tr_handle_get_status:
3048 len = 2;
3049 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3050 goto tr_valid;
3051
3052 tr_handle_set_address:
3053 if (value & 0xFF00)
3054 goto tr_stalled;
3055
3056 sc->sc_rt_addr = value;
3057 goto tr_valid;
3058
3059 tr_handle_set_config:
3060 if (value >= 2)
3061 goto tr_stalled;
3062 sc->sc_conf = value;
3063 goto tr_valid;
3064
3065 tr_handle_get_interface:
3066 len = 1;
3067 sc->sc_hub_temp.wValue[0] = 0;
3068 goto tr_valid;
3069
3070 tr_handle_get_tt_state:
3071 tr_handle_get_class_status:
3072 tr_handle_get_iface_status:
3073 tr_handle_get_ep_status:
3074 len = 2;
3075 USETW(sc->sc_hub_temp.wValue, 0);
3076 goto tr_valid;
3077
3078 tr_handle_set_halt:
3079 tr_handle_set_interface:
3080 tr_handle_set_wakeup:
3081 tr_handle_clear_wakeup:
3082 tr_handle_clear_halt:
3083 goto tr_valid;
3084
3085 tr_handle_clear_port_feature_device:
3086 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3087
3088 switch (value) {
3089 case UHF_PORT_SUSPEND:
3090 saf1761_otg_wakeup_peer(sc);
3091 break;
3092
3093 case UHF_PORT_ENABLE:
3094 sc->sc_flags.port_enabled = 0;
3095 break;
3096
3097 case UHF_PORT_TEST:
3098 case UHF_PORT_INDICATOR:
3099 case UHF_C_PORT_ENABLE:
3100 case UHF_C_PORT_OVER_CURRENT:
3101 case UHF_C_PORT_RESET:
3102 /* nops */
3103 break;
3104 case UHF_PORT_POWER:
3105 sc->sc_flags.port_powered = 0;
3106 saf1761_otg_pull_down(sc);
3107 break;
3108 case UHF_C_PORT_CONNECTION:
3109 sc->sc_flags.change_connect = 0;
3110 break;
3111 case UHF_C_PORT_SUSPEND:
3112 sc->sc_flags.change_suspend = 0;
3113 break;
3114 default:
3115 err = USB_ERR_IOERROR;
3116 goto tr_valid;
3117 }
3118 goto tr_valid;
3119
3120 tr_handle_clear_port_feature_host:
3121 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3122
3123 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3124
3125 switch (value) {
3126 case UHF_PORT_ENABLE:
3127 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
3128 break;
3129 case UHF_PORT_SUSPEND:
3130 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
3131 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
3132
3133 /* wait 20ms for resume sequence to complete */
3134 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3135
3136 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
3137 SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
3138
3139 /* 4ms settle time */
3140 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3141 break;
3142 case UHF_PORT_INDICATOR:
3143 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
3144 break;
3145 case UHF_PORT_TEST:
3146 case UHF_C_PORT_ENABLE:
3147 case UHF_C_PORT_OVER_CURRENT:
3148 case UHF_C_PORT_RESET:
3149 case UHF_C_PORT_SUSPEND:
3150 /* NOPs */
3151 break;
3152 case UHF_PORT_POWER:
3153 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
3154 break;
3155 case UHF_C_PORT_CONNECTION:
3156 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
3157 break;
3158 default:
3159 err = USB_ERR_IOERROR;
3160 goto tr_valid;
3161 }
3162 goto tr_valid;
3163
3164 tr_handle_set_port_feature_device:
3165 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3166
3167 switch (value) {
3168 case UHF_PORT_ENABLE:
3169 sc->sc_flags.port_enabled = 1;
3170 break;
3171 case UHF_PORT_SUSPEND:
3172 case UHF_PORT_RESET:
3173 case UHF_PORT_TEST:
3174 case UHF_PORT_INDICATOR:
3175 /* nops */
3176 break;
3177 case UHF_PORT_POWER:
3178 sc->sc_flags.port_powered = 1;
3179 break;
3180 default:
3181 err = USB_ERR_IOERROR;
3182 goto tr_valid;
3183 }
3184 goto tr_valid;
3185
3186 tr_handle_set_port_feature_host:
3187 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3188
3189 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3190
3191 switch (value) {
3192 case UHF_PORT_ENABLE:
3193 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
3194 break;
3195 case UHF_PORT_SUSPEND:
3196 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
3197 break;
3198 case UHF_PORT_RESET:
3199 DPRINTFN(6, "reset port %d\n", index);
3200
3201 /* Start reset sequence. */
3202 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
3203
3204 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
3205
3206 /* Wait for reset to complete. */
3207 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3208 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3209
3210 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
3211
3212 /* Wait for HC to complete reset. */
3213 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
3214
3215 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3216
3217 DPRINTF("After reset, status=0x%08x\n", temp);
3218 if (temp & SOTG_PORTSC1_PR) {
3219 device_printf(sc->sc_bus.bdev, "port reset timeout\n");
3220 err = USB_ERR_TIMEOUT;
3221 goto tr_valid;
3222 }
3223 if (!(temp & SOTG_PORTSC1_PED)) {
3224 /* Not a high speed device, give up ownership.*/
3225 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
3226 break;
3227 }
3228 sc->sc_isreset = 1;
3229 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
3230 break;
3231 case UHF_PORT_POWER:
3232 DPRINTFN(3, "set port power %d\n", index);
3233 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
3234 break;
3235
3236 case UHF_PORT_TEST:
3237 DPRINTFN(3, "set port test %d\n", index);
3238 break;
3239
3240 case UHF_PORT_INDICATOR:
3241 DPRINTFN(3, "set port ind %d\n", index);
3242 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
3243 break;
3244 default:
3245 err = USB_ERR_IOERROR;
3246 goto tr_valid;
3247 }
3248 goto tr_valid;
3249
3250 tr_handle_get_port_status_device:
3251
3252 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
3253
3254 if (sc->sc_flags.status_vbus) {
3255 saf1761_otg_pull_up(sc);
3256 } else {
3257 saf1761_otg_pull_down(sc);
3258 }
3259
3260 /* Select FULL-speed and Device Side Mode */
3261
3262 value = UPS_PORT_MODE_DEVICE;
3263
3264 if (sc->sc_flags.port_powered)
3265 value |= UPS_PORT_POWER;
3266
3267 if (sc->sc_flags.port_enabled)
3268 value |= UPS_PORT_ENABLED;
3269
3270 if (sc->sc_flags.status_vbus &&
3271 sc->sc_flags.status_bus_reset)
3272 value |= UPS_CURRENT_CONNECT_STATUS;
3273
3274 if (sc->sc_flags.status_suspend)
3275 value |= UPS_SUSPEND;
3276
3277 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3278
3279 value = 0;
3280
3281 if (sc->sc_flags.change_connect)
3282 value |= UPS_C_CONNECT_STATUS;
3283
3284 if (sc->sc_flags.change_suspend)
3285 value |= UPS_C_SUSPEND;
3286
3287 USETW(sc->sc_hub_temp.ps.wPortChange, value);
3288 len = sizeof(sc->sc_hub_temp.ps);
3289 goto tr_valid;
3290
3291 tr_handle_get_port_status_host:
3292
3293 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3294
3295 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3296
3297 i = UPS_HIGH_SPEED;
3298
3299 if (temp & SOTG_PORTSC1_ECCS)
3300 i |= UPS_CURRENT_CONNECT_STATUS;
3301 if (temp & SOTG_PORTSC1_PED)
3302 i |= UPS_PORT_ENABLED;
3303 if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3304 i |= UPS_SUSPEND;
3305 if (temp & SOTG_PORTSC1_PR)
3306 i |= UPS_RESET;
3307 if (temp & SOTG_PORTSC1_PP)
3308 i |= UPS_PORT_POWER;
3309
3310 USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3311 i = 0;
3312
3313 if (temp & SOTG_PORTSC1_ECSC)
3314 i |= UPS_C_CONNECT_STATUS;
3315 if (temp & SOTG_PORTSC1_FPR)
3316 i |= UPS_C_SUSPEND;
3317 if (sc->sc_isreset)
3318 i |= UPS_C_PORT_RESET;
3319 USETW(sc->sc_hub_temp.ps.wPortChange, i);
3320 len = sizeof(sc->sc_hub_temp.ps);
3321 goto tr_valid;
3322
3323 tr_handle_get_class_descriptor:
3324 if (value & 0xFF)
3325 goto tr_stalled;
3326 ptr = (const void *)&saf1761_otg_hubd;
3327 len = sizeof(saf1761_otg_hubd);
3328 goto tr_valid;
3329
3330 tr_stalled:
3331 err = USB_ERR_STALLED;
3332 tr_valid:
3333 *plength = len;
3334 *pptr = ptr;
3335 return (err);
3336 }
3337
3338 static void
saf1761_otg_xfer_setup(struct usb_setup_params * parm)3339 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3340 {
3341 struct saf1761_otg_softc *sc;
3342 struct usb_xfer *xfer;
3343 void *last_obj;
3344 uint32_t dw1;
3345 uint32_t ntd;
3346 uint32_t n;
3347 uint8_t ep_no;
3348 uint8_t ep_type;
3349
3350 sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3351 xfer = parm->curr_xfer;
3352
3353 /*
3354 * NOTE: This driver does not use any of the parameters that
3355 * are computed from the following values. Just set some
3356 * reasonable dummies:
3357 */
3358 parm->hc_max_packet_size = 0x500;
3359 parm->hc_max_packet_count = 1;
3360 parm->hc_max_frame_size = 0x500;
3361
3362 usbd_transfer_setup_sub(parm);
3363
3364 /*
3365 * Compute maximum number of TDs:
3366 */
3367 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3368
3369 if (ep_type == UE_CONTROL) {
3370 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3371
3372 } else {
3373 ntd = xfer->nframes + 1 /* SYNC */ ;
3374 }
3375
3376 /*
3377 * check if "usbd_transfer_setup_sub" set an error
3378 */
3379 if (parm->err)
3380 return;
3381
3382 /*
3383 * allocate transfer descriptors
3384 */
3385 last_obj = NULL;
3386
3387 ep_no = xfer->endpointno & UE_ADDR;
3388
3389 /*
3390 * Check profile stuff
3391 */
3392 if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3393 const struct usb_hw_ep_profile *pf;
3394
3395 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3396
3397 if (pf == NULL) {
3398 /* should not happen */
3399 parm->err = USB_ERR_INVAL;
3400 return;
3401 }
3402 }
3403
3404 dw1 = (xfer->address << 3) | (ep_type << 12);
3405
3406 switch (parm->udev->speed) {
3407 case USB_SPEED_FULL:
3408 case USB_SPEED_LOW:
3409 /* check if root HUB port is running High Speed */
3410 if (parm->udev->parent_hs_hub != NULL) {
3411 dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3412 dw1 |= (parm->udev->hs_port_no << 18);
3413 dw1 |= (parm->udev->hs_hub_addr << 25);
3414 if (parm->udev->speed == USB_SPEED_LOW)
3415 dw1 |= (1 << 17);
3416 }
3417 break;
3418 default:
3419 break;
3420 }
3421
3422 /* align data */
3423 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3424
3425 for (n = 0; n != ntd; n++) {
3426 struct saf1761_otg_td *td;
3427
3428 if (parm->buf) {
3429 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3430
3431 /* init TD */
3432 td->max_packet_size = xfer->max_packet_size;
3433 td->ep_index = ep_no;
3434 td->ep_type = ep_type;
3435 td->dw1_value = dw1;
3436 td->uframe = 0;
3437
3438 if (ep_type == UE_INTERRUPT) {
3439 if (xfer->interval > 32)
3440 td->interval = (32 / 2) << 3;
3441 else
3442 td->interval = (xfer->interval / 2) << 3;
3443 } else {
3444 td->interval = 0;
3445 }
3446 td->obj_next = last_obj;
3447
3448 last_obj = td;
3449 }
3450 parm->size[0] += sizeof(*td);
3451 }
3452
3453 xfer->td_start[0] = last_obj;
3454 }
3455
3456 static void
saf1761_otg_xfer_unsetup(struct usb_xfer * xfer)3457 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3458 {
3459 }
3460
3461 static void
saf1761_otg_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3462 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3463 struct usb_endpoint *ep)
3464 {
3465 uint16_t mps;
3466
3467 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3468 ep, udev->address,
3469 edesc->bEndpointAddress, udev->flags.usb_mode);
3470
3471 if (udev->parent_hub == NULL) {
3472 /* root HUB has special endpoint handling */
3473 return;
3474 }
3475
3476 /* Verify wMaxPacketSize */
3477 mps = UGETW(edesc->wMaxPacketSize);
3478 if (udev->speed == USB_SPEED_HIGH) {
3479 if ((mps >> 11) & 3) {
3480 DPRINTF("A packet multiplier different from "
3481 "1 is not supported\n");
3482 return;
3483 }
3484 }
3485 if (mps > SOTG_HS_MAX_PACKET_SIZE) {
3486 DPRINTF("Packet size %d bigger than %d\n",
3487 (int)mps, SOTG_HS_MAX_PACKET_SIZE);
3488 return;
3489 }
3490 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3491 if (udev->speed != USB_SPEED_FULL &&
3492 udev->speed != USB_SPEED_HIGH) {
3493 /* not supported */
3494 return;
3495 }
3496 switch (edesc->bmAttributes & UE_XFERTYPE) {
3497 case UE_ISOCHRONOUS:
3498 ep->methods = &saf1761_otg_device_isoc_methods;
3499 break;
3500 default:
3501 ep->methods = &saf1761_otg_non_isoc_methods;
3502 break;
3503 }
3504 } else {
3505 switch (edesc->bmAttributes & UE_XFERTYPE) {
3506 case UE_ISOCHRONOUS:
3507 ep->methods = &saf1761_otg_host_isoc_methods;
3508 break;
3509 default:
3510 ep->methods = &saf1761_otg_non_isoc_methods;
3511 break;
3512 }
3513 }
3514 }
3515
3516 static void
saf1761_otg_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)3517 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3518 {
3519 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3520
3521 switch (state) {
3522 case USB_HW_POWER_SUSPEND:
3523 saf1761_otg_suspend(sc);
3524 break;
3525 case USB_HW_POWER_SHUTDOWN:
3526 saf1761_otg_uninit(sc);
3527 break;
3528 case USB_HW_POWER_RESUME:
3529 saf1761_otg_resume(sc);
3530 break;
3531 default:
3532 break;
3533 }
3534 }
3535
3536 static void
saf1761_otg_device_resume(struct usb_device * udev)3537 saf1761_otg_device_resume(struct usb_device *udev)
3538 {
3539 struct saf1761_otg_softc *sc;
3540 struct saf1761_otg_td *td;
3541 struct usb_xfer *xfer;
3542 uint8_t x;
3543
3544 DPRINTF("\n");
3545
3546 if (udev->flags.usb_mode != USB_MODE_HOST)
3547 return;
3548
3549 sc = SAF1761_OTG_BUS2SC(udev->bus);
3550
3551 USB_BUS_LOCK(&sc->sc_bus);
3552 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3553
3554 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3555 if (xfer->xroot->udev != udev)
3556 continue;
3557
3558 td = xfer->td_transfer_cache;
3559 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3560 continue;
3561
3562 switch (td->ep_type) {
3563 case UE_INTERRUPT:
3564 x = td->channel - 32;
3565 sc->sc_host_intr_suspend_map &= ~(1U << x);
3566 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3567 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3568 break;
3569 case UE_ISOCHRONOUS:
3570 x = td->channel;
3571 sc->sc_host_isoc_suspend_map &= ~(1U << x);
3572 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3573 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3574 break;
3575 default:
3576 x = td->channel - 64;
3577 sc->sc_host_async_suspend_map &= ~(1U << x);
3578 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3579 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3580 break;
3581 }
3582 }
3583
3584 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3585 USB_BUS_UNLOCK(&sc->sc_bus);
3586
3587 /* poll all transfers again to restart resumed ones */
3588 saf1761_otg_do_poll(&sc->sc_bus);
3589 }
3590
3591 static void
saf1761_otg_device_suspend(struct usb_device * udev)3592 saf1761_otg_device_suspend(struct usb_device *udev)
3593 {
3594 struct saf1761_otg_softc *sc;
3595 struct saf1761_otg_td *td;
3596 struct usb_xfer *xfer;
3597 uint8_t x;
3598
3599 DPRINTF("\n");
3600
3601 if (udev->flags.usb_mode != USB_MODE_HOST)
3602 return;
3603
3604 sc = SAF1761_OTG_BUS2SC(udev->bus);
3605
3606 USB_BUS_LOCK(&sc->sc_bus);
3607 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3608
3609 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3610 if (xfer->xroot->udev != udev)
3611 continue;
3612
3613 td = xfer->td_transfer_cache;
3614 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3615 continue;
3616
3617 switch (td->ep_type) {
3618 case UE_INTERRUPT:
3619 x = td->channel - 32;
3620 sc->sc_host_intr_suspend_map |= (1U << x);
3621 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3622 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3623 break;
3624 case UE_ISOCHRONOUS:
3625 x = td->channel;
3626 sc->sc_host_isoc_suspend_map |= (1U << x);
3627 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3628 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3629 break;
3630 default:
3631 x = td->channel - 64;
3632 sc->sc_host_async_suspend_map |= (1U << x);
3633 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3634 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3635 break;
3636 }
3637 }
3638
3639 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3640 USB_BUS_UNLOCK(&sc->sc_bus);
3641 }
3642
3643 static const struct usb_bus_methods saf1761_otg_bus_methods =
3644 {
3645 .endpoint_init = &saf1761_otg_ep_init,
3646 .xfer_setup = &saf1761_otg_xfer_setup,
3647 .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3648 .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3649 .xfer_stall = &saf1761_otg_xfer_stall,
3650 .set_stall = &saf1761_otg_set_stall,
3651 .clear_stall = &saf1761_otg_clear_stall,
3652 .roothub_exec = &saf1761_otg_roothub_exec,
3653 .xfer_poll = &saf1761_otg_do_poll,
3654 .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3655 .device_resume = &saf1761_otg_device_resume,
3656 .device_suspend = &saf1761_otg_device_suspend,
3657 };
3658