1 /* $FreeBSD$ */
2 /*-
3 * Copyright (c) 2014 Hans Petter Selasky <[email protected]>
4 * All rights reserved.
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /*
33 * This file contains the driver for the SAF1761 series USB OTG
34 * controller.
35 *
36 * Datasheet is available from:
37 * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
38 */
39
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
42 #else
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/bus.h>
51 #include <sys/module.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
56 #include <sys/sx.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
60 #include <sys/priv.h>
61 #include <sys/libkern.h>
62
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
65
66 #define USB_DEBUG_VAR saf1761_otg_debug
67
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
76
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #endif /* USB_GLOBAL_INCLUDE_FILE */
80
81 #include <dev/usb/controller/saf1761_otg.h>
82 #include <dev/usb/controller/saf1761_otg_reg.h>
83
84 #define SAF1761_OTG_BUS2SC(bus) \
85 ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
86 ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
87
88 #define SAF1761_OTG_PC2UDEV(pc) \
89 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
90
91 #define SAF1761_DCINTERRUPT_THREAD_IRQ \
92 (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST | \
93 SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
94
95 #ifdef USB_DEBUG
96 static int saf1761_otg_debug = 0;
97 static int saf1761_otg_forcefs = 0;
98
99 static
100 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
101 "USB SAF1761 DCI");
102
103 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
104 &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
105 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RWTUN,
106 &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
107 #endif
108
109 #define SAF1761_OTG_INTR_ENDPT 1
110
111 /* prototypes */
112
113 static const struct usb_bus_methods saf1761_otg_bus_methods;
114 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
115 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
116 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods;
117
118 static saf1761_otg_cmd_t saf1761_host_setup_tx;
119 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
120 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
121 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
122 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
123 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
124 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
125 static saf1761_otg_cmd_t saf1761_device_setup_rx;
126 static saf1761_otg_cmd_t saf1761_device_data_rx;
127 static saf1761_otg_cmd_t saf1761_device_data_tx;
128 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
129 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
130 static void saf1761_otg_do_poll(struct usb_bus *);
131 static void saf1761_otg_standard_done(struct usb_xfer *);
132 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
133 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
134 static void saf1761_otg_enable_psof(struct saf1761_otg_softc *, uint8_t);
135
136 /*
137 * Here is a list of what the SAF1761 chip can support. The main
138 * limitation is that the sum of the buffer sizes must be less than
139 * 8192 bytes.
140 */
141 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
142
143 [0] = {
144 .max_in_frame_size = 64,
145 .max_out_frame_size = 64,
146 .is_simplex = 0,
147 .support_control = 1,
148 },
149 [1] = {
150 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
151 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
152 .is_simplex = 0,
153 .support_interrupt = 1,
154 .support_bulk = 1,
155 .support_isochronous = 1,
156 .support_in = 1,
157 .support_out = 1,
158 },
159 };
160
161 static void
saf1761_otg_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)162 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
163 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
164 {
165 if (ep_addr == 0) {
166 *ppf = saf1761_otg_ep_profile + 0;
167 } else if (ep_addr < 8) {
168 *ppf = saf1761_otg_ep_profile + 1;
169 } else {
170 *ppf = NULL;
171 }
172 }
173
174 static void
saf1761_otg_pull_up(struct saf1761_otg_softc * sc)175 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
176 {
177 /* activate pullup on D+, if possible */
178
179 if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
180 DPRINTF("\n");
181
182 sc->sc_flags.d_pulled_up = 1;
183 }
184 }
185
186 static void
saf1761_otg_pull_down(struct saf1761_otg_softc * sc)187 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
188 {
189 /* release pullup on D+, if possible */
190
191 if (sc->sc_flags.d_pulled_up) {
192 DPRINTF("\n");
193
194 sc->sc_flags.d_pulled_up = 0;
195 }
196 }
197
198 static void
saf1761_otg_wakeup_peer(struct saf1761_otg_softc * sc)199 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
200 {
201 uint16_t temp;
202
203 if (!(sc->sc_flags.status_suspend))
204 return;
205
206 DPRINTFN(5, "\n");
207
208 temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
209 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
210 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
211
212 /* Wait 8ms for remote wakeup to complete. */
213 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
214 }
215
216 static uint8_t
saf1761_host_channel_alloc(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)217 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
218 {
219 uint32_t map;
220 int x;
221
222 if (td->channel < SOTG_HOST_CHANNEL_MAX)
223 return (0);
224
225 /* check if device is suspended */
226 if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
227 return (1); /* busy - cannot transfer data */
228
229 switch (td->ep_type) {
230 case UE_INTERRUPT:
231 map = ~(sc->sc_host_intr_map |
232 sc->sc_host_intr_busy_map[0] |
233 sc->sc_host_intr_busy_map[1]);
234 /* find first set bit */
235 x = ffs(map) - 1;
236 if (x < 0 || x > 31)
237 break;
238 sc->sc_host_intr_map |= (1U << x);
239 td->channel = 32 + x;
240 return (0);
241 case UE_ISOCHRONOUS:
242 map = ~(sc->sc_host_isoc_map |
243 sc->sc_host_isoc_busy_map[0] |
244 sc->sc_host_isoc_busy_map[1]);
245 /* find first set bit */
246 x = ffs(map) - 1;
247 if (x < 0 || x > 31)
248 break;
249 sc->sc_host_isoc_map |= (1U << x);
250 td->channel = x;
251 return (0);
252 default:
253 map = ~(sc->sc_host_async_map |
254 sc->sc_host_async_busy_map[0] |
255 sc->sc_host_async_busy_map[1]);
256 /* find first set bit */
257 x = ffs(map) - 1;
258 if (x < 0 || x > 31)
259 break;
260 sc->sc_host_async_map |= (1U << x);
261 td->channel = 64 + x;
262 return (0);
263 }
264 return (1);
265 }
266
267 static void
saf1761_host_channel_free(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)268 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
269 {
270 uint32_t x;
271
272 if (td->channel >= SOTG_HOST_CHANNEL_MAX)
273 return;
274
275 switch (td->ep_type) {
276 case UE_INTERRUPT:
277 x = td->channel - 32;
278 td->channel = SOTG_HOST_CHANNEL_MAX;
279 sc->sc_host_intr_map &= ~(1U << x);
280 sc->sc_host_intr_suspend_map &= ~(1U << x);
281 sc->sc_host_intr_busy_map[0] |= (1U << x);
282 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
283 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
284 break;
285 case UE_ISOCHRONOUS:
286 x = td->channel;
287 td->channel = SOTG_HOST_CHANNEL_MAX;
288 sc->sc_host_isoc_map &= ~(1U << x);
289 sc->sc_host_isoc_suspend_map &= ~(1U << x);
290 sc->sc_host_isoc_busy_map[0] |= (1U << x);
291 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
292 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
293 break;
294 default:
295 x = td->channel - 64;
296 td->channel = SOTG_HOST_CHANNEL_MAX;
297 sc->sc_host_async_map &= ~(1U << x);
298 sc->sc_host_async_suspend_map &= ~(1U << x);
299 sc->sc_host_async_busy_map[0] |= (1U << x);
300 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
301 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
302 break;
303 }
304 saf1761_otg_enable_psof(sc, 1);
305 }
306
307 static uint32_t
saf1761_peek_host_status_le_4(struct saf1761_otg_softc * sc,uint32_t offset)308 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
309 {
310 uint32_t x = 0;
311 while (1) {
312 uint32_t retval;
313
314 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
315 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
316 retval = SAF1761_READ_LE_4(sc, offset);
317 if (retval != 0)
318 return (retval);
319 if (++x == 8) {
320 DPRINTF("STAUS is zero at offset 0x%x\n", offset);
321 break;
322 }
323 }
324 return (0);
325 }
326
327 static void
saf1761_read_host_memory(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)328 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
329 struct saf1761_otg_td *td, uint32_t len)
330 {
331 struct usb_page_search buf_res;
332 uint32_t offset;
333 uint32_t count;
334
335 if (len == 0)
336 return;
337
338 offset = SOTG_DATA_ADDR(td->channel);
339 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
340 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
341
342 /* optimised read first */
343 while (len > 0) {
344 usbd_get_page(td->pc, td->offset, &buf_res);
345
346 /* get correct length */
347 if (buf_res.length > len)
348 buf_res.length = len;
349
350 /* check buffer alignment */
351 if (((uintptr_t)buf_res.buffer) & 3)
352 break;
353
354 count = buf_res.length & ~3;
355 if (count == 0)
356 break;
357
358 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
359 offset, buf_res.buffer, count / 4);
360
361 len -= count;
362 offset += count;
363
364 /* update remainder and offset */
365 td->remainder -= count;
366 td->offset += count;
367 }
368
369 if (len > 0) {
370 /* use bounce buffer */
371 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
372 offset, sc->sc_bounce_buffer, (len + 3) / 4);
373 usbd_copy_in(td->pc, td->offset,
374 sc->sc_bounce_buffer, len);
375
376 /* update remainder and offset */
377 td->remainder -= len;
378 td->offset += len;
379 }
380 }
381
382 static void
saf1761_write_host_memory(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)383 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
384 struct saf1761_otg_td *td, uint32_t len)
385 {
386 struct usb_page_search buf_res;
387 uint32_t offset;
388 uint32_t count;
389
390 if (len == 0)
391 return;
392
393 offset = SOTG_DATA_ADDR(td->channel);
394
395 /* optimised write first */
396 while (len > 0) {
397 usbd_get_page(td->pc, td->offset, &buf_res);
398
399 /* get correct length */
400 if (buf_res.length > len)
401 buf_res.length = len;
402
403 /* check buffer alignment */
404 if (((uintptr_t)buf_res.buffer) & 3)
405 break;
406
407 count = buf_res.length & ~3;
408 if (count == 0)
409 break;
410
411 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
412 offset, buf_res.buffer, count / 4);
413
414 len -= count;
415 offset += count;
416
417 /* update remainder and offset */
418 td->remainder -= count;
419 td->offset += count;
420 }
421 if (len > 0) {
422 /* use bounce buffer */
423 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
424 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
425 offset, sc->sc_bounce_buffer, (len + 3) / 4);
426
427 /* update remainder and offset */
428 td->remainder -= len;
429 td->offset += len;
430 }
431 }
432
433 static uint8_t
saf1761_host_setup_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)434 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
435 {
436 uint32_t pdt_addr;
437 uint32_t status;
438 uint32_t count;
439 uint32_t temp;
440
441 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
442 pdt_addr = SOTG_PTD(td->channel);
443
444 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
445
446 DPRINTFN(5, "STATUS=0x%08x\n", status);
447
448 if (status & SOTG_PTD_DW3_ACTIVE) {
449 goto busy;
450 } else if (status & SOTG_PTD_DW3_HALTED) {
451 td->error_any = 1;
452 }
453 goto complete;
454 }
455 if (saf1761_host_channel_alloc(sc, td))
456 goto busy;
457
458 count = 8;
459
460 if (count != td->remainder) {
461 td->error_any = 1;
462 goto complete;
463 }
464
465 saf1761_write_host_memory(sc, td, count);
466
467 pdt_addr = SOTG_PTD(td->channel);
468
469 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
470 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
471 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
472 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
473
474 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
475 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
476
477 temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
478 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
479
480 temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
481 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
482
483 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
484 (td->max_packet_size << 18) /* wMaxPacketSize */ |
485 (count << 3) /* transfer count */ |
486 SOTG_PTD_DW0_VALID;
487 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
488
489 /* activate PTD */
490 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
491 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
492
493 td->toggle = 1;
494 busy:
495 return (1); /* busy */
496 complete:
497 saf1761_host_channel_free(sc, td);
498 return (0); /* complete */
499 }
500
501 static uint8_t
saf1761_host_bulk_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)502 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
503 {
504 uint32_t pdt_addr;
505 uint32_t temp;
506
507 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
508 uint32_t status;
509 uint32_t count;
510 uint8_t got_short;
511
512 pdt_addr = SOTG_PTD(td->channel);
513
514 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
515
516 DPRINTFN(5, "STATUS=0x%08x\n", status);
517
518 if (status & SOTG_PTD_DW3_ACTIVE) {
519 temp = saf1761_peek_host_status_le_4(sc,
520 pdt_addr + SOTG_PTD_DW0);
521 if (temp & SOTG_PTD_DW0_VALID) {
522 goto busy;
523 } else {
524 status = saf1761_peek_host_status_le_4(sc,
525 pdt_addr + SOTG_PTD_DW3);
526
527 /* check if still active */
528 if (status & SOTG_PTD_DW3_ACTIVE) {
529 saf1761_host_channel_free(sc, td);
530 goto retry;
531 } else if (status & SOTG_PTD_DW3_HALTED) {
532 if (!(status & SOTG_PTD_DW3_ERRORS))
533 td->error_stall = 1;
534 td->error_any = 1;
535 goto complete;
536 }
537 }
538 } else if (status & SOTG_PTD_DW3_HALTED) {
539 if (!(status & SOTG_PTD_DW3_ERRORS))
540 td->error_stall = 1;
541 td->error_any = 1;
542 goto complete;
543 }
544 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
545 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
546 else
547 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
548 got_short = 0;
549
550 /* verify the packet byte count */
551 if (count != td->max_packet_size) {
552 if (count < td->max_packet_size) {
553 /* we have a short packet */
554 td->short_pkt = 1;
555 got_short = 1;
556 } else {
557 /* invalid USB packet */
558 td->error_any = 1;
559 goto complete;
560 }
561 }
562 td->toggle ^= 1;
563
564 /* verify the packet byte count */
565 if (count > td->remainder) {
566 /* invalid USB packet */
567 td->error_any = 1;
568 goto complete;
569 }
570
571 saf1761_read_host_memory(sc, td, count);
572
573 /* check if we are complete */
574 if ((td->remainder == 0) || got_short) {
575 if (td->short_pkt)
576 goto complete;
577 /* else need to receive a zero length packet */
578 }
579 saf1761_host_channel_free(sc, td);
580 }
581 retry:
582 if (saf1761_host_channel_alloc(sc, td))
583 goto busy;
584
585 /* set toggle, if any */
586 if (td->set_toggle) {
587 td->set_toggle = 0;
588 td->toggle = 1;
589 }
590
591 /* receive one more packet */
592
593 pdt_addr = SOTG_PTD(td->channel);
594
595 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
596 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
597 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
598 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
599
600 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
601 SOTG_PTD_DW3_CERR_2;
602 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
603
604 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
605 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
606
607 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
608 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
609
610 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
611 (td->max_packet_size << 18) /* wMaxPacketSize */ |
612 (td->max_packet_size << 3) /* transfer count */ |
613 SOTG_PTD_DW0_VALID;
614 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
615
616 /* activate PTD */
617 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
618 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
619 busy:
620 return (1); /* busy */
621 complete:
622 saf1761_host_channel_free(sc, td);
623 return (0); /* complete */
624 }
625
626 static uint8_t
saf1761_host_bulk_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)627 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
628 {
629 uint32_t pdt_addr;
630 uint32_t temp;
631 uint32_t count;
632
633 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
634 uint32_t status;
635
636 pdt_addr = SOTG_PTD(td->channel);
637
638 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
639
640 DPRINTFN(5, "STATUS=0x%08x\n", status);
641
642 if (status & SOTG_PTD_DW3_ACTIVE) {
643 goto busy;
644 } else if (status & SOTG_PTD_DW3_HALTED) {
645 if (!(status & SOTG_PTD_DW3_ERRORS))
646 td->error_stall = 1;
647 td->error_any = 1;
648 goto complete;
649 }
650 /* check remainder */
651 if (td->remainder == 0) {
652 if (td->short_pkt)
653 goto complete;
654 /* else we need to transmit a short packet */
655 }
656 saf1761_host_channel_free(sc, td);
657 }
658 if (saf1761_host_channel_alloc(sc, td))
659 goto busy;
660
661 count = td->max_packet_size;
662 if (td->remainder < count) {
663 /* we have a short packet */
664 td->short_pkt = 1;
665 count = td->remainder;
666 }
667
668 saf1761_write_host_memory(sc, td, count);
669
670 /* set toggle, if any */
671 if (td->set_toggle) {
672 td->set_toggle = 0;
673 td->toggle = 1;
674 }
675
676 /* send one more packet */
677
678 pdt_addr = SOTG_PTD(td->channel);
679
680 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
681 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
682 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
683 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
684
685 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
686 SOTG_PTD_DW3_CERR_2;
687 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
688
689 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
690 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
691
692 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
693 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
694
695 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
696 (td->max_packet_size << 18) /* wMaxPacketSize */ |
697 (count << 3) /* transfer count */ |
698 SOTG_PTD_DW0_VALID;
699 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
700
701 /* activate PTD */
702 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
703 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
704
705 td->toggle ^= 1;
706 busy:
707 return (1); /* busy */
708 complete:
709 saf1761_host_channel_free(sc, td);
710 return (0); /* complete */
711 }
712
713 static uint8_t
saf1761_host_intr_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)714 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
715 {
716 uint32_t pdt_addr;
717 uint32_t temp;
718
719 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
720 uint32_t status;
721 uint32_t count;
722 uint8_t got_short;
723
724 pdt_addr = SOTG_PTD(td->channel);
725
726 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
727
728 DPRINTFN(5, "STATUS=0x%08x\n", status);
729
730 if (status & SOTG_PTD_DW3_ACTIVE) {
731 goto busy;
732 } else if (status & SOTG_PTD_DW3_HALTED) {
733 if (!(status & SOTG_PTD_DW3_ERRORS))
734 td->error_stall = 1;
735 td->error_any = 1;
736 goto complete;
737 }
738 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
739 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
740 else
741 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
742 got_short = 0;
743
744 /* verify the packet byte count */
745 if (count != td->max_packet_size) {
746 if (count < td->max_packet_size) {
747 /* we have a short packet */
748 td->short_pkt = 1;
749 got_short = 1;
750 } else {
751 /* invalid USB packet */
752 td->error_any = 1;
753 goto complete;
754 }
755 }
756 td->toggle ^= 1;
757
758 /* verify the packet byte count */
759 if (count > td->remainder) {
760 /* invalid USB packet */
761 td->error_any = 1;
762 goto complete;
763 }
764
765 saf1761_read_host_memory(sc, td, count);
766
767 /* check if we are complete */
768 if ((td->remainder == 0) || got_short) {
769 if (td->short_pkt)
770 goto complete;
771 /* else need to receive a zero length packet */
772 }
773 saf1761_host_channel_free(sc, td);
774 }
775 if (saf1761_host_channel_alloc(sc, td))
776 goto busy;
777
778 /* set toggle, if any */
779 if (td->set_toggle) {
780 td->set_toggle = 0;
781 td->toggle = 1;
782 }
783
784 /* receive one more packet */
785
786 pdt_addr = SOTG_PTD(td->channel);
787
788 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
789 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
790
791 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
792 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
793 } else {
794 temp = 0;
795 }
796 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
797
798 temp = (1U << td->uframe); /* start mask or start split */
799 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
800
801 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
802 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
803
804 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
805 (td->interval & 0xF8);
806 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
807
808 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
809 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
810
811 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
812 (td->max_packet_size << 18) /* wMaxPacketSize */ |
813 (td->max_packet_size << 3) /* transfer count */ |
814 SOTG_PTD_DW0_VALID;
815 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
816
817 /* activate PTD */
818 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
819 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
820 busy:
821 return (1); /* busy */
822 complete:
823 saf1761_host_channel_free(sc, td);
824 return (0); /* complete */
825 }
826
827 static uint8_t
saf1761_host_intr_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)828 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
829 {
830 uint32_t pdt_addr;
831 uint32_t temp;
832 uint32_t count;
833
834 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
835 uint32_t status;
836
837 pdt_addr = SOTG_PTD(td->channel);
838
839 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
840
841 DPRINTFN(5, "STATUS=0x%08x\n", status);
842
843 if (status & SOTG_PTD_DW3_ACTIVE) {
844 goto busy;
845 } else if (status & SOTG_PTD_DW3_HALTED) {
846 if (!(status & SOTG_PTD_DW3_ERRORS))
847 td->error_stall = 1;
848 td->error_any = 1;
849 goto complete;
850 }
851
852 /* check remainder */
853 if (td->remainder == 0) {
854 if (td->short_pkt)
855 goto complete;
856 /* else we need to transmit a short packet */
857 }
858 saf1761_host_channel_free(sc, td);
859 }
860 if (saf1761_host_channel_alloc(sc, td))
861 goto busy;
862
863 count = td->max_packet_size;
864 if (td->remainder < count) {
865 /* we have a short packet */
866 td->short_pkt = 1;
867 count = td->remainder;
868 }
869
870 saf1761_write_host_memory(sc, td, count);
871
872 /* set toggle, if any */
873 if (td->set_toggle) {
874 td->set_toggle = 0;
875 td->toggle = 1;
876 }
877
878 /* send one more packet */
879
880 pdt_addr = SOTG_PTD(td->channel);
881
882 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
883 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
884
885 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
886 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
887 } else {
888 temp = 0;
889 }
890 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
891
892 temp = (1U << td->uframe); /* start mask or start split */
893 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
894
895 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
896 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
897
898 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
899 (td->interval & 0xF8);
900 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
901
902 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
903 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
904
905 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
906 (td->max_packet_size << 18) /* wMaxPacketSize */ |
907 (count << 3) /* transfer count */ |
908 SOTG_PTD_DW0_VALID;
909 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
910
911 /* activate PTD */
912 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
913 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
914
915 td->toggle ^= 1;
916 busy:
917 return (1); /* busy */
918 complete:
919 saf1761_host_channel_free(sc, td);
920 return (0); /* complete */
921 }
922
923 static uint8_t
saf1761_host_isoc_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)924 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
925 {
926 uint32_t pdt_addr;
927 uint32_t temp;
928
929 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
930 uint32_t status;
931 uint32_t count;
932
933 pdt_addr = SOTG_PTD(td->channel);
934
935 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
936
937 DPRINTFN(5, "STATUS=0x%08x\n", status);
938
939 if (status & SOTG_PTD_DW3_ACTIVE) {
940 goto busy;
941 } else if (status & SOTG_PTD_DW3_HALTED) {
942 goto complete;
943 }
944 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
945 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
946 else
947 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
948
949 /* verify the packet byte count */
950 if (count != td->max_packet_size) {
951 if (count < td->max_packet_size) {
952 /* we have a short packet */
953 td->short_pkt = 1;
954 } else {
955 /* invalid USB packet */
956 td->error_any = 1;
957 goto complete;
958 }
959 }
960
961 /* verify the packet byte count */
962 if (count > td->remainder) {
963 /* invalid USB packet */
964 td->error_any = 1;
965 goto complete;
966 }
967
968 saf1761_read_host_memory(sc, td, count);
969 goto complete;
970 }
971
972 if (saf1761_host_channel_alloc(sc, td))
973 goto busy;
974
975 /* receive one more packet */
976
977 pdt_addr = SOTG_PTD(td->channel);
978
979 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
980 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
981
982 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
983 temp = (0xFC << (td->uframe & 7)) & 0xFF; /* complete split */
984 } else {
985 temp = 0;
986 }
987 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
988
989 temp = (1U << (td->uframe & 7)); /* start mask or start split */
990 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
991
992 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
993 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
994
995 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
996 (td->uframe & 0xF8);
997 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
998
999 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
1000 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1001
1002 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1003 (td->max_packet_size << 18) /* wMaxPacketSize */ |
1004 (td->max_packet_size << 3) /* transfer count */ |
1005 SOTG_PTD_DW0_VALID;
1006 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1007
1008 /* activate PTD */
1009 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1010 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1011 busy:
1012 return (1); /* busy */
1013 complete:
1014 saf1761_host_channel_free(sc, td);
1015 return (0); /* complete */
1016 }
1017
1018 static uint8_t
saf1761_host_isoc_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1019 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1020 {
1021 uint32_t pdt_addr;
1022 uint32_t temp;
1023 uint32_t count;
1024
1025 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
1026 uint32_t status;
1027
1028 pdt_addr = SOTG_PTD(td->channel);
1029
1030 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
1031
1032 DPRINTFN(5, "STATUS=0x%08x\n", status);
1033
1034 if (status & SOTG_PTD_DW3_ACTIVE) {
1035 goto busy;
1036 } else if (status & SOTG_PTD_DW3_HALTED) {
1037 goto complete;
1038 }
1039 goto complete;
1040 }
1041 if (saf1761_host_channel_alloc(sc, td))
1042 goto busy;
1043
1044 count = td->max_packet_size;
1045 if (td->remainder < count) {
1046 /* we have a short packet */
1047 td->short_pkt = 1;
1048 count = td->remainder;
1049 }
1050
1051 saf1761_write_host_memory(sc, td, count);
1052
1053 /* send one more packet */
1054
1055 pdt_addr = SOTG_PTD(td->channel);
1056
1057 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
1058 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
1059 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
1060
1061 temp = (1U << (td->uframe & 7)); /* start mask or start split */
1062 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
1063
1064 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
1065 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
1066
1067 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
1068 (td->uframe & 0xF8);
1069 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
1070
1071 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
1072 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1073
1074 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1075 (count << 18) /* wMaxPacketSize */ |
1076 (count << 3) /* transfer count */ |
1077 SOTG_PTD_DW0_VALID;
1078 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1079
1080 /* activate PTD */
1081 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1082 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1083 busy:
1084 return (1); /* busy */
1085 complete:
1086 saf1761_host_channel_free(sc, td);
1087 return (0); /* complete */
1088 }
1089
1090 static void
saf1761_otg_set_address(struct saf1761_otg_softc * sc,uint8_t addr)1091 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
1092 {
1093 DPRINTFN(5, "addr=%d\n", addr);
1094
1095 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
1096 }
1097
1098
1099 static void
saf1761_read_device_fifo(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)1100 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
1101 struct saf1761_otg_td *td, uint32_t len)
1102 {
1103 struct usb_page_search buf_res;
1104 uint32_t count;
1105
1106 /* optimised read first */
1107 while (len > 0) {
1108 usbd_get_page(td->pc, td->offset, &buf_res);
1109
1110 /* get correct length */
1111 if (buf_res.length > len)
1112 buf_res.length = len;
1113
1114 /* check buffer alignment */
1115 if (((uintptr_t)buf_res.buffer) & 3)
1116 break;
1117
1118 count = buf_res.length & ~3;
1119 if (count == 0)
1120 break;
1121
1122 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1123 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1124
1125 len -= count;
1126
1127 /* update remainder and offset */
1128 td->remainder -= count;
1129 td->offset += count;
1130 }
1131
1132 if (len > 0) {
1133 /* use bounce buffer */
1134 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1135 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1136 usbd_copy_in(td->pc, td->offset,
1137 sc->sc_bounce_buffer, len);
1138
1139 /* update remainder and offset */
1140 td->remainder -= len;
1141 td->offset += len;
1142 }
1143 }
1144
1145 static void
saf1761_write_device_fifo(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td,uint32_t len)1146 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
1147 struct saf1761_otg_td *td, uint32_t len)
1148 {
1149 struct usb_page_search buf_res;
1150 uint32_t count;
1151
1152 /* optimised write first */
1153 while (len > 0) {
1154 usbd_get_page(td->pc, td->offset, &buf_res);
1155
1156 /* get correct length */
1157 if (buf_res.length > len)
1158 buf_res.length = len;
1159
1160 /* check buffer alignment */
1161 if (((uintptr_t)buf_res.buffer) & 3)
1162 break;
1163
1164 count = buf_res.length & ~3;
1165 if (count == 0)
1166 break;
1167
1168 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1169 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1170
1171 len -= count;
1172
1173 /* update remainder and offset */
1174 td->remainder -= count;
1175 td->offset += count;
1176 }
1177 if (len > 0) {
1178 /* use bounce buffer */
1179 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
1180 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1181 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1182
1183 /* update remainder and offset */
1184 td->remainder -= len;
1185 td->offset += len;
1186 }
1187 }
1188
1189 static uint8_t
saf1761_device_setup_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1190 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1191 {
1192 struct usb_device_request req;
1193 uint32_t count;
1194
1195 /* select the correct endpoint */
1196 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1197
1198 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1199
1200 /* check buffer status */
1201 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1202 goto busy;
1203
1204 /* get buffer length */
1205 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1206
1207 DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1208
1209 /* clear did stall */
1210 td->did_stall = 0;
1211
1212 /* clear stall */
1213 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1214
1215 /* verify data length */
1216 if (count != td->remainder) {
1217 DPRINTFN(0, "Invalid SETUP packet "
1218 "length, %d bytes\n", count);
1219 goto busy;
1220 }
1221 if (count != sizeof(req)) {
1222 DPRINTFN(0, "Unsupported SETUP packet "
1223 "length, %d bytes\n", count);
1224 goto busy;
1225 }
1226 /* receive data */
1227 saf1761_read_device_fifo(sc, td, sizeof(req));
1228
1229 /* extract SETUP packet again */
1230 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1231
1232 /* sneak peek the set address request */
1233 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1234 (req.bRequest == UR_SET_ADDRESS)) {
1235 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1236 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1237 } else {
1238 sc->sc_dv_addr = 0xFF;
1239 }
1240 return (0); /* complete */
1241
1242 busy:
1243 /* abort any ongoing transfer */
1244 if (!td->did_stall) {
1245 DPRINTFN(5, "stalling\n");
1246
1247 /* set stall */
1248 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1249
1250 td->did_stall = 1;
1251 }
1252 return (1); /* not complete */
1253 }
1254
1255 static uint8_t
saf1761_device_data_rx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1256 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1257 {
1258 uint32_t count;
1259 uint8_t got_short = 0;
1260
1261 if (td->ep_index == 0) {
1262 /* select the correct endpoint */
1263 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1264
1265 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1266
1267 /* check buffer status */
1268 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1269
1270 if (td->remainder == 0) {
1271 /*
1272 * We are actually complete and have
1273 * received the next SETUP:
1274 */
1275 DPRINTFN(5, "faking complete\n");
1276 return (0); /* complete */
1277 }
1278 DPRINTFN(5, "SETUP packet while receiving data\n");
1279 /*
1280 * USB Host Aborted the transfer.
1281 */
1282 td->error_any = 1;
1283 return (0); /* complete */
1284 }
1285 }
1286 /* select the correct endpoint */
1287 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1288 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1289 SOTG_EP_INDEX_DIR_OUT);
1290
1291 /* enable data stage */
1292 if (td->set_toggle) {
1293 td->set_toggle = 0;
1294 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1295 }
1296
1297 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1298
1299 /* check buffer status */
1300 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1301 return (1); /* not complete */
1302
1303 /* get buffer length */
1304 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1305
1306 DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1307
1308 /* verify the packet byte count */
1309 if (count != td->max_packet_size) {
1310 if (count < td->max_packet_size) {
1311 /* we have a short packet */
1312 td->short_pkt = 1;
1313 got_short = 1;
1314 } else {
1315 /* invalid USB packet */
1316 td->error_any = 1;
1317 return (0); /* we are complete */
1318 }
1319 }
1320 /* verify the packet byte count */
1321 if (count > td->remainder) {
1322 /* invalid USB packet */
1323 td->error_any = 1;
1324 return (0); /* we are complete */
1325 }
1326 /* receive data */
1327 saf1761_read_device_fifo(sc, td, count);
1328
1329 /* check if we are complete */
1330 if ((td->remainder == 0) || got_short) {
1331 if (td->short_pkt) {
1332 /* we are complete */
1333 return (0);
1334 }
1335 /* else need to receive a zero length packet */
1336 }
1337 return (1); /* not complete */
1338 }
1339
1340 static uint8_t
saf1761_device_data_tx(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1341 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1342 {
1343 uint32_t count;
1344
1345 if (td->ep_index == 0) {
1346 /* select the correct endpoint */
1347 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1348
1349 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1350
1351 /* check buffer status */
1352 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1353 DPRINTFN(5, "SETUP abort\n");
1354 /*
1355 * USB Host Aborted the transfer.
1356 */
1357 td->error_any = 1;
1358 return (0); /* complete */
1359 }
1360 }
1361 /* select the correct endpoint */
1362 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1363 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1364 SOTG_EP_INDEX_DIR_IN);
1365
1366 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1367
1368 /* check buffer status */
1369 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1370 return (1); /* not complete */
1371
1372 /* enable data stage */
1373 if (td->set_toggle) {
1374 td->set_toggle = 0;
1375 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1376 }
1377
1378 DPRINTFN(5, "rem=%u\n", td->remainder);
1379
1380 count = td->max_packet_size;
1381 if (td->remainder < count) {
1382 /* we have a short packet */
1383 td->short_pkt = 1;
1384 count = td->remainder;
1385 }
1386 /* transmit data */
1387 saf1761_write_device_fifo(sc, td, count);
1388
1389 if (td->ep_index == 0) {
1390 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1391 /* set end of packet */
1392 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1393 }
1394 } else {
1395 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1396 /* set end of packet */
1397 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1398 }
1399 }
1400
1401 /* check remainder */
1402 if (td->remainder == 0) {
1403 if (td->short_pkt) {
1404 return (0); /* complete */
1405 }
1406 /* else we need to transmit a short packet */
1407 }
1408 return (1); /* not complete */
1409 }
1410
1411 static uint8_t
saf1761_device_data_tx_sync(struct saf1761_otg_softc * sc,struct saf1761_otg_td * td)1412 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1413 {
1414 uint32_t count;
1415
1416 if (td->ep_index == 0) {
1417 /* select the correct endpoint */
1418 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1419
1420 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1421
1422 /* check buffer status */
1423 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1424 DPRINTFN(5, "Faking complete\n");
1425 return (0); /* complete */
1426 }
1427 }
1428 /* select the correct endpoint */
1429 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1430 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1431 SOTG_EP_INDEX_DIR_IN);
1432
1433 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1434
1435 /* check buffer status */
1436 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1437 return (1); /* busy */
1438
1439 if (sc->sc_dv_addr != 0xFF) {
1440 /* write function address */
1441 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1442 }
1443 return (0); /* complete */
1444 }
1445
1446 static void
saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc * sc,struct usb_xfer * xfer)1447 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1448 {
1449 struct saf1761_otg_td *td;
1450 uint8_t toggle;
1451
1452 DPRINTFN(9, "\n");
1453
1454 td = xfer->td_transfer_cache;
1455 if (td == NULL)
1456 return;
1457
1458 while (1) {
1459 if ((td->func) (sc, td)) {
1460 /* operation in progress */
1461 break;
1462 }
1463 if (((void *)td) == xfer->td_transfer_last) {
1464 goto done;
1465 }
1466 if (td->error_any) {
1467 goto done;
1468 } else if (td->remainder > 0) {
1469 /*
1470 * We had a short transfer. If there is no alternate
1471 * next, stop processing !
1472 */
1473 if (!td->alt_next) {
1474 goto done;
1475 }
1476 }
1477 /*
1478 * Fetch the next transfer descriptor.
1479 */
1480 toggle = td->toggle;
1481 td = td->obj_next;
1482 td->toggle = toggle;
1483 xfer->td_transfer_cache = td;
1484 }
1485 return;
1486
1487 done:
1488 /* compute all actual lengths */
1489 xfer->td_transfer_cache = NULL;
1490 sc->sc_xfer_complete = 1;
1491 }
1492
1493 static uint8_t
saf1761_otg_xfer_do_complete(struct saf1761_otg_softc * sc,struct usb_xfer * xfer)1494 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1495 {
1496 struct saf1761_otg_td *td;
1497
1498 DPRINTFN(9, "\n");
1499
1500 td = xfer->td_transfer_cache;
1501 if (td == NULL) {
1502 /* compute all actual lengths */
1503 saf1761_otg_standard_done(xfer);
1504 return (1);
1505 }
1506 return (0);
1507 }
1508
1509 static void
saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc * sc)1510 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1511 {
1512 struct usb_xfer *xfer;
1513
1514 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1515 saf1761_otg_xfer_do_fifo(sc, xfer);
1516 }
1517
1518 static void
saf1761_otg_enable_psof(struct saf1761_otg_softc * sc,uint8_t on)1519 saf1761_otg_enable_psof(struct saf1761_otg_softc *sc, uint8_t on)
1520 {
1521 if (on) {
1522 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IEPSOF;
1523 } else {
1524 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IEPSOF;
1525 }
1526 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1527 }
1528
1529 static void
saf1761_otg_wait_suspend(struct saf1761_otg_softc * sc,uint8_t on)1530 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1531 {
1532 if (on) {
1533 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1534 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1535 } else {
1536 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1537 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1538 }
1539 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1540 }
1541
1542 static void
saf1761_otg_update_vbus(struct saf1761_otg_softc * sc)1543 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1544 {
1545 uint16_t status;
1546
1547 /* read fresh status */
1548 status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1549
1550 DPRINTFN(4, "STATUS=0x%04x\n", status);
1551
1552 if ((status & SOTG_STATUS_VBUS_VLD) &&
1553 (status & SOTG_STATUS_ID)) {
1554 /* VBUS present and device mode */
1555 if (!sc->sc_flags.status_vbus) {
1556 sc->sc_flags.status_vbus = 1;
1557
1558 /* complete root HUB interrupt endpoint */
1559 saf1761_otg_root_intr(sc);
1560 }
1561 } else {
1562 /* VBUS not-present or host mode */
1563 if (sc->sc_flags.status_vbus) {
1564 sc->sc_flags.status_vbus = 0;
1565 sc->sc_flags.status_bus_reset = 0;
1566 sc->sc_flags.status_suspend = 0;
1567 sc->sc_flags.change_suspend = 0;
1568 sc->sc_flags.change_connect = 1;
1569
1570 /* complete root HUB interrupt endpoint */
1571 saf1761_otg_root_intr(sc);
1572 }
1573 }
1574 }
1575
1576 static void
saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc * sc)1577 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1578 {
1579 struct usb_xfer *xfer;
1580 repeat:
1581 /* scan for completion events */
1582 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1583 if (saf1761_otg_xfer_do_complete(sc, xfer))
1584 goto repeat;
1585 }
1586 }
1587
1588 int
saf1761_otg_filter_interrupt(void * arg)1589 saf1761_otg_filter_interrupt(void *arg)
1590 {
1591 struct saf1761_otg_softc *sc = arg;
1592 int retval = FILTER_HANDLED;
1593 uint32_t hcstat;
1594 uint32_t status;
1595
1596 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1597
1598 hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1599 /* acknowledge all host controller interrupts */
1600 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1601
1602 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1603 /* acknowledge all device controller interrupts */
1604 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1605 status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1606
1607 (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1608 (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1609 (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1610
1611 DPRINTFN(9, "HCINTERRUPT=0x%08x DCINTERRUPT=0x%08x\n", hcstat, status);
1612
1613 if (status & SOTG_DCINTERRUPT_IEPSOF) {
1614 if ((sc->sc_host_async_busy_map[1] | sc->sc_host_async_busy_map[0] |
1615 sc->sc_host_intr_busy_map[1] | sc->sc_host_intr_busy_map[0] |
1616 sc->sc_host_isoc_busy_map[1] | sc->sc_host_isoc_busy_map[0]) != 0) {
1617 /* busy waiting is active */
1618 retval = FILTER_SCHEDULE_THREAD;
1619
1620 sc->sc_host_async_busy_map[1] = sc->sc_host_async_busy_map[0];
1621 sc->sc_host_async_busy_map[0] = 0;
1622
1623 sc->sc_host_intr_busy_map[1] = sc->sc_host_intr_busy_map[0];
1624 sc->sc_host_intr_busy_map[0] = 0;
1625
1626 sc->sc_host_isoc_busy_map[1] = sc->sc_host_isoc_busy_map[0];
1627 sc->sc_host_isoc_busy_map[0] = 0;
1628 } else {
1629 /* busy waiting is not active */
1630 saf1761_otg_enable_psof(sc, 0);
1631 }
1632 }
1633
1634 if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1635 retval = FILTER_SCHEDULE_THREAD;
1636
1637 /* poll FIFOs, if any */
1638 saf1761_otg_interrupt_poll_locked(sc);
1639
1640 if (sc->sc_xfer_complete != 0)
1641 retval = FILTER_SCHEDULE_THREAD;
1642
1643 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1644
1645 return (retval);
1646 }
1647
1648 void
saf1761_otg_interrupt(void * arg)1649 saf1761_otg_interrupt(void *arg)
1650 {
1651 struct saf1761_otg_softc *sc = arg;
1652 uint32_t status;
1653
1654 USB_BUS_LOCK(&sc->sc_bus);
1655 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1656
1657 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1658 SAF1761_DCINTERRUPT_THREAD_IRQ;
1659
1660 /* acknowledge all device controller interrupts */
1661 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1662
1663 DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1664 "FRINDEX=0x%08x\n", status,
1665 SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1666 SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1667
1668 /* update VBUS and ID bits, if any */
1669 if (status & SOTG_DCINTERRUPT_IEVBUS)
1670 saf1761_otg_update_vbus(sc);
1671
1672 if (status & SOTG_DCINTERRUPT_IEBRST) {
1673 /* unlock device */
1674 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1675 SOTG_UNLOCK_DEVICE_CODE);
1676
1677 /* Enable device address */
1678 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1679 SOTG_ADDRESS_ENABLE);
1680
1681 sc->sc_flags.status_bus_reset = 1;
1682 sc->sc_flags.status_suspend = 0;
1683 sc->sc_flags.change_suspend = 0;
1684 sc->sc_flags.change_connect = 1;
1685
1686 /* disable resume interrupt */
1687 saf1761_otg_wait_suspend(sc, 1);
1688 /* complete root HUB interrupt endpoint */
1689 saf1761_otg_root_intr(sc);
1690 }
1691 /*
1692 * If "RESUME" and "SUSPEND" is set at the same time we
1693 * interpret that like "RESUME". Resume is set when there is
1694 * at least 3 milliseconds of inactivity on the USB BUS:
1695 */
1696 if (status & SOTG_DCINTERRUPT_IERESM) {
1697 /* unlock device */
1698 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1699 SOTG_UNLOCK_DEVICE_CODE);
1700
1701 if (sc->sc_flags.status_suspend) {
1702 sc->sc_flags.status_suspend = 0;
1703 sc->sc_flags.change_suspend = 1;
1704 /* disable resume interrupt */
1705 saf1761_otg_wait_suspend(sc, 1);
1706 /* complete root HUB interrupt endpoint */
1707 saf1761_otg_root_intr(sc);
1708 }
1709 } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1710 if (!sc->sc_flags.status_suspend) {
1711 sc->sc_flags.status_suspend = 1;
1712 sc->sc_flags.change_suspend = 1;
1713 /* enable resume interrupt */
1714 saf1761_otg_wait_suspend(sc, 0);
1715 /* complete root HUB interrupt endpoint */
1716 saf1761_otg_root_intr(sc);
1717 }
1718 }
1719
1720 if (sc->sc_xfer_complete != 0) {
1721 sc->sc_xfer_complete = 0;
1722
1723 /* complete FIFOs, if any */
1724 saf1761_otg_interrupt_complete_locked(sc);
1725 }
1726 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1727 USB_BUS_UNLOCK(&sc->sc_bus);
1728 }
1729
1730 static void
saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp * temp)1731 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1732 {
1733 struct saf1761_otg_td *td;
1734
1735 /* get current Transfer Descriptor */
1736 td = temp->td_next;
1737 temp->td = td;
1738
1739 /* prepare for next TD */
1740 temp->td_next = td->obj_next;
1741
1742 /* fill out the Transfer Descriptor */
1743 td->func = temp->func;
1744 td->pc = temp->pc;
1745 td->offset = temp->offset;
1746 td->remainder = temp->len;
1747 td->error_any = 0;
1748 td->error_stall = 0;
1749 td->set_toggle = 0;
1750 td->did_stall = temp->did_stall;
1751 td->short_pkt = temp->short_pkt;
1752 td->alt_next = temp->setup_alt_next;
1753 td->channel = SOTG_HOST_CHANNEL_MAX;
1754 }
1755
1756 static void
saf1761_otg_setup_standard_chain(struct usb_xfer * xfer)1757 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1758 {
1759 struct saf1761_otg_std_temp temp;
1760 struct saf1761_otg_softc *sc;
1761 struct saf1761_otg_td *td;
1762 uint32_t x;
1763 uint8_t ep_no;
1764 uint8_t ep_type;
1765 uint8_t need_sync;
1766 uint8_t is_host;
1767 uint8_t uframe_start;
1768 uint8_t uframe_interval;
1769
1770 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1771 xfer->address, UE_GET_ADDR(xfer->endpointno),
1772 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1773
1774 temp.max_frame_size = xfer->max_frame_size;
1775
1776 td = xfer->td_start[0];
1777 xfer->td_transfer_first = td;
1778 xfer->td_transfer_cache = td;
1779
1780 /* setup temp */
1781
1782 temp.pc = NULL;
1783 temp.td = NULL;
1784 temp.td_next = xfer->td_start[0];
1785 temp.offset = 0;
1786 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1787 xfer->flags_int.isochronous_xfr;
1788 temp.did_stall = !xfer->flags_int.control_stall;
1789
1790 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1791
1792 sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1793 ep_no = (xfer->endpointno & UE_ADDR);
1794 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1795
1796 /* check if we should prepend a setup message */
1797
1798 if (xfer->flags_int.control_xfr) {
1799 if (xfer->flags_int.control_hdr) {
1800
1801 if (is_host)
1802 temp.func = &saf1761_host_setup_tx;
1803 else
1804 temp.func = &saf1761_device_setup_rx;
1805
1806 temp.len = xfer->frlengths[0];
1807 temp.pc = xfer->frbuffers + 0;
1808 temp.short_pkt = temp.len ? 1 : 0;
1809 /* check for last frame */
1810 if (xfer->nframes == 1) {
1811 /* no STATUS stage yet, SETUP is last */
1812 if (xfer->flags_int.control_act)
1813 temp.setup_alt_next = 0;
1814 }
1815 saf1761_otg_setup_standard_chain_sub(&temp);
1816 }
1817 x = 1;
1818 } else {
1819 x = 0;
1820 }
1821
1822 uframe_start = 0;
1823 uframe_interval = 0;
1824
1825 if (x != xfer->nframes) {
1826 if (xfer->endpointno & UE_DIR_IN) {
1827 if (is_host) {
1828 if (ep_type == UE_INTERRUPT) {
1829 temp.func = &saf1761_host_intr_data_rx;
1830 } else if (ep_type == UE_ISOCHRONOUS) {
1831 temp.func = &saf1761_host_isoc_data_rx;
1832 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1833 (SOTG_FRINDEX_MASK & ~7);
1834 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1835 uframe_interval = 1U << xfer->fps_shift;
1836 else
1837 uframe_interval = 8U;
1838 } else {
1839 temp.func = &saf1761_host_bulk_data_rx;
1840 }
1841 need_sync = 0;
1842 } else {
1843 temp.func = &saf1761_device_data_tx;
1844 need_sync = 1;
1845 }
1846 } else {
1847 if (is_host) {
1848 if (ep_type == UE_INTERRUPT) {
1849 temp.func = &saf1761_host_intr_data_tx;
1850 } else if (ep_type == UE_ISOCHRONOUS) {
1851 temp.func = &saf1761_host_isoc_data_tx;
1852 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1853 (SOTG_FRINDEX_MASK & ~7);
1854 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1855 uframe_interval = 1U << xfer->fps_shift;
1856 else
1857 uframe_interval = 8U;
1858 } else {
1859 temp.func = &saf1761_host_bulk_data_tx;
1860 }
1861 need_sync = 0;
1862 } else {
1863 temp.func = &saf1761_device_data_rx;
1864 need_sync = 0;
1865 }
1866 }
1867
1868 /* setup "pc" pointer */
1869 temp.pc = xfer->frbuffers + x;
1870 } else {
1871 need_sync = 0;
1872 }
1873
1874 while (x != xfer->nframes) {
1875
1876 /* DATA0 / DATA1 message */
1877
1878 temp.len = xfer->frlengths[x];
1879
1880 x++;
1881
1882 if (x == xfer->nframes) {
1883 if (xfer->flags_int.control_xfr) {
1884 if (xfer->flags_int.control_act) {
1885 temp.setup_alt_next = 0;
1886 }
1887 } else {
1888 temp.setup_alt_next = 0;
1889 }
1890 }
1891 if (temp.len == 0) {
1892
1893 /* make sure that we send an USB packet */
1894
1895 temp.short_pkt = 0;
1896
1897 } else {
1898
1899 /* regular data transfer */
1900
1901 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1902 }
1903
1904 saf1761_otg_setup_standard_chain_sub(&temp);
1905
1906 if (xfer->flags_int.isochronous_xfr) {
1907 temp.offset += temp.len;
1908
1909 /* stamp the starting point for this transaction */
1910 temp.td->uframe = uframe_start;
1911
1912 /* advance to next */
1913 uframe_start += uframe_interval;
1914 } else {
1915 /* get next Page Cache pointer */
1916 temp.pc = xfer->frbuffers + x;
1917 }
1918 }
1919
1920 /* check for control transfer */
1921 if (xfer->flags_int.control_xfr) {
1922 /* always setup a valid "pc" pointer for status and sync */
1923 temp.pc = xfer->frbuffers + 0;
1924 temp.len = 0;
1925 temp.short_pkt = 0;
1926 temp.setup_alt_next = 0;
1927
1928 /* check if we should append a status stage */
1929 if (!xfer->flags_int.control_act) {
1930
1931 /*
1932 * Send a DATA1 message and invert the current
1933 * endpoint direction.
1934 */
1935 if (xfer->endpointno & UE_DIR_IN) {
1936 if (is_host) {
1937 temp.func = &saf1761_host_bulk_data_tx;
1938 need_sync = 0;
1939 } else {
1940 temp.func = &saf1761_device_data_rx;
1941 need_sync = 0;
1942 }
1943 } else {
1944 if (is_host) {
1945 temp.func = &saf1761_host_bulk_data_rx;
1946 need_sync = 0;
1947 } else {
1948 temp.func = &saf1761_device_data_tx;
1949 need_sync = 1;
1950 }
1951 }
1952 temp.len = 0;
1953 temp.short_pkt = 0;
1954
1955 saf1761_otg_setup_standard_chain_sub(&temp);
1956
1957 /* data toggle should be DATA1 */
1958 td = temp.td;
1959 td->set_toggle = 1;
1960
1961 if (need_sync) {
1962 /* we need a SYNC point after TX */
1963 temp.func = &saf1761_device_data_tx_sync;
1964 saf1761_otg_setup_standard_chain_sub(&temp);
1965 }
1966 }
1967 } else {
1968 if (need_sync) {
1969 temp.pc = xfer->frbuffers + 0;
1970 temp.len = 0;
1971 temp.short_pkt = 0;
1972 temp.setup_alt_next = 0;
1973
1974 /* we need a SYNC point after TX */
1975 temp.func = &saf1761_device_data_tx_sync;
1976 saf1761_otg_setup_standard_chain_sub(&temp);
1977 }
1978 }
1979
1980 /* must have at least one frame! */
1981 td = temp.td;
1982 xfer->td_transfer_last = td;
1983
1984 if (is_host) {
1985 /* get first again */
1986 td = xfer->td_transfer_first;
1987 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1988 }
1989 }
1990
1991 static void
saf1761_otg_timeout(void * arg)1992 saf1761_otg_timeout(void *arg)
1993 {
1994 struct usb_xfer *xfer = arg;
1995
1996 DPRINTF("xfer=%p\n", xfer);
1997
1998 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1999
2000 /* transfer is transferred */
2001 saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
2002 }
2003
2004 static void
saf1761_otg_intr_set(struct usb_xfer * xfer,uint8_t set)2005 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
2006 {
2007 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2008 uint8_t ep_no = (xfer->endpointno & UE_ADDR);
2009 uint32_t mask;
2010
2011 DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
2012
2013 if (ep_no == 0) {
2014 mask = SOTG_DCINTERRUPT_IEPRX(0) |
2015 SOTG_DCINTERRUPT_IEPTX(0) |
2016 SOTG_DCINTERRUPT_IEP0SETUP;
2017 } else if (xfer->endpointno & UE_DIR_IN) {
2018 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
2019 } else {
2020 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
2021 }
2022
2023 if (set)
2024 sc->sc_intr_enable |= mask;
2025 else
2026 sc->sc_intr_enable &= ~mask;
2027
2028 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2029 }
2030
2031 static void
saf1761_otg_start_standard_chain(struct usb_xfer * xfer)2032 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
2033 {
2034 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2035
2036 DPRINTFN(9, "\n");
2037
2038 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2039
2040 /* poll one time */
2041 saf1761_otg_xfer_do_fifo(sc, xfer);
2042
2043 if (saf1761_otg_xfer_do_complete(sc, xfer) == 0) {
2044 /*
2045 * Only enable the endpoint interrupt when we are
2046 * actually waiting for data, hence we are dealing
2047 * with level triggered interrupts !
2048 */
2049 saf1761_otg_intr_set(xfer, 1);
2050
2051 /* put transfer on interrupt queue */
2052 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2053
2054 /* start timeout, if any */
2055 if (xfer->timeout != 0) {
2056 usbd_transfer_timeout_ms(xfer,
2057 &saf1761_otg_timeout, xfer->timeout);
2058 }
2059 }
2060 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2061 }
2062
2063 static void
saf1761_otg_root_intr(struct saf1761_otg_softc * sc)2064 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
2065 {
2066 DPRINTFN(9, "\n");
2067
2068 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2069
2070 /* set port bit - we only have one port */
2071 sc->sc_hub_idata[0] = 0x02;
2072
2073 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2074 sizeof(sc->sc_hub_idata));
2075 }
2076
2077 static usb_error_t
saf1761_otg_standard_done_sub(struct usb_xfer * xfer)2078 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
2079 {
2080 struct saf1761_otg_td *td;
2081 uint32_t len;
2082 usb_error_t error;
2083
2084 DPRINTFN(9, "\n");
2085
2086 td = xfer->td_transfer_cache;
2087
2088 do {
2089 len = td->remainder;
2090
2091 /* store last data toggle */
2092 xfer->endpoint->toggle_next = td->toggle;
2093
2094 if (xfer->aframes != xfer->nframes) {
2095 /*
2096 * Verify the length and subtract
2097 * the remainder from "frlengths[]":
2098 */
2099 if (len > xfer->frlengths[xfer->aframes]) {
2100 td->error_any = 1;
2101 } else {
2102 xfer->frlengths[xfer->aframes] -= len;
2103 }
2104 }
2105 /* Check for transfer error */
2106 if (td->error_any) {
2107 /* the transfer is finished */
2108 error = (td->error_stall ?
2109 USB_ERR_STALLED : USB_ERR_IOERROR);
2110 td = NULL;
2111 break;
2112 }
2113 /* Check for short transfer */
2114 if (len > 0) {
2115 if (xfer->flags_int.short_frames_ok ||
2116 xfer->flags_int.isochronous_xfr) {
2117 /* follow alt next */
2118 if (td->alt_next) {
2119 td = td->obj_next;
2120 } else {
2121 td = NULL;
2122 }
2123 } else {
2124 /* the transfer is finished */
2125 td = NULL;
2126 }
2127 error = 0;
2128 break;
2129 }
2130 td = td->obj_next;
2131
2132 /* this USB frame is complete */
2133 error = 0;
2134 break;
2135
2136 } while (0);
2137
2138 /* update transfer cache */
2139
2140 xfer->td_transfer_cache = td;
2141
2142 return (error);
2143 }
2144
2145 static void
saf1761_otg_standard_done(struct usb_xfer * xfer)2146 saf1761_otg_standard_done(struct usb_xfer *xfer)
2147 {
2148 usb_error_t err = 0;
2149
2150 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2151 xfer, xfer->endpoint);
2152
2153 /* reset scanner */
2154
2155 xfer->td_transfer_cache = xfer->td_transfer_first;
2156
2157 if (xfer->flags_int.control_xfr) {
2158
2159 if (xfer->flags_int.control_hdr) {
2160
2161 err = saf1761_otg_standard_done_sub(xfer);
2162 }
2163 xfer->aframes = 1;
2164
2165 if (xfer->td_transfer_cache == NULL) {
2166 goto done;
2167 }
2168 }
2169 while (xfer->aframes != xfer->nframes) {
2170
2171 err = saf1761_otg_standard_done_sub(xfer);
2172 xfer->aframes++;
2173
2174 if (xfer->td_transfer_cache == NULL) {
2175 goto done;
2176 }
2177 }
2178
2179 if (xfer->flags_int.control_xfr &&
2180 !xfer->flags_int.control_act) {
2181
2182 err = saf1761_otg_standard_done_sub(xfer);
2183 }
2184 done:
2185 saf1761_otg_device_done(xfer, err);
2186 }
2187
2188 /*------------------------------------------------------------------------*
2189 * saf1761_otg_device_done
2190 *
2191 * NOTE: this function can be called more than one time on the
2192 * same USB transfer!
2193 *------------------------------------------------------------------------*/
2194 static void
saf1761_otg_device_done(struct usb_xfer * xfer,usb_error_t error)2195 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
2196 {
2197 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2198
2199 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2200
2201 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2202 xfer, xfer->endpoint, error);
2203
2204 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2205
2206 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
2207 saf1761_otg_intr_set(xfer, 0);
2208 } else {
2209 struct saf1761_otg_td *td;
2210
2211 td = xfer->td_transfer_cache;
2212
2213 if (td != NULL)
2214 saf1761_host_channel_free(sc, td);
2215 }
2216
2217 /* dequeue transfer and start next transfer */
2218 usbd_transfer_done(xfer, error);
2219
2220 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2221 }
2222
2223 static void
saf1761_otg_xfer_stall(struct usb_xfer * xfer)2224 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
2225 {
2226 saf1761_otg_device_done(xfer, USB_ERR_STALLED);
2227 }
2228
2229 static void
saf1761_otg_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)2230 saf1761_otg_set_stall(struct usb_device *udev,
2231 struct usb_endpoint *ep, uint8_t *did_stall)
2232 {
2233 struct saf1761_otg_softc *sc;
2234 uint8_t ep_no;
2235 uint8_t ep_type;
2236 uint8_t ep_dir;
2237
2238 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2239
2240 /* check mode */
2241 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2242 /* not supported */
2243 return;
2244 }
2245
2246 DPRINTFN(5, "endpoint=%p\n", ep);
2247
2248 /* set STALL bit */
2249 sc = SAF1761_OTG_BUS2SC(udev->bus);
2250
2251 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2252 ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2253 ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2254
2255 if (ep_type == UE_CONTROL) {
2256 /* should not happen */
2257 return;
2258 }
2259 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2260
2261 /* select the correct endpoint */
2262 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2263 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2264 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2265 SOTG_EP_INDEX_DIR_OUT));
2266
2267 /* set stall */
2268 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2269
2270 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2271 }
2272
2273 static void
saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc * sc,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)2274 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2275 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2276 {
2277 if (ep_type == UE_CONTROL) {
2278 /* clearing stall is not needed */
2279 return;
2280 }
2281 /* select the correct endpoint */
2282 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2283 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2284 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2285 SOTG_EP_INDEX_DIR_OUT));
2286
2287 /* disable endpoint */
2288 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2289 /* enable endpoint again - will clear data toggle */
2290 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2291
2292 /* clear buffer */
2293 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2294 /* clear stall */
2295 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2296 }
2297
2298 static void
saf1761_otg_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)2299 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2300 {
2301 struct saf1761_otg_softc *sc;
2302 struct usb_endpoint_descriptor *ed;
2303
2304 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2305
2306 DPRINTFN(5, "endpoint=%p\n", ep);
2307
2308 /* check mode */
2309 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2310 /* not supported */
2311 return;
2312 }
2313 /* get softc */
2314 sc = SAF1761_OTG_BUS2SC(udev->bus);
2315
2316 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2317
2318 /* get endpoint descriptor */
2319 ed = ep->edesc;
2320
2321 /* reset endpoint */
2322 saf1761_otg_clear_stall_sub_locked(sc,
2323 (ed->bEndpointAddress & UE_ADDR),
2324 (ed->bmAttributes & UE_XFERTYPE),
2325 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2326
2327 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2328 }
2329
2330 usb_error_t
saf1761_otg_init(struct saf1761_otg_softc * sc)2331 saf1761_otg_init(struct saf1761_otg_softc *sc)
2332 {
2333 const struct usb_hw_ep_profile *pf;
2334 uint32_t x;
2335
2336 DPRINTF("\n");
2337
2338 /* set up the bus structure */
2339 sc->sc_bus.usbrev = USB_REV_2_0;
2340 sc->sc_bus.methods = &saf1761_otg_bus_methods;
2341
2342 USB_BUS_LOCK(&sc->sc_bus);
2343
2344 /* Reset Host controller, including HW mode */
2345 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2346
2347 DELAY(1000);
2348
2349 /* Reset Host controller, including HW mode */
2350 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2351
2352 /* wait a bit */
2353 DELAY(1000);
2354
2355 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2356
2357 /* wait a bit */
2358 DELAY(1000);
2359
2360 /* Enable interrupts */
2361 sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2362 SOTG_HW_MODE_CTRL_COMN_INT;
2363
2364 /* unlock device */
2365 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2366
2367 /*
2368 * Set correct hardware mode, must be written twice if bus
2369 * width is changed:
2370 */
2371 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2372 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2373
2374 SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2375 SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2376
2377 DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2378 SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2379 SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2380 SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2381 SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2382 SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2383
2384 /* reset device controller */
2385 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2386 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2387
2388 /* wait a bit */
2389 DELAY(1000);
2390
2391 /* reset host controller */
2392 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2393
2394 /* wait for reset to clear */
2395 for (x = 0; x != 10; x++) {
2396 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2397 break;
2398 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2399 }
2400
2401 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2402 SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2403
2404 /* wait a bit */
2405 DELAY(1000);
2406
2407 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2408
2409 /* wait a bit */
2410 DELAY(1000);
2411
2412 /* do a pulldown */
2413 saf1761_otg_pull_down(sc);
2414
2415 /* wait 10ms for pulldown to stabilise */
2416 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2417
2418 for (x = 1;; x++) {
2419
2420 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2421 if (pf == NULL)
2422 break;
2423
2424 /* select the correct endpoint */
2425 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2426 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2427 SOTG_EP_INDEX_DIR_IN);
2428
2429 /* select the maximum packet size */
2430 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2431
2432 /* select the correct endpoint */
2433 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2434 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2435 SOTG_EP_INDEX_DIR_OUT);
2436
2437 /* select the maximum packet size */
2438 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2439 }
2440
2441 /* enable interrupts */
2442 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2443 SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2444
2445 sc->sc_interrupt_cfg |=
2446 SOTG_INTERRUPT_CFG_CDBGMOD |
2447 SOTG_INTERRUPT_CFG_DDBGMODIN |
2448 SOTG_INTERRUPT_CFG_DDBGMODOUT;
2449
2450 /* set default values */
2451 SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2452
2453 /* enable VBUS and ID interrupt */
2454 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2455 SOTG_IRQ_ENABLE_CLR(0xFFFF));
2456 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2457 SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2458
2459 /* enable interrupts */
2460 sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2461 SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2462 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2463
2464 /*
2465 * Connect ATX port 1 to device controller, select external
2466 * charge pump and driver VBUS to +5V:
2467 */
2468 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2469 SOTG_CTRL_CLR(0xFFFF));
2470 #ifdef __rtems__
2471 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2472 SOTG_CTRL_SET(SOTG_CTRL_SEL_CP_EXT | SOTG_CTRL_VBUS_DRV));
2473 #else
2474 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2475 SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2476 SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2477 SOTG_CTRL_VBUS_DRV));
2478 #endif
2479 /* disable device address */
2480 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2481
2482 /* enable host controller clock and preserve reserved bits */
2483 x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2484 SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2485
2486 /* wait 10ms for clock */
2487 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2488
2489 /* enable configuration flag */
2490 SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2491
2492 /* clear RAM block */
2493 for (x = 0x400; x != 0x10000; x += 4)
2494 SAF1761_WRITE_LE_4(sc, x, 0);
2495
2496 /* start the HC */
2497 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2498
2499 DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2500
2501 /* make HC scan all PTDs */
2502 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2503 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2504 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2505
2506 /* skip all PTDs by default */
2507 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2508 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2509 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2510
2511 /* activate all PTD types */
2512 SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2513 SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2514 SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2515 SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2516
2517 /* we don't use the AND mask */
2518 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2519 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2520 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2521
2522 /* enable all PTD OR interrupts by default */
2523 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2524 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2525 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2526
2527 /* enable HC interrupts */
2528 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2529 SOTG_HCINTERRUPT_OTG_IRQ |
2530 SOTG_HCINTERRUPT_ISO_IRQ |
2531 SOTG_HCINTERRUPT_ALT_IRQ |
2532 SOTG_HCINTERRUPT_INT_IRQ);
2533
2534 /* poll initial VBUS status */
2535 saf1761_otg_update_vbus(sc);
2536
2537 USB_BUS_UNLOCK(&sc->sc_bus);
2538
2539 /* catch any lost interrupts */
2540
2541 saf1761_otg_do_poll(&sc->sc_bus);
2542
2543 return (0); /* success */
2544 }
2545
2546 void
saf1761_otg_uninit(struct saf1761_otg_softc * sc)2547 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2548 {
2549 USB_BUS_LOCK(&sc->sc_bus);
2550
2551 /* disable all interrupts */
2552 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2553
2554 sc->sc_flags.port_powered = 0;
2555 sc->sc_flags.status_vbus = 0;
2556 sc->sc_flags.status_bus_reset = 0;
2557 sc->sc_flags.status_suspend = 0;
2558 sc->sc_flags.change_suspend = 0;
2559 sc->sc_flags.change_connect = 1;
2560
2561 saf1761_otg_pull_down(sc);
2562 USB_BUS_UNLOCK(&sc->sc_bus);
2563 }
2564
2565 static void
saf1761_otg_suspend(struct saf1761_otg_softc * sc)2566 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2567 {
2568 /* TODO */
2569 }
2570
2571 static void
saf1761_otg_resume(struct saf1761_otg_softc * sc)2572 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2573 {
2574 /* TODO */
2575 }
2576
2577 static void
saf1761_otg_do_poll(struct usb_bus * bus)2578 saf1761_otg_do_poll(struct usb_bus *bus)
2579 {
2580 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2581
2582 USB_BUS_LOCK(&sc->sc_bus);
2583 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2584 saf1761_otg_interrupt_poll_locked(sc);
2585 saf1761_otg_interrupt_complete_locked(sc);
2586 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2587 USB_BUS_UNLOCK(&sc->sc_bus);
2588 }
2589
2590 /*------------------------------------------------------------------------*
2591 * saf1761_otg control support
2592 * saf1761_otg interrupt support
2593 * saf1761_otg bulk support
2594 *------------------------------------------------------------------------*/
2595 static void
saf1761_otg_device_non_isoc_open(struct usb_xfer * xfer)2596 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2597 {
2598 return;
2599 }
2600
2601 static void
saf1761_otg_device_non_isoc_close(struct usb_xfer * xfer)2602 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2603 {
2604 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2605 }
2606
2607 static void
saf1761_otg_device_non_isoc_enter(struct usb_xfer * xfer)2608 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2609 {
2610 return;
2611 }
2612
2613 static void
saf1761_otg_device_non_isoc_start(struct usb_xfer * xfer)2614 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2615 {
2616 /* setup TDs */
2617 saf1761_otg_setup_standard_chain(xfer);
2618 saf1761_otg_start_standard_chain(xfer);
2619 }
2620
2621 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2622 {
2623 .open = saf1761_otg_device_non_isoc_open,
2624 .close = saf1761_otg_device_non_isoc_close,
2625 .enter = saf1761_otg_device_non_isoc_enter,
2626 .start = saf1761_otg_device_non_isoc_start,
2627 };
2628
2629 /*------------------------------------------------------------------------*
2630 * saf1761_otg device side isochronous support
2631 *------------------------------------------------------------------------*/
2632 static void
saf1761_otg_device_isoc_open(struct usb_xfer * xfer)2633 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2634 {
2635 return;
2636 }
2637
2638 static void
saf1761_otg_device_isoc_close(struct usb_xfer * xfer)2639 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2640 {
2641 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2642 }
2643
2644 static void
saf1761_otg_device_isoc_enter(struct usb_xfer * xfer)2645 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2646 {
2647 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2648 uint32_t temp;
2649 uint32_t nframes;
2650
2651 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2652 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2653
2654 /* get the current frame index - we don't need the high bits */
2655
2656 nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2657
2658 /*
2659 * check if the frame index is within the window where the
2660 * frames will be inserted
2661 */
2662 temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2663
2664 if ((xfer->endpoint->is_synced == 0) ||
2665 (temp < xfer->nframes)) {
2666 /*
2667 * If there is data underflow or the pipe queue is
2668 * empty we schedule the transfer a few frames ahead
2669 * of the current frame position. Else two isochronous
2670 * transfers might overlap.
2671 */
2672 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2673 xfer->endpoint->is_synced = 1;
2674 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2675 }
2676 /*
2677 * compute how many milliseconds the insertion is ahead of the
2678 * current frame position:
2679 */
2680 temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2681
2682 /*
2683 * pre-compute when the isochronous transfer will be finished:
2684 */
2685 xfer->isoc_time_complete =
2686 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2687 xfer->nframes;
2688
2689 /* compute frame number for next insertion */
2690 xfer->endpoint->isoc_next += xfer->nframes;
2691
2692 /* setup TDs */
2693 saf1761_otg_setup_standard_chain(xfer);
2694 }
2695
2696 static void
saf1761_otg_device_isoc_start(struct usb_xfer * xfer)2697 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2698 {
2699 /* start TD chain */
2700 saf1761_otg_start_standard_chain(xfer);
2701 }
2702
2703 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2704 {
2705 .open = saf1761_otg_device_isoc_open,
2706 .close = saf1761_otg_device_isoc_close,
2707 .enter = saf1761_otg_device_isoc_enter,
2708 .start = saf1761_otg_device_isoc_start,
2709 };
2710
2711 /*------------------------------------------------------------------------*
2712 * saf1761_otg host side isochronous support
2713 *------------------------------------------------------------------------*/
2714 static void
saf1761_otg_host_isoc_open(struct usb_xfer * xfer)2715 saf1761_otg_host_isoc_open(struct usb_xfer *xfer)
2716 {
2717 return;
2718 }
2719
2720 static void
saf1761_otg_host_isoc_close(struct usb_xfer * xfer)2721 saf1761_otg_host_isoc_close(struct usb_xfer *xfer)
2722 {
2723 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2724 }
2725
2726 static void
saf1761_otg_host_isoc_enter(struct usb_xfer * xfer)2727 saf1761_otg_host_isoc_enter(struct usb_xfer *xfer)
2728 {
2729 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2730 uint32_t temp;
2731 uint32_t nframes;
2732
2733 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2734 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2735
2736 /* get the current frame index - we don't need the high bits */
2737
2738 nframes = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) & SOTG_FRINDEX_MASK) >> 3;
2739
2740 /*
2741 * check if the frame index is within the window where the
2742 * frames will be inserted
2743 */
2744 temp = (nframes - xfer->endpoint->isoc_next) & (SOTG_FRINDEX_MASK >> 3);
2745
2746 if ((xfer->endpoint->is_synced == 0) ||
2747 (temp < xfer->nframes)) {
2748 /*
2749 * If there is data underflow or the pipe queue is
2750 * empty we schedule the transfer a few frames ahead
2751 * of the current frame position. Else two isochronous
2752 * transfers might overlap.
2753 */
2754 xfer->endpoint->isoc_next = (nframes + 3) & (SOTG_FRINDEX_MASK >> 3);
2755 xfer->endpoint->is_synced = 1;
2756 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2757 }
2758 /*
2759 * compute how many milliseconds the insertion is ahead of the
2760 * current frame position:
2761 */
2762 temp = (xfer->endpoint->isoc_next - nframes) & (SOTG_FRINDEX_MASK >> 3);
2763
2764 /*
2765 * pre-compute when the isochronous transfer will be finished:
2766 */
2767 xfer->isoc_time_complete =
2768 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2769 xfer->nframes;
2770
2771 /* compute frame number for next insertion */
2772 xfer->endpoint->isoc_next += xfer->nframes;
2773
2774 /* setup TDs */
2775 saf1761_otg_setup_standard_chain(xfer);
2776 }
2777
2778 static void
saf1761_otg_host_isoc_start(struct usb_xfer * xfer)2779 saf1761_otg_host_isoc_start(struct usb_xfer *xfer)
2780 {
2781 /* start TD chain */
2782 saf1761_otg_start_standard_chain(xfer);
2783 }
2784
2785 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods =
2786 {
2787 .open = saf1761_otg_host_isoc_open,
2788 .close = saf1761_otg_host_isoc_close,
2789 .enter = saf1761_otg_host_isoc_enter,
2790 .start = saf1761_otg_host_isoc_start,
2791 };
2792
2793 /*------------------------------------------------------------------------*
2794 * saf1761_otg root control support
2795 *------------------------------------------------------------------------*
2796 * Simulate a hardware HUB by handling all the necessary requests.
2797 *------------------------------------------------------------------------*/
2798
2799 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2800
2801 static const struct usb_device_descriptor saf1761_otg_devd = {
2802 .bLength = sizeof(struct usb_device_descriptor),
2803 .bDescriptorType = UDESC_DEVICE,
2804 HSETW(.idVendor, 0x04cc),
2805 HSETW(.idProduct, 0x1761),
2806 .bcdUSB = {0x00, 0x02},
2807 .bDeviceClass = UDCLASS_HUB,
2808 .bDeviceSubClass = UDSUBCLASS_HUB,
2809 .bDeviceProtocol = UDPROTO_FSHUB,
2810 .bMaxPacketSize = 64,
2811 .bcdDevice = {0x00, 0x01},
2812 .iManufacturer = 1,
2813 .iProduct = 2,
2814 .bNumConfigurations = 1,
2815 };
2816
2817 static const struct usb_device_qualifier saf1761_otg_odevd = {
2818 .bLength = sizeof(struct usb_device_qualifier),
2819 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2820 .bcdUSB = {0x00, 0x02},
2821 .bDeviceClass = UDCLASS_HUB,
2822 .bDeviceSubClass = UDSUBCLASS_HUB,
2823 .bDeviceProtocol = UDPROTO_FSHUB,
2824 .bMaxPacketSize0 = 0,
2825 .bNumConfigurations = 0,
2826 };
2827
2828 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2829 .confd = {
2830 .bLength = sizeof(struct usb_config_descriptor),
2831 .bDescriptorType = UDESC_CONFIG,
2832 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2833 .bNumInterface = 1,
2834 .bConfigurationValue = 1,
2835 .iConfiguration = 0,
2836 .bmAttributes = UC_SELF_POWERED,
2837 .bMaxPower = 0,
2838 },
2839 .ifcd = {
2840 .bLength = sizeof(struct usb_interface_descriptor),
2841 .bDescriptorType = UDESC_INTERFACE,
2842 .bNumEndpoints = 1,
2843 .bInterfaceClass = UICLASS_HUB,
2844 .bInterfaceSubClass = UISUBCLASS_HUB,
2845 .bInterfaceProtocol = 0,
2846 },
2847
2848 .endpd = {
2849 .bLength = sizeof(struct usb_endpoint_descriptor),
2850 .bDescriptorType = UDESC_ENDPOINT,
2851 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2852 .bmAttributes = UE_INTERRUPT,
2853 .wMaxPacketSize[0] = 8,
2854 .bInterval = 255,
2855 },
2856 };
2857
2858 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2859 .bDescLength = sizeof(saf1761_otg_hubd),
2860 .bDescriptorType = UDESC_HUB,
2861 .bNbrPorts = SOTG_NUM_PORTS,
2862 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2863 .bPwrOn2PwrGood = 50,
2864 .bHubContrCurrent = 0,
2865 .DeviceRemovable = {0}, /* port is removable */
2866 };
2867
2868 #define STRING_VENDOR \
2869 "N\0X\0P"
2870
2871 #define STRING_PRODUCT \
2872 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2873
2874 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2875 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2876
2877 static usb_error_t
saf1761_otg_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)2878 saf1761_otg_roothub_exec(struct usb_device *udev,
2879 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2880 {
2881 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2882 const void *ptr;
2883 uint16_t len;
2884 uint16_t value;
2885 uint16_t index;
2886 uint32_t temp;
2887 uint32_t i;
2888 usb_error_t err;
2889
2890 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2891
2892 /* buffer reset */
2893 ptr = (const void *)&sc->sc_hub_temp;
2894 len = 0;
2895 err = 0;
2896
2897 value = UGETW(req->wValue);
2898 index = UGETW(req->wIndex);
2899
2900 /* demultiplex the control request */
2901
2902 switch (req->bmRequestType) {
2903 case UT_READ_DEVICE:
2904 switch (req->bRequest) {
2905 case UR_GET_DESCRIPTOR:
2906 goto tr_handle_get_descriptor;
2907 case UR_GET_CONFIG:
2908 goto tr_handle_get_config;
2909 case UR_GET_STATUS:
2910 goto tr_handle_get_status;
2911 default:
2912 goto tr_stalled;
2913 }
2914 break;
2915
2916 case UT_WRITE_DEVICE:
2917 switch (req->bRequest) {
2918 case UR_SET_ADDRESS:
2919 goto tr_handle_set_address;
2920 case UR_SET_CONFIG:
2921 goto tr_handle_set_config;
2922 case UR_CLEAR_FEATURE:
2923 goto tr_valid; /* nop */
2924 case UR_SET_DESCRIPTOR:
2925 goto tr_valid; /* nop */
2926 case UR_SET_FEATURE:
2927 default:
2928 goto tr_stalled;
2929 }
2930 break;
2931
2932 case UT_WRITE_ENDPOINT:
2933 switch (req->bRequest) {
2934 case UR_CLEAR_FEATURE:
2935 switch (UGETW(req->wValue)) {
2936 case UF_ENDPOINT_HALT:
2937 goto tr_handle_clear_halt;
2938 case UF_DEVICE_REMOTE_WAKEUP:
2939 goto tr_handle_clear_wakeup;
2940 default:
2941 goto tr_stalled;
2942 }
2943 break;
2944 case UR_SET_FEATURE:
2945 switch (UGETW(req->wValue)) {
2946 case UF_ENDPOINT_HALT:
2947 goto tr_handle_set_halt;
2948 case UF_DEVICE_REMOTE_WAKEUP:
2949 goto tr_handle_set_wakeup;
2950 default:
2951 goto tr_stalled;
2952 }
2953 break;
2954 case UR_SYNCH_FRAME:
2955 goto tr_valid; /* nop */
2956 default:
2957 goto tr_stalled;
2958 }
2959 break;
2960
2961 case UT_READ_ENDPOINT:
2962 switch (req->bRequest) {
2963 case UR_GET_STATUS:
2964 goto tr_handle_get_ep_status;
2965 default:
2966 goto tr_stalled;
2967 }
2968 break;
2969
2970 case UT_WRITE_INTERFACE:
2971 switch (req->bRequest) {
2972 case UR_SET_INTERFACE:
2973 goto tr_handle_set_interface;
2974 case UR_CLEAR_FEATURE:
2975 goto tr_valid; /* nop */
2976 case UR_SET_FEATURE:
2977 default:
2978 goto tr_stalled;
2979 }
2980 break;
2981
2982 case UT_READ_INTERFACE:
2983 switch (req->bRequest) {
2984 case UR_GET_INTERFACE:
2985 goto tr_handle_get_interface;
2986 case UR_GET_STATUS:
2987 goto tr_handle_get_iface_status;
2988 default:
2989 goto tr_stalled;
2990 }
2991 break;
2992
2993 case UT_WRITE_CLASS_INTERFACE:
2994 case UT_WRITE_VENDOR_INTERFACE:
2995 /* XXX forward */
2996 break;
2997
2998 case UT_READ_CLASS_INTERFACE:
2999 case UT_READ_VENDOR_INTERFACE:
3000 /* XXX forward */
3001 break;
3002
3003 case UT_WRITE_CLASS_DEVICE:
3004 switch (req->bRequest) {
3005 case UR_CLEAR_FEATURE:
3006 goto tr_valid;
3007 case UR_SET_DESCRIPTOR:
3008 case UR_SET_FEATURE:
3009 break;
3010 default:
3011 goto tr_stalled;
3012 }
3013 break;
3014
3015 case UT_WRITE_CLASS_OTHER:
3016 switch (req->bRequest) {
3017 case UR_CLEAR_FEATURE:
3018 if (index == SOTG_HOST_PORT_NUM)
3019 goto tr_handle_clear_port_feature_host;
3020 else if (index == SOTG_DEVICE_PORT_NUM)
3021 goto tr_handle_clear_port_feature_device;
3022 else
3023 goto tr_stalled;
3024 case UR_SET_FEATURE:
3025 if (index == SOTG_HOST_PORT_NUM)
3026 goto tr_handle_set_port_feature_host;
3027 else if (index == SOTG_DEVICE_PORT_NUM)
3028 goto tr_handle_set_port_feature_device;
3029 else
3030 goto tr_stalled;
3031 case UR_CLEAR_TT_BUFFER:
3032 case UR_RESET_TT:
3033 case UR_STOP_TT:
3034 goto tr_valid;
3035
3036 default:
3037 goto tr_stalled;
3038 }
3039 break;
3040
3041 case UT_READ_CLASS_OTHER:
3042 switch (req->bRequest) {
3043 case UR_GET_TT_STATE:
3044 goto tr_handle_get_tt_state;
3045 case UR_GET_STATUS:
3046 if (index == SOTG_HOST_PORT_NUM)
3047 goto tr_handle_get_port_status_host;
3048 else if (index == SOTG_DEVICE_PORT_NUM)
3049 goto tr_handle_get_port_status_device;
3050 else
3051 goto tr_stalled;
3052 default:
3053 goto tr_stalled;
3054 }
3055 break;
3056
3057 case UT_READ_CLASS_DEVICE:
3058 switch (req->bRequest) {
3059 case UR_GET_DESCRIPTOR:
3060 goto tr_handle_get_class_descriptor;
3061 case UR_GET_STATUS:
3062 goto tr_handle_get_class_status;
3063
3064 default:
3065 goto tr_stalled;
3066 }
3067 break;
3068 default:
3069 goto tr_stalled;
3070 }
3071 goto tr_valid;
3072
3073 tr_handle_get_descriptor:
3074 switch (value >> 8) {
3075 case UDESC_DEVICE:
3076 if (value & 0xff)
3077 goto tr_stalled;
3078 len = sizeof(saf1761_otg_devd);
3079 ptr = (const void *)&saf1761_otg_devd;
3080 goto tr_valid;
3081 case UDESC_DEVICE_QUALIFIER:
3082 if (value & 0xff)
3083 goto tr_stalled;
3084 len = sizeof(saf1761_otg_odevd);
3085 ptr = (const void *)&saf1761_otg_odevd;
3086 goto tr_valid;
3087 case UDESC_CONFIG:
3088 if (value & 0xff)
3089 goto tr_stalled;
3090 len = sizeof(saf1761_otg_confd);
3091 ptr = (const void *)&saf1761_otg_confd;
3092 goto tr_valid;
3093 case UDESC_STRING:
3094 switch (value & 0xff) {
3095 case 0: /* Language table */
3096 len = sizeof(usb_string_lang_en);
3097 ptr = (const void *)&usb_string_lang_en;
3098 goto tr_valid;
3099
3100 case 1: /* Vendor */
3101 len = sizeof(saf1761_otg_vendor);
3102 ptr = (const void *)&saf1761_otg_vendor;
3103 goto tr_valid;
3104
3105 case 2: /* Product */
3106 len = sizeof(saf1761_otg_product);
3107 ptr = (const void *)&saf1761_otg_product;
3108 goto tr_valid;
3109 default:
3110 break;
3111 }
3112 break;
3113 default:
3114 goto tr_stalled;
3115 }
3116 goto tr_stalled;
3117
3118 tr_handle_get_config:
3119 len = 1;
3120 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3121 goto tr_valid;
3122
3123 tr_handle_get_status:
3124 len = 2;
3125 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3126 goto tr_valid;
3127
3128 tr_handle_set_address:
3129 if (value & 0xFF00)
3130 goto tr_stalled;
3131
3132 sc->sc_rt_addr = value;
3133 goto tr_valid;
3134
3135 tr_handle_set_config:
3136 if (value >= 2)
3137 goto tr_stalled;
3138 sc->sc_conf = value;
3139 goto tr_valid;
3140
3141 tr_handle_get_interface:
3142 len = 1;
3143 sc->sc_hub_temp.wValue[0] = 0;
3144 goto tr_valid;
3145
3146 tr_handle_get_tt_state:
3147 tr_handle_get_class_status:
3148 tr_handle_get_iface_status:
3149 tr_handle_get_ep_status:
3150 len = 2;
3151 USETW(sc->sc_hub_temp.wValue, 0);
3152 goto tr_valid;
3153
3154 tr_handle_set_halt:
3155 tr_handle_set_interface:
3156 tr_handle_set_wakeup:
3157 tr_handle_clear_wakeup:
3158 tr_handle_clear_halt:
3159 goto tr_valid;
3160
3161 tr_handle_clear_port_feature_device:
3162 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3163
3164 switch (value) {
3165 case UHF_PORT_SUSPEND:
3166 saf1761_otg_wakeup_peer(sc);
3167 break;
3168
3169 case UHF_PORT_ENABLE:
3170 sc->sc_flags.port_enabled = 0;
3171 break;
3172
3173 case UHF_PORT_TEST:
3174 case UHF_PORT_INDICATOR:
3175 case UHF_C_PORT_ENABLE:
3176 case UHF_C_PORT_OVER_CURRENT:
3177 case UHF_C_PORT_RESET:
3178 /* nops */
3179 break;
3180 case UHF_PORT_POWER:
3181 sc->sc_flags.port_powered = 0;
3182 saf1761_otg_pull_down(sc);
3183 break;
3184 case UHF_C_PORT_CONNECTION:
3185 sc->sc_flags.change_connect = 0;
3186 break;
3187 case UHF_C_PORT_SUSPEND:
3188 sc->sc_flags.change_suspend = 0;
3189 break;
3190 default:
3191 err = USB_ERR_IOERROR;
3192 goto tr_valid;
3193 }
3194 goto tr_valid;
3195
3196 tr_handle_clear_port_feature_host:
3197 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3198
3199 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3200
3201 switch (value) {
3202 case UHF_PORT_ENABLE:
3203 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
3204 break;
3205 case UHF_PORT_SUSPEND:
3206 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
3207 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
3208
3209 /* wait 20ms for resume sequence to complete */
3210 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3211
3212 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
3213 SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
3214
3215 /* 4ms settle time */
3216 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3217 break;
3218 case UHF_PORT_INDICATOR:
3219 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
3220 break;
3221 case UHF_PORT_TEST:
3222 case UHF_C_PORT_ENABLE:
3223 case UHF_C_PORT_OVER_CURRENT:
3224 case UHF_C_PORT_RESET:
3225 case UHF_C_PORT_SUSPEND:
3226 /* NOPs */
3227 break;
3228 case UHF_PORT_POWER:
3229 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
3230 break;
3231 case UHF_C_PORT_CONNECTION:
3232 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
3233 break;
3234 default:
3235 err = USB_ERR_IOERROR;
3236 goto tr_valid;
3237 }
3238 goto tr_valid;
3239
3240 tr_handle_set_port_feature_device:
3241 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3242
3243 switch (value) {
3244 case UHF_PORT_ENABLE:
3245 sc->sc_flags.port_enabled = 1;
3246 break;
3247 case UHF_PORT_SUSPEND:
3248 case UHF_PORT_RESET:
3249 case UHF_PORT_TEST:
3250 case UHF_PORT_INDICATOR:
3251 /* nops */
3252 break;
3253 case UHF_PORT_POWER:
3254 sc->sc_flags.port_powered = 1;
3255 break;
3256 default:
3257 err = USB_ERR_IOERROR;
3258 goto tr_valid;
3259 }
3260 goto tr_valid;
3261
3262 tr_handle_set_port_feature_host:
3263 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3264
3265 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3266
3267 switch (value) {
3268 case UHF_PORT_ENABLE:
3269 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
3270 break;
3271 case UHF_PORT_SUSPEND:
3272 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
3273 break;
3274 case UHF_PORT_RESET:
3275 DPRINTFN(6, "reset port %d\n", index);
3276
3277 /* Start reset sequence. */
3278 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
3279
3280 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
3281
3282 /* Wait for reset to complete. */
3283 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3284 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3285
3286 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
3287
3288 /* Wait for HC to complete reset. */
3289 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
3290
3291 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3292
3293 DPRINTF("After reset, status=0x%08x\n", temp);
3294 if (temp & SOTG_PORTSC1_PR) {
3295 device_printf(sc->sc_bus.bdev, "port reset timeout\n");
3296 err = USB_ERR_TIMEOUT;
3297 goto tr_valid;
3298 }
3299 if (!(temp & SOTG_PORTSC1_PED)) {
3300 /* Not a high speed device, give up ownership.*/
3301 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
3302 break;
3303 }
3304 sc->sc_isreset = 1;
3305 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
3306 break;
3307 case UHF_PORT_POWER:
3308 DPRINTFN(3, "set port power %d\n", index);
3309 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
3310 break;
3311
3312 case UHF_PORT_TEST:
3313 DPRINTFN(3, "set port test %d\n", index);
3314 break;
3315
3316 case UHF_PORT_INDICATOR:
3317 DPRINTFN(3, "set port ind %d\n", index);
3318 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
3319 break;
3320 default:
3321 err = USB_ERR_IOERROR;
3322 goto tr_valid;
3323 }
3324 goto tr_valid;
3325
3326 tr_handle_get_port_status_device:
3327
3328 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
3329
3330 if (sc->sc_flags.status_vbus) {
3331 saf1761_otg_pull_up(sc);
3332 } else {
3333 saf1761_otg_pull_down(sc);
3334 }
3335
3336 /* Select FULL-speed and Device Side Mode */
3337
3338 value = UPS_PORT_MODE_DEVICE;
3339
3340 if (sc->sc_flags.port_powered)
3341 value |= UPS_PORT_POWER;
3342
3343 if (sc->sc_flags.port_enabled)
3344 value |= UPS_PORT_ENABLED;
3345
3346 if (sc->sc_flags.status_vbus &&
3347 sc->sc_flags.status_bus_reset)
3348 value |= UPS_CURRENT_CONNECT_STATUS;
3349
3350 if (sc->sc_flags.status_suspend)
3351 value |= UPS_SUSPEND;
3352
3353 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3354
3355 value = 0;
3356
3357 if (sc->sc_flags.change_connect)
3358 value |= UPS_C_CONNECT_STATUS;
3359
3360 if (sc->sc_flags.change_suspend)
3361 value |= UPS_C_SUSPEND;
3362
3363 USETW(sc->sc_hub_temp.ps.wPortChange, value);
3364 len = sizeof(sc->sc_hub_temp.ps);
3365 goto tr_valid;
3366
3367 tr_handle_get_port_status_host:
3368
3369 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3370
3371 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3372
3373 i = UPS_HIGH_SPEED;
3374
3375 if (temp & SOTG_PORTSC1_ECCS)
3376 i |= UPS_CURRENT_CONNECT_STATUS;
3377 if (temp & SOTG_PORTSC1_PED)
3378 i |= UPS_PORT_ENABLED;
3379 if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3380 i |= UPS_SUSPEND;
3381 if (temp & SOTG_PORTSC1_PR)
3382 i |= UPS_RESET;
3383 if (temp & SOTG_PORTSC1_PP)
3384 i |= UPS_PORT_POWER;
3385
3386 USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3387 i = 0;
3388
3389 if (temp & SOTG_PORTSC1_ECSC)
3390 i |= UPS_C_CONNECT_STATUS;
3391 if (temp & SOTG_PORTSC1_FPR)
3392 i |= UPS_C_SUSPEND;
3393 if (sc->sc_isreset)
3394 i |= UPS_C_PORT_RESET;
3395 USETW(sc->sc_hub_temp.ps.wPortChange, i);
3396 len = sizeof(sc->sc_hub_temp.ps);
3397 goto tr_valid;
3398
3399 tr_handle_get_class_descriptor:
3400 if (value & 0xFF)
3401 goto tr_stalled;
3402 ptr = (const void *)&saf1761_otg_hubd;
3403 len = sizeof(saf1761_otg_hubd);
3404 goto tr_valid;
3405
3406 tr_stalled:
3407 err = USB_ERR_STALLED;
3408 tr_valid:
3409 *plength = len;
3410 *pptr = ptr;
3411 return (err);
3412 }
3413
3414 static void
saf1761_otg_xfer_setup(struct usb_setup_params * parm)3415 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3416 {
3417 struct saf1761_otg_softc *sc;
3418 struct usb_xfer *xfer;
3419 void *last_obj;
3420 uint32_t dw1;
3421 uint32_t ntd;
3422 uint32_t n;
3423 uint8_t ep_no;
3424 uint8_t ep_type;
3425
3426 sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3427 xfer = parm->curr_xfer;
3428
3429 /*
3430 * NOTE: This driver does not use any of the parameters that
3431 * are computed from the following values. Just set some
3432 * reasonable dummies:
3433 */
3434 parm->hc_max_packet_size = 0x500;
3435 parm->hc_max_packet_count = 1;
3436 parm->hc_max_frame_size = 0x500;
3437
3438 usbd_transfer_setup_sub(parm);
3439
3440 /*
3441 * Compute maximum number of TDs:
3442 */
3443 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3444
3445 if (ep_type == UE_CONTROL) {
3446
3447 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3448
3449 } else {
3450 ntd = xfer->nframes + 1 /* SYNC */ ;
3451 }
3452
3453 /*
3454 * check if "usbd_transfer_setup_sub" set an error
3455 */
3456 if (parm->err)
3457 return;
3458
3459 /*
3460 * allocate transfer descriptors
3461 */
3462 last_obj = NULL;
3463
3464 ep_no = xfer->endpointno & UE_ADDR;
3465
3466 /*
3467 * Check profile stuff
3468 */
3469 if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3470 const struct usb_hw_ep_profile *pf;
3471
3472 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3473
3474 if (pf == NULL) {
3475 /* should not happen */
3476 parm->err = USB_ERR_INVAL;
3477 return;
3478 }
3479 }
3480
3481 dw1 = (xfer->address << 3) | (ep_type << 12);
3482
3483 switch (parm->udev->speed) {
3484 case USB_SPEED_FULL:
3485 case USB_SPEED_LOW:
3486 /* check if root HUB port is running High Speed */
3487 if (parm->udev->parent_hs_hub != NULL) {
3488 dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3489 dw1 |= (parm->udev->hs_port_no << 18);
3490 dw1 |= (parm->udev->hs_hub_addr << 25);
3491 if (parm->udev->speed == USB_SPEED_LOW)
3492 dw1 |= (1 << 17);
3493 }
3494 break;
3495 default:
3496 break;
3497 }
3498
3499 /* align data */
3500 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3501
3502 for (n = 0; n != ntd; n++) {
3503
3504 struct saf1761_otg_td *td;
3505
3506 if (parm->buf) {
3507
3508 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3509
3510 /* init TD */
3511 td->max_packet_size = xfer->max_packet_size;
3512 td->ep_index = ep_no;
3513 td->ep_type = ep_type;
3514 td->dw1_value = dw1;
3515 td->uframe = 0;
3516
3517 if (ep_type == UE_INTERRUPT) {
3518 if (xfer->interval > 32)
3519 td->interval = (32 / 2) << 3;
3520 else
3521 td->interval = (xfer->interval / 2) << 3;
3522 } else {
3523 td->interval = 0;
3524 }
3525 td->obj_next = last_obj;
3526
3527 last_obj = td;
3528 }
3529 parm->size[0] += sizeof(*td);
3530 }
3531
3532 xfer->td_start[0] = last_obj;
3533 }
3534
3535 static void
saf1761_otg_xfer_unsetup(struct usb_xfer * xfer)3536 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3537 {
3538 }
3539
3540 static void
saf1761_otg_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3541 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3542 struct usb_endpoint *ep)
3543 {
3544 uint16_t mps;
3545
3546 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3547 ep, udev->address,
3548 edesc->bEndpointAddress, udev->flags.usb_mode);
3549
3550 if (udev->parent_hub == NULL) {
3551 /* root HUB has special endpoint handling */
3552 return;
3553 }
3554
3555 /* Verify wMaxPacketSize */
3556 mps = UGETW(edesc->wMaxPacketSize);
3557 if (udev->speed == USB_SPEED_HIGH) {
3558 if ((mps >> 11) & 3) {
3559 DPRINTF("A packet multiplier different from "
3560 "1 is not supported\n");
3561 return;
3562 }
3563 }
3564 if (mps > SOTG_HS_MAX_PACKET_SIZE) {
3565 DPRINTF("Packet size %d bigger than %d\n",
3566 (int)mps, SOTG_HS_MAX_PACKET_SIZE);
3567 return;
3568 }
3569 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3570 if (udev->speed != USB_SPEED_FULL &&
3571 udev->speed != USB_SPEED_HIGH) {
3572 /* not supported */
3573 return;
3574 }
3575 switch (edesc->bmAttributes & UE_XFERTYPE) {
3576 case UE_ISOCHRONOUS:
3577 ep->methods = &saf1761_otg_device_isoc_methods;
3578 break;
3579 default:
3580 ep->methods = &saf1761_otg_non_isoc_methods;
3581 break;
3582 }
3583 } else {
3584 switch (edesc->bmAttributes & UE_XFERTYPE) {
3585 case UE_ISOCHRONOUS:
3586 ep->methods = &saf1761_otg_host_isoc_methods;
3587 break;
3588 default:
3589 ep->methods = &saf1761_otg_non_isoc_methods;
3590 break;
3591 }
3592 }
3593 }
3594
3595 static void
saf1761_otg_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)3596 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3597 {
3598 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3599
3600 switch (state) {
3601 case USB_HW_POWER_SUSPEND:
3602 saf1761_otg_suspend(sc);
3603 break;
3604 case USB_HW_POWER_SHUTDOWN:
3605 saf1761_otg_uninit(sc);
3606 break;
3607 case USB_HW_POWER_RESUME:
3608 saf1761_otg_resume(sc);
3609 break;
3610 default:
3611 break;
3612 }
3613 }
3614
3615 static void
saf1761_otg_device_resume(struct usb_device * udev)3616 saf1761_otg_device_resume(struct usb_device *udev)
3617 {
3618 struct saf1761_otg_softc *sc;
3619 struct saf1761_otg_td *td;
3620 struct usb_xfer *xfer;
3621 uint8_t x;
3622
3623 DPRINTF("\n");
3624
3625 if (udev->flags.usb_mode != USB_MODE_HOST)
3626 return;
3627
3628 sc = SAF1761_OTG_BUS2SC(udev->bus);
3629
3630 USB_BUS_LOCK(&sc->sc_bus);
3631 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3632
3633 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3634
3635 if (xfer->xroot->udev != udev)
3636 continue;
3637
3638 td = xfer->td_transfer_cache;
3639 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3640 continue;
3641
3642 switch (td->ep_type) {
3643 case UE_INTERRUPT:
3644 x = td->channel - 32;
3645 sc->sc_host_intr_suspend_map &= ~(1U << x);
3646 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3647 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3648 break;
3649 case UE_ISOCHRONOUS:
3650 x = td->channel;
3651 sc->sc_host_isoc_suspend_map &= ~(1U << x);
3652 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3653 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3654 break;
3655 default:
3656 x = td->channel - 64;
3657 sc->sc_host_async_suspend_map &= ~(1U << x);
3658 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3659 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3660 break;
3661 }
3662 }
3663
3664 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3665 USB_BUS_UNLOCK(&sc->sc_bus);
3666
3667 /* poll all transfers again to restart resumed ones */
3668 saf1761_otg_do_poll(&sc->sc_bus);
3669 }
3670
3671 static void
saf1761_otg_device_suspend(struct usb_device * udev)3672 saf1761_otg_device_suspend(struct usb_device *udev)
3673 {
3674 struct saf1761_otg_softc *sc;
3675 struct saf1761_otg_td *td;
3676 struct usb_xfer *xfer;
3677 uint8_t x;
3678
3679 DPRINTF("\n");
3680
3681 if (udev->flags.usb_mode != USB_MODE_HOST)
3682 return;
3683
3684 sc = SAF1761_OTG_BUS2SC(udev->bus);
3685
3686 USB_BUS_LOCK(&sc->sc_bus);
3687 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3688
3689 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3690
3691 if (xfer->xroot->udev != udev)
3692 continue;
3693
3694 td = xfer->td_transfer_cache;
3695 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3696 continue;
3697
3698 switch (td->ep_type) {
3699 case UE_INTERRUPT:
3700 x = td->channel - 32;
3701 sc->sc_host_intr_suspend_map |= (1U << x);
3702 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3703 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3704 break;
3705 case UE_ISOCHRONOUS:
3706 x = td->channel;
3707 sc->sc_host_isoc_suspend_map |= (1U << x);
3708 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3709 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3710 break;
3711 default:
3712 x = td->channel - 64;
3713 sc->sc_host_async_suspend_map |= (1U << x);
3714 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3715 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3716 break;
3717 }
3718 }
3719
3720 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3721 USB_BUS_UNLOCK(&sc->sc_bus);
3722 }
3723
3724 static const struct usb_bus_methods saf1761_otg_bus_methods =
3725 {
3726 .endpoint_init = &saf1761_otg_ep_init,
3727 .xfer_setup = &saf1761_otg_xfer_setup,
3728 .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3729 .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3730 .xfer_stall = &saf1761_otg_xfer_stall,
3731 .set_stall = &saf1761_otg_set_stall,
3732 .clear_stall = &saf1761_otg_clear_stall,
3733 .roothub_exec = &saf1761_otg_roothub_exec,
3734 .xfer_poll = &saf1761_otg_do_poll,
3735 .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3736 .device_resume = &saf1761_otg_device_resume,
3737 .device_suspend = &saf1761_otg_device_suspend,
3738 };
3739