1 /* $FreeBSD$ */
2 /*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
31 * at their homepage.
32 */
33
34 /*
35 * This file contains the driver for the Mentor Graphics Inventra USB
36 * 2.0 High Speed Dual-Role controller.
37 *
38 */
39
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
42 #else
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/bus.h>
51 #include <sys/module.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
56 #include <sys/sx.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
60 #include <sys/priv.h>
61
62 #include <dev/usb/usb.h>
63 #include <dev/usb/usbdi.h>
64
65 #define USB_DEBUG_VAR musbotgdebug
66
67 #include <dev/usb/usb_core.h>
68 #include <dev/usb/usb_debug.h>
69 #include <dev/usb/usb_busdma.h>
70 #include <dev/usb/usb_process.h>
71 #include <dev/usb/usb_transfer.h>
72 #include <dev/usb/usb_device.h>
73 #include <dev/usb/usb_hub.h>
74 #include <dev/usb/usb_util.h>
75
76 #include <dev/usb/usb_controller.h>
77 #include <dev/usb/usb_bus.h>
78 #endif /* USB_GLOBAL_INCLUDE_FILE */
79
80 #include <dev/usb/controller/musb_otg.h>
81
82 #define MUSBOTG_INTR_ENDPT 1
83
84 #define MUSBOTG_BUS2SC(bus) \
85 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
86 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
87
88 #define MUSBOTG_PC2SC(pc) \
89 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
90
91 #ifdef USB_DEBUG
92 static int musbotgdebug = 0;
93
94 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
95 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
96 &musbotgdebug, 0, "Debug level");
97 #endif
98
99 #define MAX_NAK_TO 16
100
101 /* prototypes */
102
103 static const struct usb_bus_methods musbotg_bus_methods;
104 static const struct usb_pipe_methods musbotg_device_bulk_methods;
105 static const struct usb_pipe_methods musbotg_device_ctrl_methods;
106 static const struct usb_pipe_methods musbotg_device_intr_methods;
107 static const struct usb_pipe_methods musbotg_device_isoc_methods;
108
109 /* Control transfers: Device mode */
110 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
112 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
113 static musbotg_cmd_t musbotg_dev_ctrl_status;
114
115 /* Control transfers: Host mode */
116 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
118 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
120 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
121
122 /* Bulk, Interrupt, Isochronous: Device mode */
123 static musbotg_cmd_t musbotg_dev_data_rx;
124 static musbotg_cmd_t musbotg_dev_data_tx;
125
126 /* Bulk, Interrupt, Isochronous: Host mode */
127 static musbotg_cmd_t musbotg_host_data_rx;
128 static musbotg_cmd_t musbotg_host_data_tx;
129
130 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
131 static void musbotg_do_poll(struct usb_bus *);
132 static void musbotg_standard_done(struct usb_xfer *);
133 static void musbotg_interrupt_poll(struct musbotg_softc *);
134 static void musbotg_root_intr(struct musbotg_softc *);
135 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
136 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
137 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
138
139 /*
140 * Here is a configuration that the chip supports.
141 */
142 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
143
144 [0] = {
145 .max_in_frame_size = 64,/* fixed */
146 .max_out_frame_size = 64, /* fixed */
147 .is_simplex = 1,
148 .support_control = 1,
149 }
150 };
151
152 static const struct musb_otg_ep_cfg musbotg_ep_default[] = {
153 {
154 .ep_end = 1,
155 .ep_fifosz_shift = 12,
156 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB,
157 },
158 {
159 .ep_end = 7,
160 .ep_fifosz_shift = 10,
161 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB,
162 },
163 {
164 .ep_end = 15,
165 .ep_fifosz_shift = 7,
166 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128,
167 },
168 {
169 .ep_end = -1,
170 },
171 };
172
173 static int
musbotg_channel_alloc(struct musbotg_softc * sc,struct musbotg_td * td,uint8_t is_tx)174 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
175 {
176 int ch;
177 int ep;
178
179 ep = td->ep_no;
180
181 /* In device mode each EP got its own channel */
182 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
183 musbotg_ep_int_set(sc, ep, 1);
184 return (ep);
185 }
186
187 /*
188 * All control transactions go through EP0
189 */
190 if (ep == 0) {
191 if (sc->sc_channel_mask & (1 << 0))
192 return (-1);
193 sc->sc_channel_mask |= (1 << 0);
194 musbotg_ep_int_set(sc, ep, 1);
195 return (0);
196 }
197
198 for (ch = sc->sc_ep_max; ch != 0; ch--) {
199 if (sc->sc_channel_mask & (1 << ch))
200 continue;
201
202 /* check FIFO size requirement */
203 if (is_tx) {
204 if (td->max_frame_size >
205 sc->sc_hw_ep_profile[ch].max_in_frame_size)
206 continue;
207 } else {
208 if (td->max_frame_size >
209 sc->sc_hw_ep_profile[ch].max_out_frame_size)
210 continue;
211 }
212 sc->sc_channel_mask |= (1 << ch);
213 musbotg_ep_int_set(sc, ch, 1);
214 return (ch);
215 }
216
217 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
218
219 return (-1);
220 }
221
222 static void
musbotg_channel_free(struct musbotg_softc * sc,struct musbotg_td * td)223 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
224 {
225
226 DPRINTFN(1, "ep_no=%d\n", td->channel);
227
228 if (sc->sc_mode == MUSB2_DEVICE_MODE)
229 return;
230
231 if (td == NULL)
232 return;
233 if (td->channel == -1)
234 return;
235
236 musbotg_ep_int_set(sc, td->channel, 0);
237 sc->sc_channel_mask &= ~(1 << td->channel);
238
239 td->channel = -1;
240 }
241
242 static void
musbotg_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)243 musbotg_get_hw_ep_profile(struct usb_device *udev,
244 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
245 {
246 struct musbotg_softc *sc;
247
248 sc = MUSBOTG_BUS2SC(udev->bus);
249
250 if (ep_addr == 0) {
251 /* control endpoint */
252 *ppf = musbotg_ep_profile;
253 } else if (ep_addr <= sc->sc_ep_max) {
254 /* other endpoints */
255 *ppf = sc->sc_hw_ep_profile + ep_addr;
256 } else {
257 *ppf = NULL;
258 }
259 }
260
261 static void
musbotg_clocks_on(struct musbotg_softc * sc)262 musbotg_clocks_on(struct musbotg_softc *sc)
263 {
264 if (sc->sc_flags.clocks_off &&
265 sc->sc_flags.port_powered) {
266
267 DPRINTFN(4, "\n");
268
269 if (sc->sc_clocks_on) {
270 (sc->sc_clocks_on) (sc->sc_clocks_arg);
271 }
272 sc->sc_flags.clocks_off = 0;
273
274 /* XXX enable Transceiver */
275 }
276 }
277
278 static void
musbotg_clocks_off(struct musbotg_softc * sc)279 musbotg_clocks_off(struct musbotg_softc *sc)
280 {
281 if (!sc->sc_flags.clocks_off) {
282
283 DPRINTFN(4, "\n");
284
285 /* XXX disable Transceiver */
286
287 if (sc->sc_clocks_off) {
288 (sc->sc_clocks_off) (sc->sc_clocks_arg);
289 }
290 sc->sc_flags.clocks_off = 1;
291 }
292 }
293
294 static void
musbotg_pull_common(struct musbotg_softc * sc,uint8_t on)295 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
296 {
297 uint8_t temp;
298
299 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
300 if (on)
301 temp |= MUSB2_MASK_SOFTC;
302 else
303 temp &= ~MUSB2_MASK_SOFTC;
304
305 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
306 }
307
308 static void
musbotg_pull_up(struct musbotg_softc * sc)309 musbotg_pull_up(struct musbotg_softc *sc)
310 {
311 /* pullup D+, if possible */
312
313 if (!sc->sc_flags.d_pulled_up &&
314 sc->sc_flags.port_powered) {
315 sc->sc_flags.d_pulled_up = 1;
316 musbotg_pull_common(sc, 1);
317 }
318 }
319
320 static void
musbotg_pull_down(struct musbotg_softc * sc)321 musbotg_pull_down(struct musbotg_softc *sc)
322 {
323 /* pulldown D+, if possible */
324
325 if (sc->sc_flags.d_pulled_up) {
326 sc->sc_flags.d_pulled_up = 0;
327 musbotg_pull_common(sc, 0);
328 }
329 }
330
331 static void
musbotg_suspend_host(struct musbotg_softc * sc)332 musbotg_suspend_host(struct musbotg_softc *sc)
333 {
334 uint8_t temp;
335
336 if (sc->sc_flags.status_suspend) {
337 return;
338 }
339
340 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
341 temp |= MUSB2_MASK_SUSPMODE;
342 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
343 sc->sc_flags.status_suspend = 1;
344 }
345
346 static void
musbotg_wakeup_host(struct musbotg_softc * sc)347 musbotg_wakeup_host(struct musbotg_softc *sc)
348 {
349 uint8_t temp;
350
351 if (!(sc->sc_flags.status_suspend)) {
352 return;
353 }
354
355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
356 temp &= ~MUSB2_MASK_SUSPMODE;
357 temp |= MUSB2_MASK_RESUME;
358 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
359
360 /* wait 20 milliseconds */
361 /* Wait for reset to complete. */
362 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
363
364 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
365 temp &= ~MUSB2_MASK_RESUME;
366 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
367
368 sc->sc_flags.status_suspend = 0;
369 }
370
371 static void
musbotg_wakeup_peer(struct musbotg_softc * sc)372 musbotg_wakeup_peer(struct musbotg_softc *sc)
373 {
374 uint8_t temp;
375
376 if (!(sc->sc_flags.status_suspend)) {
377 return;
378 }
379
380 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
381 temp |= MUSB2_MASK_RESUME;
382 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
383
384 /* wait 8 milliseconds */
385 /* Wait for reset to complete. */
386 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
387
388 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
389 temp &= ~MUSB2_MASK_RESUME;
390 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
391 }
392
393 static void
musbotg_set_address(struct musbotg_softc * sc,uint8_t addr)394 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
395 {
396 DPRINTFN(4, "addr=%d\n", addr);
397 addr &= 0x7F;
398 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
399 }
400
401 static uint8_t
musbotg_dev_ctrl_setup_rx(struct musbotg_td * td)402 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
403 {
404 struct musbotg_softc *sc;
405 struct usb_device_request req;
406 uint16_t count;
407 uint8_t csr;
408
409 /* get pointer to softc */
410 sc = MUSBOTG_PC2SC(td->pc);
411
412 if (td->channel == -1)
413 td->channel = musbotg_channel_alloc(sc, td, 0);
414
415 /* EP0 is busy, wait */
416 if (td->channel == -1)
417 return (1);
418
419 DPRINTFN(1, "ep_no=%d\n", td->channel);
420
421 /* select endpoint 0 */
422 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
423
424 /* read out FIFO status */
425 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
426
427 DPRINTFN(4, "csr=0x%02x\n", csr);
428
429 /*
430 * NOTE: If DATAEND is set we should not call the
431 * callback, hence the status stage is not complete.
432 */
433 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
434 /* do not stall at this point */
435 td->did_stall = 1;
436 /* wait for interrupt */
437 DPRINTFN(1, "CSR0 DATAEND\n");
438 goto not_complete;
439 }
440
441 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
442 /* clear SENTSTALL */
443 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
444 /* get latest status */
445 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
446 /* update EP0 state */
447 sc->sc_ep0_busy = 0;
448 }
449 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
450 /* clear SETUPEND */
451 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
452 MUSB2_MASK_CSR0L_SETUPEND_CLR);
453 /* get latest status */
454 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
455 /* update EP0 state */
456 sc->sc_ep0_busy = 0;
457 }
458 if (sc->sc_ep0_busy) {
459 DPRINTFN(1, "EP0 BUSY\n");
460 goto not_complete;
461 }
462 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
463 goto not_complete;
464 }
465 /* get the packet byte count */
466 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
467
468 /* verify data length */
469 if (count != td->remainder) {
470 DPRINTFN(1, "Invalid SETUP packet "
471 "length, %d bytes\n", count);
472 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
473 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
474 /* don't clear stall */
475 td->did_stall = 1;
476 goto not_complete;
477 }
478 if (count != sizeof(req)) {
479 DPRINTFN(1, "Unsupported SETUP packet "
480 "length, %d bytes\n", count);
481 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
482 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
483 /* don't clear stall */
484 td->did_stall = 1;
485 goto not_complete;
486 }
487 /* clear did stall flag */
488 td->did_stall = 0;
489
490 /* receive data */
491 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
492 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
493
494 /* copy data into real buffer */
495 usbd_copy_in(td->pc, 0, &req, sizeof(req));
496
497 td->offset = sizeof(req);
498 td->remainder = 0;
499
500 /* set pending command */
501 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
502
503 /* we need set stall or dataend after this */
504 sc->sc_ep0_busy = 1;
505
506 /* sneak peek the set address */
507 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
508 (req.bRequest == UR_SET_ADDRESS)) {
509 sc->sc_dv_addr = req.wValue[0] & 0x7F;
510 } else {
511 sc->sc_dv_addr = 0xFF;
512 }
513
514 musbotg_channel_free(sc, td);
515 return (0); /* complete */
516
517 not_complete:
518 /* abort any ongoing transfer */
519 if (!td->did_stall) {
520 DPRINTFN(4, "stalling\n");
521 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
522 MUSB2_MASK_CSR0L_SENDSTALL);
523 td->did_stall = 1;
524 }
525 return (1); /* not complete */
526 }
527
528 static uint8_t
musbotg_host_ctrl_setup_tx(struct musbotg_td * td)529 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
530 {
531 struct musbotg_softc *sc;
532 struct usb_device_request req;
533 uint8_t csr, csrh;
534
535 /* get pointer to softc */
536 sc = MUSBOTG_PC2SC(td->pc);
537
538 if (td->channel == -1)
539 td->channel = musbotg_channel_alloc(sc, td, 1);
540
541 /* EP0 is busy, wait */
542 if (td->channel == -1)
543 return (1);
544
545 DPRINTFN(1, "ep_no=%d\n", td->channel);
546
547 /* select endpoint 0 */
548 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
549
550 /* read out FIFO status */
551 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
552 DPRINTFN(4, "csr=0x%02x\n", csr);
553
554 /* Not ready yet yet */
555 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
556 return (1);
557
558 /* Failed */
559 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
560 MUSB2_MASK_CSR0L_ERROR))
561 {
562 /* Clear status bit */
563 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
564 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
565 td->error = 1;
566 }
567
568 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
569 DPRINTFN(1, "NAK timeout\n");
570
571 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
572 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
573 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
574 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
575 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
576 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
577 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
578 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
579 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
580 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
581 }
582 }
583
584 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
585 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
586
587 td->error = 1;
588 }
589
590 if (td->error) {
591 musbotg_channel_free(sc, td);
592 return (0);
593 }
594
595 /* Fifo is not empty and there is no NAK timeout */
596 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
597 return (1);
598
599 /* check if we are complete */
600 if (td->remainder == 0) {
601 /* we are complete */
602 musbotg_channel_free(sc, td);
603 return (0);
604 }
605
606 /* copy data into real buffer */
607 usbd_copy_out(td->pc, 0, &req, sizeof(req));
608
609 /* send data */
610 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
611 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
612
613 /* update offset and remainder */
614 td->offset += sizeof(req);
615 td->remainder -= sizeof(req);
616
617
618 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
619 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
620 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
621 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
622 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
623
624 /* write command */
625 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
626 MUSB2_MASK_CSR0L_TXPKTRDY |
627 MUSB2_MASK_CSR0L_SETUPPKT);
628
629 /* Just to be consistent, not used above */
630 td->transaction_started = 1;
631
632 return (1); /* in progress */
633 }
634
635 /* Control endpoint only data handling functions (RX/TX/SYNC) */
636
637 static uint8_t
musbotg_dev_ctrl_data_rx(struct musbotg_td * td)638 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
639 {
640 struct usb_page_search buf_res;
641 struct musbotg_softc *sc;
642 uint16_t count;
643 uint8_t csr;
644 uint8_t got_short;
645
646 /* get pointer to softc */
647 sc = MUSBOTG_PC2SC(td->pc);
648
649 /* select endpoint 0 */
650 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
651
652 /* check if a command is pending */
653 if (sc->sc_ep0_cmd) {
654 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
655 sc->sc_ep0_cmd = 0;
656 }
657 /* read out FIFO status */
658 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
659
660 DPRINTFN(4, "csr=0x%02x\n", csr);
661
662 got_short = 0;
663
664 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
665 MUSB2_MASK_CSR0L_SENTSTALL)) {
666 if (td->remainder == 0) {
667 /*
668 * We are actually complete and have
669 * received the next SETUP
670 */
671 DPRINTFN(4, "faking complete\n");
672 return (0); /* complete */
673 }
674 /*
675 * USB Host Aborted the transfer.
676 */
677 td->error = 1;
678 return (0); /* complete */
679 }
680 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
681 return (1); /* not complete */
682 }
683 /* get the packet byte count */
684 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
685
686 /* verify the packet byte count */
687 if (count != td->max_frame_size) {
688 if (count < td->max_frame_size) {
689 /* we have a short packet */
690 td->short_pkt = 1;
691 got_short = 1;
692 } else {
693 /* invalid USB packet */
694 td->error = 1;
695 return (0); /* we are complete */
696 }
697 }
698 /* verify the packet byte count */
699 if (count > td->remainder) {
700 /* invalid USB packet */
701 td->error = 1;
702 return (0); /* we are complete */
703 }
704 while (count > 0) {
705 uint32_t temp;
706
707 usbd_get_page(td->pc, td->offset, &buf_res);
708
709 /* get correct length */
710 if (buf_res.length > count) {
711 buf_res.length = count;
712 }
713 /* check for unaligned memory address */
714 if (USB_P2U(buf_res.buffer) & 3) {
715
716 temp = count & ~3;
717
718 if (temp) {
719 /* receive data 4 bytes at a time */
720 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
721 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
722 temp / 4);
723 }
724 temp = count & 3;
725 if (temp) {
726 /* receive data 1 byte at a time */
727 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
728 MUSB2_REG_EPFIFO(0),
729 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
730 }
731 usbd_copy_in(td->pc, td->offset,
732 sc->sc_bounce_buf, count);
733
734 /* update offset and remainder */
735 td->offset += count;
736 td->remainder -= count;
737 break;
738 }
739 /* check if we can optimise */
740 if (buf_res.length >= 4) {
741
742 /* receive data 4 bytes at a time */
743 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
744 MUSB2_REG_EPFIFO(0), buf_res.buffer,
745 buf_res.length / 4);
746
747 temp = buf_res.length & ~3;
748
749 /* update counters */
750 count -= temp;
751 td->offset += temp;
752 td->remainder -= temp;
753 continue;
754 }
755 /* receive data */
756 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
757 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
758
759 /* update counters */
760 count -= buf_res.length;
761 td->offset += buf_res.length;
762 td->remainder -= buf_res.length;
763 }
764
765 /* check if we are complete */
766 if ((td->remainder == 0) || got_short) {
767 if (td->short_pkt) {
768 /* we are complete */
769 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
770 return (0);
771 }
772 /* else need to receive a zero length packet */
773 }
774 /* write command - need more data */
775 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
776 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
777 return (1); /* not complete */
778 }
779
780 static uint8_t
musbotg_dev_ctrl_data_tx(struct musbotg_td * td)781 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
782 {
783 struct usb_page_search buf_res;
784 struct musbotg_softc *sc;
785 uint16_t count;
786 uint8_t csr;
787
788 /* get pointer to softc */
789 sc = MUSBOTG_PC2SC(td->pc);
790
791 /* select endpoint 0 */
792 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
793
794 /* check if a command is pending */
795 if (sc->sc_ep0_cmd) {
796 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
797 sc->sc_ep0_cmd = 0;
798 }
799 /* read out FIFO status */
800 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
801
802 DPRINTFN(4, "csr=0x%02x\n", csr);
803
804 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
805 MUSB2_MASK_CSR0L_SENTSTALL)) {
806 /*
807 * The current transfer was aborted
808 * by the USB Host
809 */
810 td->error = 1;
811 return (0); /* complete */
812 }
813 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
814 return (1); /* not complete */
815 }
816 count = td->max_frame_size;
817 if (td->remainder < count) {
818 /* we have a short packet */
819 td->short_pkt = 1;
820 count = td->remainder;
821 }
822 while (count > 0) {
823 uint32_t temp;
824
825 usbd_get_page(td->pc, td->offset, &buf_res);
826
827 /* get correct length */
828 if (buf_res.length > count) {
829 buf_res.length = count;
830 }
831 /* check for unaligned memory address */
832 if (USB_P2U(buf_res.buffer) & 3) {
833
834 usbd_copy_out(td->pc, td->offset,
835 sc->sc_bounce_buf, count);
836
837 temp = count & ~3;
838
839 if (temp) {
840 /* transmit data 4 bytes at a time */
841 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
842 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
843 temp / 4);
844 }
845 temp = count & 3;
846 if (temp) {
847 /* receive data 1 byte at a time */
848 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
849 MUSB2_REG_EPFIFO(0),
850 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
851 }
852 /* update offset and remainder */
853 td->offset += count;
854 td->remainder -= count;
855 break;
856 }
857 /* check if we can optimise */
858 if (buf_res.length >= 4) {
859
860 /* transmit data 4 bytes at a time */
861 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
862 MUSB2_REG_EPFIFO(0), buf_res.buffer,
863 buf_res.length / 4);
864
865 temp = buf_res.length & ~3;
866
867 /* update counters */
868 count -= temp;
869 td->offset += temp;
870 td->remainder -= temp;
871 continue;
872 }
873 /* transmit data */
874 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
875 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
876
877 /* update counters */
878 count -= buf_res.length;
879 td->offset += buf_res.length;
880 td->remainder -= buf_res.length;
881 }
882
883 /* check remainder */
884 if (td->remainder == 0) {
885 if (td->short_pkt) {
886 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
887 return (0); /* complete */
888 }
889 /* else we need to transmit a short packet */
890 }
891 /* write command */
892 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
893 MUSB2_MASK_CSR0L_TXPKTRDY);
894
895 return (1); /* not complete */
896 }
897
898 static uint8_t
musbotg_host_ctrl_data_rx(struct musbotg_td * td)899 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
900 {
901 struct usb_page_search buf_res;
902 struct musbotg_softc *sc;
903 uint16_t count;
904 uint8_t csr;
905 uint8_t got_short;
906
907 /* get pointer to softc */
908 sc = MUSBOTG_PC2SC(td->pc);
909
910 if (td->channel == -1)
911 td->channel = musbotg_channel_alloc(sc, td, 0);
912
913 /* EP0 is busy, wait */
914 if (td->channel == -1)
915 return (1);
916
917 DPRINTFN(1, "ep_no=%d\n", td->channel);
918
919 /* select endpoint 0 */
920 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
921
922 /* read out FIFO status */
923 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
924
925 DPRINTFN(4, "csr=0x%02x\n", csr);
926
927 got_short = 0;
928 if (!td->transaction_started) {
929 td->transaction_started = 1;
930
931 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
932
933 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
934 td->dev_addr);
935 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
936 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
937 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
938
939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
940 MUSB2_MASK_CSR0L_REQPKT);
941
942 return (1);
943 }
944
945 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
946 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
947 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
948
949 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
950 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
951
952 td->error = 1;
953 }
954
955 /* Failed */
956 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
957 MUSB2_MASK_CSR0L_ERROR))
958 {
959 /* Clear status bit */
960 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
961 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
962 td->error = 1;
963 }
964
965 if (td->error) {
966 musbotg_channel_free(sc, td);
967 return (0); /* we are complete */
968 }
969
970 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
971 return (1); /* not yet */
972
973 /* get the packet byte count */
974 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
975
976 /* verify the packet byte count */
977 if (count != td->max_frame_size) {
978 if (count < td->max_frame_size) {
979 /* we have a short packet */
980 td->short_pkt = 1;
981 got_short = 1;
982 } else {
983 /* invalid USB packet */
984 td->error = 1;
985 musbotg_channel_free(sc, td);
986 return (0); /* we are complete */
987 }
988 }
989 /* verify the packet byte count */
990 if (count > td->remainder) {
991 /* invalid USB packet */
992 td->error = 1;
993 musbotg_channel_free(sc, td);
994 return (0); /* we are complete */
995 }
996 while (count > 0) {
997 uint32_t temp;
998
999 usbd_get_page(td->pc, td->offset, &buf_res);
1000
1001 /* get correct length */
1002 if (buf_res.length > count) {
1003 buf_res.length = count;
1004 }
1005 /* check for unaligned memory address */
1006 if (USB_P2U(buf_res.buffer) & 3) {
1007
1008 temp = count & ~3;
1009
1010 if (temp) {
1011 /* receive data 4 bytes at a time */
1012 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1013 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
1014 temp / 4);
1015 }
1016 temp = count & 3;
1017 if (temp) {
1018 /* receive data 1 byte at a time */
1019 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1020 MUSB2_REG_EPFIFO(0),
1021 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1022 }
1023 usbd_copy_in(td->pc, td->offset,
1024 sc->sc_bounce_buf, count);
1025
1026 /* update offset and remainder */
1027 td->offset += count;
1028 td->remainder -= count;
1029 break;
1030 }
1031 /* check if we can optimise */
1032 if (buf_res.length >= 4) {
1033
1034 /* receive data 4 bytes at a time */
1035 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1036 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1037 buf_res.length / 4);
1038
1039 temp = buf_res.length & ~3;
1040
1041 /* update counters */
1042 count -= temp;
1043 td->offset += temp;
1044 td->remainder -= temp;
1045 continue;
1046 }
1047 /* receive data */
1048 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1049 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1050
1051 /* update counters */
1052 count -= buf_res.length;
1053 td->offset += buf_res.length;
1054 td->remainder -= buf_res.length;
1055 }
1056
1057 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1058 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1059
1060 /* check if we are complete */
1061 if ((td->remainder == 0) || got_short) {
1062 if (td->short_pkt) {
1063 /* we are complete */
1064
1065 musbotg_channel_free(sc, td);
1066 return (0);
1067 }
1068 /* else need to receive a zero length packet */
1069 }
1070
1071 td->transaction_started = 1;
1072 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1073 MUSB2_MASK_CSR0L_REQPKT);
1074
1075 return (1); /* not complete */
1076 }
1077
1078 static uint8_t
musbotg_host_ctrl_data_tx(struct musbotg_td * td)1079 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1080 {
1081 struct usb_page_search buf_res;
1082 struct musbotg_softc *sc;
1083 uint16_t count;
1084 uint8_t csr, csrh;
1085
1086 /* get pointer to softc */
1087 sc = MUSBOTG_PC2SC(td->pc);
1088
1089 if (td->channel == -1)
1090 td->channel = musbotg_channel_alloc(sc, td, 1);
1091
1092 /* No free EPs */
1093 if (td->channel == -1)
1094 return (1);
1095
1096 DPRINTFN(1, "ep_no=%d\n", td->channel);
1097
1098 /* select endpoint */
1099 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1100
1101 /* read out FIFO status */
1102 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1103 DPRINTFN(4, "csr=0x%02x\n", csr);
1104
1105 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1106 MUSB2_MASK_CSR0L_ERROR)) {
1107 /* clear status bits */
1108 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1109 td->error = 1;
1110 }
1111
1112 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1113
1114 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1115 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1116 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1117 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1118 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1119 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1120 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1121 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1122 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1123 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1124 }
1125 }
1126
1127 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1128 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1129
1130 td->error = 1;
1131 }
1132
1133
1134 if (td->error) {
1135 musbotg_channel_free(sc, td);
1136 return (0); /* complete */
1137 }
1138
1139 /*
1140 * Wait while FIFO is empty.
1141 * Do not flush it because it will cause transactions
1142 * with size more then packet size. It might upset
1143 * some devices
1144 */
1145 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1146 return (1);
1147
1148 /* Packet still being processed */
1149 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1150 return (1);
1151
1152 if (td->transaction_started) {
1153 /* check remainder */
1154 if (td->remainder == 0) {
1155 if (td->short_pkt) {
1156 musbotg_channel_free(sc, td);
1157 return (0); /* complete */
1158 }
1159 /* else we need to transmit a short packet */
1160 }
1161
1162 /* We're not complete - more transactions required */
1163 td->transaction_started = 0;
1164 }
1165
1166 /* check for short packet */
1167 count = td->max_frame_size;
1168 if (td->remainder < count) {
1169 /* we have a short packet */
1170 td->short_pkt = 1;
1171 count = td->remainder;
1172 }
1173
1174 while (count > 0) {
1175 uint32_t temp;
1176
1177 usbd_get_page(td->pc, td->offset, &buf_res);
1178
1179 /* get correct length */
1180 if (buf_res.length > count) {
1181 buf_res.length = count;
1182 }
1183 /* check for unaligned memory address */
1184 if (USB_P2U(buf_res.buffer) & 3) {
1185
1186 usbd_copy_out(td->pc, td->offset,
1187 sc->sc_bounce_buf, count);
1188
1189 temp = count & ~3;
1190
1191 if (temp) {
1192 /* transmit data 4 bytes at a time */
1193 bus_space_write_multi_4(sc->sc_io_tag,
1194 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1195 sc->sc_bounce_buf, temp / 4);
1196 }
1197 temp = count & 3;
1198 if (temp) {
1199 /* receive data 1 byte at a time */
1200 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1201 MUSB2_REG_EPFIFO(0),
1202 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1203 }
1204 /* update offset and remainder */
1205 td->offset += count;
1206 td->remainder -= count;
1207 break;
1208 }
1209 /* check if we can optimise */
1210 if (buf_res.length >= 4) {
1211
1212 /* transmit data 4 bytes at a time */
1213 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1214 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1215 buf_res.length / 4);
1216
1217 temp = buf_res.length & ~3;
1218
1219 /* update counters */
1220 count -= temp;
1221 td->offset += temp;
1222 td->remainder -= temp;
1223 continue;
1224 }
1225 /* transmit data */
1226 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1227 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1228 buf_res.length);
1229
1230 /* update counters */
1231 count -= buf_res.length;
1232 td->offset += buf_res.length;
1233 td->remainder -= buf_res.length;
1234 }
1235
1236 /* Function address */
1237 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1238 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1239 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1240 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1241
1242 /* TX NAK timeout */
1243 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1244
1245 /* write command */
1246 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1247 MUSB2_MASK_CSR0L_TXPKTRDY);
1248
1249 td->transaction_started = 1;
1250
1251 return (1); /* not complete */
1252 }
1253
1254 static uint8_t
musbotg_dev_ctrl_status(struct musbotg_td * td)1255 musbotg_dev_ctrl_status(struct musbotg_td *td)
1256 {
1257 struct musbotg_softc *sc;
1258 uint8_t csr;
1259
1260 /* get pointer to softc */
1261 sc = MUSBOTG_PC2SC(td->pc);
1262
1263 /* select endpoint 0 */
1264 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1265
1266 if (sc->sc_ep0_busy) {
1267 sc->sc_ep0_busy = 0;
1268 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1269 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1270 sc->sc_ep0_cmd = 0;
1271 }
1272 /* read out FIFO status */
1273 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1274
1275 DPRINTFN(4, "csr=0x%02x\n", csr);
1276
1277 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1278 /* wait for interrupt */
1279 return (1); /* not complete */
1280 }
1281 if (sc->sc_dv_addr != 0xFF) {
1282 /* write function address */
1283 musbotg_set_address(sc, sc->sc_dv_addr);
1284 }
1285
1286 musbotg_channel_free(sc, td);
1287 return (0); /* complete */
1288 }
1289
1290 static uint8_t
musbotg_host_ctrl_status_rx(struct musbotg_td * td)1291 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1292 {
1293 struct musbotg_softc *sc;
1294 uint8_t csr, csrh;
1295
1296 /* get pointer to softc */
1297 sc = MUSBOTG_PC2SC(td->pc);
1298
1299 if (td->channel == -1)
1300 td->channel = musbotg_channel_alloc(sc, td, 0);
1301
1302 /* EP0 is busy, wait */
1303 if (td->channel == -1)
1304 return (1);
1305
1306 DPRINTFN(1, "ep_no=%d\n", td->channel);
1307
1308 /* select endpoint 0 */
1309 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1310
1311 if (!td->transaction_started) {
1312 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1313 td->dev_addr);
1314
1315 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1316 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1317 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1318
1319 /* RX NAK timeout */
1320 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1321
1322 td->transaction_started = 1;
1323
1324 /* Disable PING */
1325 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1326 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1327 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1328
1329 /* write command */
1330 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1331 MUSB2_MASK_CSR0L_STATUSPKT |
1332 MUSB2_MASK_CSR0L_REQPKT);
1333
1334 return (1); /* Just started */
1335
1336 }
1337
1338 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1339
1340 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1341
1342 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1343 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1344 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1345 musbotg_channel_free(sc, td);
1346 return (0); /* complete */
1347 }
1348
1349 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1350 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1351 MUSB2_MASK_CSR0L_REQPKT);
1352 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1353
1354 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1355 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1356 td->error = 1;
1357 }
1358
1359 /* Failed */
1360 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1361 MUSB2_MASK_CSR0L_ERROR))
1362 {
1363 /* Clear status bit */
1364 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1365 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1366 td->error = 1;
1367 }
1368
1369 if (td->error) {
1370 musbotg_channel_free(sc, td);
1371 return (0);
1372 }
1373
1374 return (1); /* Not ready yet */
1375 }
1376
1377 static uint8_t
musbotg_host_ctrl_status_tx(struct musbotg_td * td)1378 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1379 {
1380 struct musbotg_softc *sc;
1381 uint8_t csr;
1382
1383 /* get pointer to softc */
1384 sc = MUSBOTG_PC2SC(td->pc);
1385
1386 if (td->channel == -1)
1387 td->channel = musbotg_channel_alloc(sc, td, 1);
1388
1389 /* EP0 is busy, wait */
1390 if (td->channel == -1)
1391 return (1);
1392
1393 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1394 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1395
1396 /* select endpoint 0 */
1397 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1398
1399 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1400 DPRINTFN(4, "csr=0x%02x\n", csr);
1401
1402 /* Not yet */
1403 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1404 return (1);
1405
1406 /* Failed */
1407 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1408 MUSB2_MASK_CSR0L_ERROR))
1409 {
1410 /* Clear status bit */
1411 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1412 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1413 td->error = 1;
1414 musbotg_channel_free(sc, td);
1415 return (0); /* complete */
1416 }
1417
1418 if (td->transaction_started) {
1419 musbotg_channel_free(sc, td);
1420 return (0); /* complete */
1421 }
1422
1423 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1424
1425 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1426 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1427 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1428 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1429
1430 /* TX NAK timeout */
1431 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1432
1433 td->transaction_started = 1;
1434
1435 /* write command */
1436 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1437 MUSB2_MASK_CSR0L_STATUSPKT |
1438 MUSB2_MASK_CSR0L_TXPKTRDY);
1439
1440 return (1); /* wait for interrupt */
1441 }
1442
1443 static uint8_t
musbotg_dev_data_rx(struct musbotg_td * td)1444 musbotg_dev_data_rx(struct musbotg_td *td)
1445 {
1446 struct usb_page_search buf_res;
1447 struct musbotg_softc *sc;
1448 uint16_t count;
1449 uint8_t csr;
1450 uint8_t to;
1451 uint8_t got_short;
1452
1453 to = 8; /* don't loop forever! */
1454 got_short = 0;
1455
1456 /* get pointer to softc */
1457 sc = MUSBOTG_PC2SC(td->pc);
1458
1459 if (td->channel == -1)
1460 td->channel = musbotg_channel_alloc(sc, td, 0);
1461
1462 /* EP0 is busy, wait */
1463 if (td->channel == -1)
1464 return (1);
1465
1466 /* select endpoint */
1467 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1468
1469 repeat:
1470 /* read out FIFO status */
1471 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1472
1473 DPRINTFN(4, "csr=0x%02x\n", csr);
1474
1475 /* clear overrun */
1476 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1477 /* make sure we don't clear "RXPKTRDY" */
1478 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1479 MUSB2_MASK_CSRL_RXPKTRDY);
1480 }
1481
1482 /* check status */
1483 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1484 return (1); /* not complete */
1485
1486 /* get the packet byte count */
1487 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1488
1489 DPRINTFN(4, "count=0x%04x\n", count);
1490
1491 /*
1492 * Check for short or invalid packet:
1493 */
1494 if (count != td->max_frame_size) {
1495 if (count < td->max_frame_size) {
1496 /* we have a short packet */
1497 td->short_pkt = 1;
1498 got_short = 1;
1499 } else {
1500 /* invalid USB packet */
1501 td->error = 1;
1502 musbotg_channel_free(sc, td);
1503 return (0); /* we are complete */
1504 }
1505 }
1506 /* verify the packet byte count */
1507 if (count > td->remainder) {
1508 /* invalid USB packet */
1509 td->error = 1;
1510 musbotg_channel_free(sc, td);
1511 return (0); /* we are complete */
1512 }
1513 while (count > 0) {
1514 uint32_t temp;
1515
1516 usbd_get_page(td->pc, td->offset, &buf_res);
1517
1518 /* get correct length */
1519 if (buf_res.length > count) {
1520 buf_res.length = count;
1521 }
1522 /* check for unaligned memory address */
1523 if (USB_P2U(buf_res.buffer) & 3) {
1524
1525 temp = count & ~3;
1526
1527 if (temp) {
1528 /* receive data 4 bytes at a time */
1529 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1530 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1531 temp / 4);
1532 }
1533 temp = count & 3;
1534 if (temp) {
1535 /* receive data 1 byte at a time */
1536 bus_space_read_multi_1(sc->sc_io_tag,
1537 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1538 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1539 }
1540 usbd_copy_in(td->pc, td->offset,
1541 sc->sc_bounce_buf, count);
1542
1543 /* update offset and remainder */
1544 td->offset += count;
1545 td->remainder -= count;
1546 break;
1547 }
1548 /* check if we can optimise */
1549 if (buf_res.length >= 4) {
1550
1551 /* receive data 4 bytes at a time */
1552 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1553 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1554 buf_res.length / 4);
1555
1556 temp = buf_res.length & ~3;
1557
1558 /* update counters */
1559 count -= temp;
1560 td->offset += temp;
1561 td->remainder -= temp;
1562 continue;
1563 }
1564 /* receive data */
1565 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1566 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1567 buf_res.length);
1568
1569 /* update counters */
1570 count -= buf_res.length;
1571 td->offset += buf_res.length;
1572 td->remainder -= buf_res.length;
1573 }
1574
1575 /* clear status bits */
1576 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1577
1578 /* check if we are complete */
1579 if ((td->remainder == 0) || got_short) {
1580 if (td->short_pkt) {
1581 /* we are complete */
1582 musbotg_channel_free(sc, td);
1583 return (0);
1584 }
1585 /* else need to receive a zero length packet */
1586 }
1587 if (--to) {
1588 goto repeat;
1589 }
1590 return (1); /* not complete */
1591 }
1592
1593 static uint8_t
musbotg_dev_data_tx(struct musbotg_td * td)1594 musbotg_dev_data_tx(struct musbotg_td *td)
1595 {
1596 struct usb_page_search buf_res;
1597 struct musbotg_softc *sc;
1598 uint16_t count;
1599 uint8_t csr;
1600 uint8_t to;
1601
1602 to = 8; /* don't loop forever! */
1603
1604 /* get pointer to softc */
1605 sc = MUSBOTG_PC2SC(td->pc);
1606
1607 if (td->channel == -1)
1608 td->channel = musbotg_channel_alloc(sc, td, 1);
1609
1610 /* EP0 is busy, wait */
1611 if (td->channel == -1)
1612 return (1);
1613
1614 /* select endpoint */
1615 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1616
1617 repeat:
1618
1619 /* read out FIFO status */
1620 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1621
1622 DPRINTFN(4, "csr=0x%02x\n", csr);
1623
1624 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1625 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1626 /* clear status bits */
1627 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1628 }
1629 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1630 return (1); /* not complete */
1631 }
1632 /* check for short packet */
1633 count = td->max_frame_size;
1634 if (td->remainder < count) {
1635 /* we have a short packet */
1636 td->short_pkt = 1;
1637 count = td->remainder;
1638 }
1639 while (count > 0) {
1640 uint32_t temp;
1641
1642 usbd_get_page(td->pc, td->offset, &buf_res);
1643
1644 /* get correct length */
1645 if (buf_res.length > count) {
1646 buf_res.length = count;
1647 }
1648 /* check for unaligned memory address */
1649 if (USB_P2U(buf_res.buffer) & 3) {
1650
1651 usbd_copy_out(td->pc, td->offset,
1652 sc->sc_bounce_buf, count);
1653
1654 temp = count & ~3;
1655
1656 if (temp) {
1657 /* transmit data 4 bytes at a time */
1658 bus_space_write_multi_4(sc->sc_io_tag,
1659 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1660 sc->sc_bounce_buf, temp / 4);
1661 }
1662 temp = count & 3;
1663 if (temp) {
1664 /* receive data 1 byte at a time */
1665 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1666 MUSB2_REG_EPFIFO(td->channel),
1667 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1668 }
1669 /* update offset and remainder */
1670 td->offset += count;
1671 td->remainder -= count;
1672 break;
1673 }
1674 /* check if we can optimise */
1675 if (buf_res.length >= 4) {
1676
1677 /* transmit data 4 bytes at a time */
1678 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1679 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1680 buf_res.length / 4);
1681
1682 temp = buf_res.length & ~3;
1683
1684 /* update counters */
1685 count -= temp;
1686 td->offset += temp;
1687 td->remainder -= temp;
1688 continue;
1689 }
1690 /* transmit data */
1691 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1692 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1693 buf_res.length);
1694
1695 /* update counters */
1696 count -= buf_res.length;
1697 td->offset += buf_res.length;
1698 td->remainder -= buf_res.length;
1699 }
1700
1701 /* Max packet size */
1702 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1703
1704 /* write command */
1705 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1706 MUSB2_MASK_CSRL_TXPKTRDY);
1707
1708 /* check remainder */
1709 if (td->remainder == 0) {
1710 if (td->short_pkt) {
1711 musbotg_channel_free(sc, td);
1712 return (0); /* complete */
1713 }
1714 /* else we need to transmit a short packet */
1715 }
1716 if (--to) {
1717 goto repeat;
1718 }
1719 return (1); /* not complete */
1720 }
1721
1722 static uint8_t
musbotg_host_data_rx(struct musbotg_td * td)1723 musbotg_host_data_rx(struct musbotg_td *td)
1724 {
1725 struct usb_page_search buf_res;
1726 struct musbotg_softc *sc;
1727 uint16_t count;
1728 uint8_t csr, csrh;
1729 uint8_t to;
1730 uint8_t got_short;
1731
1732 /* get pointer to softc */
1733 sc = MUSBOTG_PC2SC(td->pc);
1734
1735 if (td->channel == -1)
1736 td->channel = musbotg_channel_alloc(sc, td, 0);
1737
1738 /* No free EPs */
1739 if (td->channel == -1)
1740 return (1);
1741
1742 DPRINTFN(1, "ep_no=%d\n", td->channel);
1743
1744 to = 8; /* don't loop forever! */
1745 got_short = 0;
1746
1747 /* select endpoint */
1748 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1749
1750 repeat:
1751 /* read out FIFO status */
1752 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1753 DPRINTFN(4, "csr=0x%02x\n", csr);
1754
1755 if (!td->transaction_started) {
1756 /* Function address */
1757 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1758 td->dev_addr);
1759
1760 /* SPLIT transaction */
1761 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1762 td->haddr);
1763 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1764 td->hport);
1765
1766 /* RX NAK timeout */
1767 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1768 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1769 else
1770 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1771
1772 /* Protocol, speed, device endpoint */
1773 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1774
1775 /* Max packet size */
1776 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1777
1778 /* Data Toggle */
1779 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1780 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1781
1782 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1783 if (td->toggle)
1784 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1785 else
1786 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1787
1788 /* Set data toggle */
1789 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1790
1791 /* write command */
1792 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1793 MUSB2_MASK_CSRL_RXREQPKT);
1794
1795 td->transaction_started = 1;
1796 return (1);
1797 }
1798
1799 /* clear NAK timeout */
1800 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1801 DPRINTFN(4, "NAK Timeout\n");
1802 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1803 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1804 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1805
1806 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1807 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1808 }
1809
1810 td->error = 1;
1811 }
1812
1813 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1814 DPRINTFN(4, "RXERROR\n");
1815 td->error = 1;
1816 }
1817
1818 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1819 DPRINTFN(4, "RXSTALL\n");
1820 td->error = 1;
1821 }
1822
1823 if (td->error) {
1824 musbotg_channel_free(sc, td);
1825 return (0); /* we are complete */
1826 }
1827
1828 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1829 /* No data available yet */
1830 return (1);
1831 }
1832
1833 td->toggle ^= 1;
1834 /* get the packet byte count */
1835 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1836 DPRINTFN(4, "count=0x%04x\n", count);
1837
1838 /*
1839 * Check for short or invalid packet:
1840 */
1841 if (count != td->max_frame_size) {
1842 if (count < td->max_frame_size) {
1843 /* we have a short packet */
1844 td->short_pkt = 1;
1845 got_short = 1;
1846 } else {
1847 /* invalid USB packet */
1848 td->error = 1;
1849 musbotg_channel_free(sc, td);
1850 return (0); /* we are complete */
1851 }
1852 }
1853
1854 /* verify the packet byte count */
1855 if (count > td->remainder) {
1856 /* invalid USB packet */
1857 td->error = 1;
1858 musbotg_channel_free(sc, td);
1859 return (0); /* we are complete */
1860 }
1861
1862 while (count > 0) {
1863 uint32_t temp;
1864
1865 usbd_get_page(td->pc, td->offset, &buf_res);
1866
1867 /* get correct length */
1868 if (buf_res.length > count) {
1869 buf_res.length = count;
1870 }
1871 /* check for unaligned memory address */
1872 if (USB_P2U(buf_res.buffer) & 3) {
1873
1874 temp = count & ~3;
1875
1876 if (temp) {
1877 /* receive data 4 bytes at a time */
1878 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1879 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1880 temp / 4);
1881 }
1882 temp = count & 3;
1883 if (temp) {
1884 /* receive data 1 byte at a time */
1885 bus_space_read_multi_1(sc->sc_io_tag,
1886 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1887 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1888 }
1889 usbd_copy_in(td->pc, td->offset,
1890 sc->sc_bounce_buf, count);
1891
1892 /* update offset and remainder */
1893 td->offset += count;
1894 td->remainder -= count;
1895 break;
1896 }
1897 /* check if we can optimise */
1898 if (buf_res.length >= 4) {
1899
1900 /* receive data 4 bytes at a time */
1901 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1902 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1903 buf_res.length / 4);
1904
1905 temp = buf_res.length & ~3;
1906
1907 /* update counters */
1908 count -= temp;
1909 td->offset += temp;
1910 td->remainder -= temp;
1911 continue;
1912 }
1913 /* receive data */
1914 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1915 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1916 buf_res.length);
1917
1918 /* update counters */
1919 count -= buf_res.length;
1920 td->offset += buf_res.length;
1921 td->remainder -= buf_res.length;
1922 }
1923
1924 /* clear status bits */
1925 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1926
1927 /* check if we are complete */
1928 if ((td->remainder == 0) || got_short) {
1929 if (td->short_pkt) {
1930 /* we are complete */
1931 musbotg_channel_free(sc, td);
1932 return (0);
1933 }
1934 /* else need to receive a zero length packet */
1935 }
1936
1937 /* Reset transaction state and restart */
1938 td->transaction_started = 0;
1939
1940 if (--to)
1941 goto repeat;
1942
1943 return (1); /* not complete */
1944 }
1945
1946 static uint8_t
musbotg_host_data_tx(struct musbotg_td * td)1947 musbotg_host_data_tx(struct musbotg_td *td)
1948 {
1949 struct usb_page_search buf_res;
1950 struct musbotg_softc *sc;
1951 uint16_t count;
1952 uint8_t csr, csrh;
1953
1954 /* get pointer to softc */
1955 sc = MUSBOTG_PC2SC(td->pc);
1956
1957 if (td->channel == -1)
1958 td->channel = musbotg_channel_alloc(sc, td, 1);
1959
1960 /* No free EPs */
1961 if (td->channel == -1)
1962 return (1);
1963
1964 DPRINTFN(1, "ep_no=%d\n", td->channel);
1965
1966 /* select endpoint */
1967 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1968
1969 /* read out FIFO status */
1970 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1971 DPRINTFN(4, "csr=0x%02x\n", csr);
1972
1973 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1974 MUSB2_MASK_CSRL_TXERROR)) {
1975 /* clear status bits */
1976 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1977 td->error = 1;
1978 musbotg_channel_free(sc, td);
1979 return (0); /* complete */
1980 }
1981
1982 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1983 /*
1984 * Flush TX FIFO before clearing NAK TO
1985 */
1986 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1987 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1988 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1989 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1990 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1991 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1992 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1993 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1994 }
1995 }
1996
1997 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1998 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1999
2000 td->error = 1;
2001 musbotg_channel_free(sc, td);
2002 return (0); /* complete */
2003 }
2004
2005 /*
2006 * Wait while FIFO is empty.
2007 * Do not flush it because it will cause transactions
2008 * with size more then packet size. It might upset
2009 * some devices
2010 */
2011 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
2012 return (1);
2013
2014 /* Packet still being processed */
2015 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
2016 return (1);
2017
2018 if (td->transaction_started) {
2019 /* check remainder */
2020 if (td->remainder == 0) {
2021 if (td->short_pkt) {
2022 musbotg_channel_free(sc, td);
2023 return (0); /* complete */
2024 }
2025 /* else we need to transmit a short packet */
2026 }
2027
2028 /* We're not complete - more transactions required */
2029 td->transaction_started = 0;
2030 }
2031
2032 /* check for short packet */
2033 count = td->max_frame_size;
2034 if (td->remainder < count) {
2035 /* we have a short packet */
2036 td->short_pkt = 1;
2037 count = td->remainder;
2038 }
2039
2040 while (count > 0) {
2041 uint32_t temp;
2042
2043 usbd_get_page(td->pc, td->offset, &buf_res);
2044
2045 /* get correct length */
2046 if (buf_res.length > count) {
2047 buf_res.length = count;
2048 }
2049 /* check for unaligned memory address */
2050 if (USB_P2U(buf_res.buffer) & 3) {
2051
2052 usbd_copy_out(td->pc, td->offset,
2053 sc->sc_bounce_buf, count);
2054
2055 temp = count & ~3;
2056
2057 if (temp) {
2058 /* transmit data 4 bytes at a time */
2059 bus_space_write_multi_4(sc->sc_io_tag,
2060 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2061 sc->sc_bounce_buf, temp / 4);
2062 }
2063 temp = count & 3;
2064 if (temp) {
2065 /* receive data 1 byte at a time */
2066 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2067 MUSB2_REG_EPFIFO(td->channel),
2068 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2069 }
2070 /* update offset and remainder */
2071 td->offset += count;
2072 td->remainder -= count;
2073 break;
2074 }
2075 /* check if we can optimise */
2076 if (buf_res.length >= 4) {
2077
2078 /* transmit data 4 bytes at a time */
2079 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2080 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2081 buf_res.length / 4);
2082
2083 temp = buf_res.length & ~3;
2084
2085 /* update counters */
2086 count -= temp;
2087 td->offset += temp;
2088 td->remainder -= temp;
2089 continue;
2090 }
2091 /* transmit data */
2092 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2093 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2094 buf_res.length);
2095
2096 /* update counters */
2097 count -= buf_res.length;
2098 td->offset += buf_res.length;
2099 td->remainder -= buf_res.length;
2100 }
2101
2102 /* Function address */
2103 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2104 td->dev_addr);
2105
2106 /* SPLIT transaction */
2107 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2108 td->haddr);
2109 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2110 td->hport);
2111
2112 /* TX NAK timeout */
2113 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2114 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2115 else
2116 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2117
2118 /* Protocol, speed, device endpoint */
2119 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2120
2121 /* Max packet size */
2122 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2123
2124 if (!td->transaction_started) {
2125 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2126 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2127
2128 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2129 if (td->toggle)
2130 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2131 else
2132 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2133
2134 /* Set data toggle */
2135 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2136 }
2137
2138 /* write command */
2139 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2140 MUSB2_MASK_CSRL_TXPKTRDY);
2141
2142 /* Update Data Toggle */
2143 td->toggle ^= 1;
2144 td->transaction_started = 1;
2145
2146 return (1); /* not complete */
2147 }
2148
2149 static uint8_t
musbotg_xfer_do_fifo(struct usb_xfer * xfer)2150 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2151 {
2152 struct musbotg_softc *sc;
2153 struct musbotg_td *td;
2154
2155 DPRINTFN(8, "\n");
2156 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2157
2158 td = xfer->td_transfer_cache;
2159 while (1) {
2160
2161 if ((td->func) (td)) {
2162 /* operation in progress */
2163 break;
2164 }
2165
2166 if (((void *)td) == xfer->td_transfer_last) {
2167 goto done;
2168 }
2169 if (td->error) {
2170 goto done;
2171 } else if (td->remainder > 0) {
2172 /*
2173 * We had a short transfer. If there is no alternate
2174 * next, stop processing !
2175 */
2176 if (!td->alt_next) {
2177 goto done;
2178 }
2179 }
2180 /*
2181 * Fetch the next transfer descriptor and transfer
2182 * some flags to the next transfer descriptor
2183 */
2184 td = td->obj_next;
2185 xfer->td_transfer_cache = td;
2186 }
2187
2188 return (1); /* not complete */
2189 done:
2190 /* compute all actual lengths */
2191 musbotg_standard_done(xfer);
2192
2193 return (0); /* complete */
2194 }
2195
2196 static void
musbotg_interrupt_poll(struct musbotg_softc * sc)2197 musbotg_interrupt_poll(struct musbotg_softc *sc)
2198 {
2199 struct usb_xfer *xfer;
2200
2201 repeat:
2202 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2203 if (!musbotg_xfer_do_fifo(xfer)) {
2204 /* queue has been modified */
2205 goto repeat;
2206 }
2207 }
2208 }
2209
2210 void
musbotg_vbus_interrupt(struct musbotg_softc * sc,uint8_t is_on)2211 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2212 {
2213 DPRINTFN(4, "vbus = %u\n", is_on);
2214
2215 USB_BUS_LOCK(&sc->sc_bus);
2216 if (is_on) {
2217 if (!sc->sc_flags.status_vbus) {
2218 sc->sc_flags.status_vbus = 1;
2219
2220 /* complete root HUB interrupt endpoint */
2221 musbotg_root_intr(sc);
2222 }
2223 } else {
2224 if (sc->sc_flags.status_vbus) {
2225 sc->sc_flags.status_vbus = 0;
2226 sc->sc_flags.status_bus_reset = 0;
2227 sc->sc_flags.status_suspend = 0;
2228 sc->sc_flags.change_suspend = 0;
2229 sc->sc_flags.change_connect = 1;
2230
2231 /* complete root HUB interrupt endpoint */
2232 musbotg_root_intr(sc);
2233 }
2234 }
2235
2236 USB_BUS_UNLOCK(&sc->sc_bus);
2237 }
2238
2239 void
musbotg_connect_interrupt(struct musbotg_softc * sc)2240 musbotg_connect_interrupt(struct musbotg_softc *sc)
2241 {
2242 USB_BUS_LOCK(&sc->sc_bus);
2243 sc->sc_flags.change_connect = 1;
2244
2245 /* complete root HUB interrupt endpoint */
2246 musbotg_root_intr(sc);
2247 USB_BUS_UNLOCK(&sc->sc_bus);
2248 }
2249
2250 void
musbotg_interrupt(struct musbotg_softc * sc,uint16_t rxstat,uint16_t txstat,uint8_t stat)2251 musbotg_interrupt(struct musbotg_softc *sc,
2252 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2253 {
2254 uint16_t rx_status;
2255 uint16_t tx_status;
2256 uint8_t usb_status;
2257 uint8_t temp;
2258 uint8_t to = 2;
2259
2260 USB_BUS_LOCK(&sc->sc_bus);
2261
2262 repeat:
2263
2264 /* read all interrupt registers */
2265 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2266
2267 /* read all FIFO interrupts */
2268 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2269 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2270 rx_status |= rxstat;
2271 tx_status |= txstat;
2272 usb_status |= stat;
2273
2274 /* Clear platform flags after first time */
2275 rxstat = 0;
2276 txstat = 0;
2277 stat = 0;
2278
2279 /* check for any bus state change interrupts */
2280
2281 if (usb_status & (MUSB2_MASK_IRESET |
2282 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2283 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2284 MUSB2_MASK_IVBUSERR)) {
2285
2286 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2287
2288 if (usb_status & MUSB2_MASK_IRESET) {
2289
2290 /* set correct state */
2291 sc->sc_flags.status_bus_reset = 1;
2292 sc->sc_flags.status_suspend = 0;
2293 sc->sc_flags.change_suspend = 0;
2294 sc->sc_flags.change_connect = 1;
2295
2296 /* determine line speed */
2297 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2298 if (temp & MUSB2_MASK_HSMODE)
2299 sc->sc_flags.status_high_speed = 1;
2300 else
2301 sc->sc_flags.status_high_speed = 0;
2302
2303 /*
2304 * After reset all interrupts are on and we need to
2305 * turn them off!
2306 */
2307 temp = MUSB2_MASK_IRESET;
2308 /* disable resume interrupt */
2309 temp &= ~MUSB2_MASK_IRESUME;
2310 /* enable suspend interrupt */
2311 temp |= MUSB2_MASK_ISUSP;
2312 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2313 /* disable TX and RX interrupts */
2314 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2315 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2316 }
2317 /*
2318 * If RXRSM and RXSUSP is set at the same time we interpret
2319 * that like RESUME. Resume is set when there is at least 3
2320 * milliseconds of inactivity on the USB BUS.
2321 */
2322 if (usb_status & MUSB2_MASK_IRESUME) {
2323 if (sc->sc_flags.status_suspend) {
2324 sc->sc_flags.status_suspend = 0;
2325 sc->sc_flags.change_suspend = 1;
2326
2327 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2328 /* disable resume interrupt */
2329 temp &= ~MUSB2_MASK_IRESUME;
2330 /* enable suspend interrupt */
2331 temp |= MUSB2_MASK_ISUSP;
2332 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2333 }
2334 } else if (usb_status & MUSB2_MASK_ISUSP) {
2335 if (!sc->sc_flags.status_suspend) {
2336 sc->sc_flags.status_suspend = 1;
2337 sc->sc_flags.change_suspend = 1;
2338
2339 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2340 /* disable suspend interrupt */
2341 temp &= ~MUSB2_MASK_ISUSP;
2342 /* enable resume interrupt */
2343 temp |= MUSB2_MASK_IRESUME;
2344 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2345 }
2346 }
2347 if (usb_status &
2348 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2349 sc->sc_flags.change_connect = 1;
2350
2351 /*
2352 * Host Mode: There is no IRESET so assume bus is
2353 * always in reset state once device is connected.
2354 */
2355 if (sc->sc_mode == MUSB2_HOST_MODE) {
2356 /* check for VBUS error in USB host mode */
2357 if (usb_status & MUSB2_MASK_IVBUSERR) {
2358 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2359 temp |= MUSB2_MASK_SESS;
2360 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2361 }
2362 if (usb_status & MUSB2_MASK_ICONN)
2363 sc->sc_flags.status_bus_reset = 1;
2364 if (usb_status & MUSB2_MASK_IDISC)
2365 sc->sc_flags.status_bus_reset = 0;
2366 }
2367
2368 /* complete root HUB interrupt endpoint */
2369 musbotg_root_intr(sc);
2370 }
2371 /* check for any endpoint interrupts */
2372
2373 if (rx_status || tx_status) {
2374 DPRINTFN(4, "real endpoint interrupt "
2375 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2376 }
2377 /* poll one time regardless of FIFO status */
2378
2379 musbotg_interrupt_poll(sc);
2380
2381 if (--to)
2382 goto repeat;
2383
2384 USB_BUS_UNLOCK(&sc->sc_bus);
2385 }
2386
2387 static void
musbotg_setup_standard_chain_sub(struct musbotg_std_temp * temp)2388 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2389 {
2390 struct musbotg_td *td;
2391
2392 /* get current Transfer Descriptor */
2393 td = temp->td_next;
2394 temp->td = td;
2395
2396 /* prepare for next TD */
2397 temp->td_next = td->obj_next;
2398
2399 /* fill out the Transfer Descriptor */
2400 td->func = temp->func;
2401 td->pc = temp->pc;
2402 td->offset = temp->offset;
2403 td->remainder = temp->len;
2404 td->error = 0;
2405 td->transaction_started = 0;
2406 td->did_stall = temp->did_stall;
2407 td->short_pkt = temp->short_pkt;
2408 td->alt_next = temp->setup_alt_next;
2409 td->channel = temp->channel;
2410 td->dev_addr = temp->dev_addr;
2411 td->haddr = temp->haddr;
2412 td->hport = temp->hport;
2413 td->transfer_type = temp->transfer_type;
2414 }
2415
2416 static void
musbotg_setup_standard_chain(struct usb_xfer * xfer)2417 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2418 {
2419 struct musbotg_std_temp temp;
2420 struct musbotg_softc *sc;
2421 struct musbotg_td *td;
2422 uint32_t x;
2423 uint8_t ep_no;
2424 uint8_t xfer_type;
2425 enum usb_dev_speed speed;
2426 int tx;
2427 int dev_addr;
2428
2429 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2430 xfer->address, UE_GET_ADDR(xfer->endpointno),
2431 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2432
2433 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2434 ep_no = (xfer->endpointno & UE_ADDR);
2435
2436 temp.max_frame_size = xfer->max_frame_size;
2437
2438 td = xfer->td_start[0];
2439 xfer->td_transfer_first = td;
2440 xfer->td_transfer_cache = td;
2441
2442 /* setup temp */
2443 dev_addr = xfer->address;
2444
2445 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2446
2447 temp.pc = NULL;
2448 temp.td = NULL;
2449 temp.td_next = xfer->td_start[0];
2450 temp.offset = 0;
2451 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2452 xfer->flags_int.isochronous_xfr;
2453 temp.did_stall = !xfer->flags_int.control_stall;
2454 temp.channel = -1;
2455 temp.dev_addr = dev_addr;
2456 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2457 temp.hport = xfer->xroot->udev->hs_port_no;
2458
2459 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2460 speed = usbd_get_speed(xfer->xroot->udev);
2461
2462 switch (speed) {
2463 case USB_SPEED_LOW:
2464 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2465 break;
2466 case USB_SPEED_FULL:
2467 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2468 break;
2469 case USB_SPEED_HIGH:
2470 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2471 break;
2472 default:
2473 temp.transfer_type = 0;
2474 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2475 break;
2476 }
2477
2478 switch (xfer_type) {
2479 case UE_CONTROL:
2480 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2481 break;
2482 case UE_ISOCHRONOUS:
2483 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2484 break;
2485 case UE_BULK:
2486 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2487 break;
2488 case UE_INTERRUPT:
2489 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2490 break;
2491 default:
2492 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2493 xfer_type);
2494 break;
2495 }
2496
2497 temp.transfer_type |= ep_no;
2498 td->toggle = xfer->endpoint->toggle_next;
2499 }
2500
2501 /* check if we should prepend a setup message */
2502
2503 if (xfer->flags_int.control_xfr) {
2504 if (xfer->flags_int.control_hdr) {
2505
2506 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2507 temp.func = &musbotg_dev_ctrl_setup_rx;
2508 else
2509 temp.func = &musbotg_host_ctrl_setup_tx;
2510
2511 temp.len = xfer->frlengths[0];
2512 temp.pc = xfer->frbuffers + 0;
2513 temp.short_pkt = temp.len ? 1 : 0;
2514
2515 musbotg_setup_standard_chain_sub(&temp);
2516 }
2517 x = 1;
2518 } else {
2519 x = 0;
2520 }
2521
2522 tx = 0;
2523
2524 if (x != xfer->nframes) {
2525 if (xfer->endpointno & UE_DIR_IN)
2526 tx = 1;
2527
2528 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2529 tx = !tx;
2530
2531 if (tx) {
2532 if (xfer->flags_int.control_xfr)
2533 temp.func = &musbotg_host_ctrl_data_tx;
2534 else
2535 temp.func = &musbotg_host_data_tx;
2536 } else {
2537 if (xfer->flags_int.control_xfr)
2538 temp.func = &musbotg_host_ctrl_data_rx;
2539 else
2540 temp.func = &musbotg_host_data_rx;
2541 }
2542
2543 } else {
2544 if (tx) {
2545 if (xfer->flags_int.control_xfr)
2546 temp.func = &musbotg_dev_ctrl_data_tx;
2547 else
2548 temp.func = &musbotg_dev_data_tx;
2549 } else {
2550 if (xfer->flags_int.control_xfr)
2551 temp.func = &musbotg_dev_ctrl_data_rx;
2552 else
2553 temp.func = &musbotg_dev_data_rx;
2554 }
2555 }
2556
2557 /* setup "pc" pointer */
2558 temp.pc = xfer->frbuffers + x;
2559 }
2560 while (x != xfer->nframes) {
2561
2562 /* DATA0 / DATA1 message */
2563
2564 temp.len = xfer->frlengths[x];
2565
2566 x++;
2567
2568 if (x == xfer->nframes) {
2569 if (xfer->flags_int.control_xfr) {
2570 if (xfer->flags_int.control_act) {
2571 temp.setup_alt_next = 0;
2572 }
2573 } else {
2574 temp.setup_alt_next = 0;
2575 }
2576 }
2577 if (temp.len == 0) {
2578
2579 /* make sure that we send an USB packet */
2580
2581 temp.short_pkt = 0;
2582
2583 } else {
2584
2585 if (xfer->flags_int.isochronous_xfr) {
2586 /* isochronous data transfer */
2587 /* don't force short */
2588 temp.short_pkt = 1;
2589 } else {
2590 /* regular data transfer */
2591 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2592 }
2593 }
2594
2595 musbotg_setup_standard_chain_sub(&temp);
2596
2597 if (xfer->flags_int.isochronous_xfr) {
2598 temp.offset += temp.len;
2599 } else {
2600 /* get next Page Cache pointer */
2601 temp.pc = xfer->frbuffers + x;
2602 }
2603 }
2604
2605 /* check for control transfer */
2606 if (xfer->flags_int.control_xfr) {
2607
2608 /* always setup a valid "pc" pointer for status and sync */
2609 temp.pc = xfer->frbuffers + 0;
2610 temp.len = 0;
2611 temp.short_pkt = 0;
2612 temp.setup_alt_next = 0;
2613
2614 /* check if we should append a status stage */
2615 if (!xfer->flags_int.control_act) {
2616 /*
2617 * Send a DATA1 message and invert the current
2618 * endpoint direction.
2619 */
2620 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2621 temp.func = &musbotg_dev_ctrl_status;
2622 else {
2623 if (xfer->endpointno & UE_DIR_IN)
2624 temp.func = musbotg_host_ctrl_status_tx;
2625 else
2626 temp.func = musbotg_host_ctrl_status_rx;
2627 }
2628 musbotg_setup_standard_chain_sub(&temp);
2629 }
2630 }
2631 /* must have at least one frame! */
2632 td = temp.td;
2633 xfer->td_transfer_last = td;
2634 }
2635
2636 static void
musbotg_timeout(void * arg)2637 musbotg_timeout(void *arg)
2638 {
2639 struct usb_xfer *xfer = arg;
2640
2641 DPRINTFN(1, "xfer=%p\n", xfer);
2642
2643 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2644
2645 /* transfer is transferred */
2646 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2647 }
2648
2649 static void
musbotg_ep_int_set(struct musbotg_softc * sc,int channel,int on)2650 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2651 {
2652 uint16_t temp;
2653
2654 /*
2655 * Only enable the endpoint interrupt when we are
2656 * actually waiting for data, hence we are dealing
2657 * with level triggered interrupts !
2658 */
2659 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2660
2661 if (channel == -1)
2662 return;
2663
2664 if (channel == 0) {
2665 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2666 if (on)
2667 temp |= MUSB2_MASK_EPINT(0);
2668 else
2669 temp &= ~MUSB2_MASK_EPINT(0);
2670
2671 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2672 } else {
2673 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2674 if (on)
2675 temp |= MUSB2_MASK_EPINT(channel);
2676 else
2677 temp &= ~MUSB2_MASK_EPINT(channel);
2678 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2679
2680 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2681 if (on)
2682 temp |= MUSB2_MASK_EPINT(channel);
2683 else
2684 temp &= ~MUSB2_MASK_EPINT(channel);
2685 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2686 }
2687
2688 if (sc->sc_ep_int_set)
2689 sc->sc_ep_int_set(sc, channel, on);
2690 }
2691
2692 static void
musbotg_start_standard_chain(struct usb_xfer * xfer)2693 musbotg_start_standard_chain(struct usb_xfer *xfer)
2694 {
2695 DPRINTFN(8, "\n");
2696
2697 /* poll one time */
2698 if (musbotg_xfer_do_fifo(xfer)) {
2699
2700 DPRINTFN(14, "enabled interrupts on endpoint\n");
2701
2702 /* put transfer on interrupt queue */
2703 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2704
2705 /* start timeout, if any */
2706 if (xfer->timeout != 0) {
2707 usbd_transfer_timeout_ms(xfer,
2708 &musbotg_timeout, xfer->timeout);
2709 }
2710 }
2711 }
2712
2713 static void
musbotg_root_intr(struct musbotg_softc * sc)2714 musbotg_root_intr(struct musbotg_softc *sc)
2715 {
2716 DPRINTFN(8, "\n");
2717
2718 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2719
2720 /* set port bit */
2721 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2722
2723 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2724 sizeof(sc->sc_hub_idata));
2725 }
2726
2727 static usb_error_t
musbotg_standard_done_sub(struct usb_xfer * xfer)2728 musbotg_standard_done_sub(struct usb_xfer *xfer)
2729 {
2730 struct musbotg_td *td;
2731 uint32_t len;
2732 uint8_t error;
2733
2734 DPRINTFN(8, "\n");
2735
2736 td = xfer->td_transfer_cache;
2737
2738 do {
2739 len = td->remainder;
2740
2741 xfer->endpoint->toggle_next = td->toggle;
2742
2743 if (xfer->aframes != xfer->nframes) {
2744 /*
2745 * Verify the length and subtract
2746 * the remainder from "frlengths[]":
2747 */
2748 if (len > xfer->frlengths[xfer->aframes]) {
2749 td->error = 1;
2750 } else {
2751 xfer->frlengths[xfer->aframes] -= len;
2752 }
2753 }
2754 /* Check for transfer error */
2755 if (td->error) {
2756 /* the transfer is finished */
2757 error = 1;
2758 td = NULL;
2759 break;
2760 }
2761 /* Check for short transfer */
2762 if (len > 0) {
2763 if (xfer->flags_int.short_frames_ok ||
2764 xfer->flags_int.isochronous_xfr) {
2765 /* follow alt next */
2766 if (td->alt_next) {
2767 td = td->obj_next;
2768 } else {
2769 td = NULL;
2770 }
2771 } else {
2772 /* the transfer is finished */
2773 td = NULL;
2774 }
2775 error = 0;
2776 break;
2777 }
2778 td = td->obj_next;
2779
2780 /* this USB frame is complete */
2781 error = 0;
2782 break;
2783
2784 } while (0);
2785
2786 /* update transfer cache */
2787
2788 xfer->td_transfer_cache = td;
2789
2790 return (error ?
2791 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2792 }
2793
2794 static void
musbotg_standard_done(struct usb_xfer * xfer)2795 musbotg_standard_done(struct usb_xfer *xfer)
2796 {
2797 usb_error_t err = 0;
2798
2799 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2800 xfer, xfer->endpoint);
2801
2802 /* reset scanner */
2803
2804 xfer->td_transfer_cache = xfer->td_transfer_first;
2805
2806 if (xfer->flags_int.control_xfr) {
2807
2808 if (xfer->flags_int.control_hdr) {
2809
2810 err = musbotg_standard_done_sub(xfer);
2811 }
2812 xfer->aframes = 1;
2813
2814 if (xfer->td_transfer_cache == NULL) {
2815 goto done;
2816 }
2817 }
2818 while (xfer->aframes != xfer->nframes) {
2819
2820 err = musbotg_standard_done_sub(xfer);
2821 xfer->aframes++;
2822
2823 if (xfer->td_transfer_cache == NULL) {
2824 goto done;
2825 }
2826 }
2827
2828 if (xfer->flags_int.control_xfr &&
2829 !xfer->flags_int.control_act) {
2830
2831 err = musbotg_standard_done_sub(xfer);
2832 }
2833 done:
2834 musbotg_device_done(xfer, err);
2835 }
2836
2837 /*------------------------------------------------------------------------*
2838 * musbotg_device_done
2839 *
2840 * NOTE: this function can be called more than one time on the
2841 * same USB transfer!
2842 *------------------------------------------------------------------------*/
2843 static void
musbotg_device_done(struct usb_xfer * xfer,usb_error_t error)2844 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2845 {
2846 struct musbotg_td *td;
2847 struct musbotg_softc *sc;
2848
2849 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2850
2851 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2852 xfer, xfer->endpoint, error);
2853
2854 DPRINTFN(14, "disabled interrupts on endpoint\n");
2855
2856 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2857 td = xfer->td_transfer_cache;
2858
2859 if (td && (td->channel != -1))
2860 musbotg_channel_free(sc, td);
2861
2862 /* dequeue transfer and start next transfer */
2863 usbd_transfer_done(xfer, error);
2864 }
2865
2866 static void
musbotg_xfer_stall(struct usb_xfer * xfer)2867 musbotg_xfer_stall(struct usb_xfer *xfer)
2868 {
2869 musbotg_device_done(xfer, USB_ERR_STALLED);
2870 }
2871
2872 static void
musbotg_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)2873 musbotg_set_stall(struct usb_device *udev,
2874 struct usb_endpoint *ep, uint8_t *did_stall)
2875 {
2876 struct musbotg_softc *sc;
2877 uint8_t ep_no;
2878
2879 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2880
2881 DPRINTFN(4, "endpoint=%p\n", ep);
2882
2883 /* set FORCESTALL */
2884 sc = MUSBOTG_BUS2SC(udev->bus);
2885
2886 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2887
2888 /* select endpoint */
2889 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2890
2891 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2892 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2893 MUSB2_MASK_CSRL_TXSENDSTALL);
2894 } else {
2895 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2896 MUSB2_MASK_CSRL_RXSENDSTALL);
2897 }
2898 }
2899
2900 static void
musbotg_clear_stall_sub(struct musbotg_softc * sc,uint16_t wMaxPacket,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)2901 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2902 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2903 {
2904 uint16_t mps;
2905 uint16_t temp;
2906 uint8_t csr;
2907
2908 if (ep_type == UE_CONTROL) {
2909 /* clearing stall is not needed */
2910 return;
2911 }
2912 /* select endpoint */
2913 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2914
2915 /* compute max frame size */
2916 mps = wMaxPacket & 0x7FF;
2917 switch ((wMaxPacket >> 11) & 3) {
2918 case 1:
2919 mps *= 2;
2920 break;
2921 case 2:
2922 mps *= 3;
2923 break;
2924 default:
2925 break;
2926 }
2927
2928 if (ep_dir == UE_DIR_IN) {
2929
2930 temp = 0;
2931
2932 /* Configure endpoint */
2933 switch (ep_type) {
2934 case UE_INTERRUPT:
2935 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2936 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2937 MUSB2_MASK_CSRH_TXMODE | temp);
2938 break;
2939 case UE_ISOCHRONOUS:
2940 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2941 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2942 MUSB2_MASK_CSRH_TXMODE |
2943 MUSB2_MASK_CSRH_TXISO | temp);
2944 break;
2945 case UE_BULK:
2946 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2947 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2948 MUSB2_MASK_CSRH_TXMODE | temp);
2949 break;
2950 default:
2951 break;
2952 }
2953
2954 /* Need to flush twice in case of double bufring */
2955 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2956 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2957 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2958 MUSB2_MASK_CSRL_TXFFLUSH);
2959 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2960 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2961 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2962 MUSB2_MASK_CSRL_TXFFLUSH);
2963 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2964 }
2965 }
2966 /* reset data toggle */
2967 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2968 MUSB2_MASK_CSRL_TXDT_CLR);
2969 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2970 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2971
2972 /* set double/single buffering */
2973 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2974 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2975 max_in_frame_size / 2)) {
2976 /* double buffer */
2977 temp &= ~(1 << ep_no);
2978 } else {
2979 /* single buffer */
2980 temp |= (1 << ep_no);
2981 }
2982 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2983
2984 /* clear sent stall */
2985 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2986 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2987 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2988 }
2989 } else {
2990
2991 temp = 0;
2992
2993 /* Configure endpoint */
2994 switch (ep_type) {
2995 case UE_INTERRUPT:
2996 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2997 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2998 MUSB2_MASK_CSRH_RXNYET | temp);
2999 break;
3000 case UE_ISOCHRONOUS:
3001 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
3002 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
3003 MUSB2_MASK_CSRH_RXNYET |
3004 MUSB2_MASK_CSRH_RXISO | temp);
3005 break;
3006 case UE_BULK:
3007 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
3008 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
3009 break;
3010 default:
3011 break;
3012 }
3013
3014 /* Need to flush twice in case of double bufring */
3015 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3016 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
3017 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3018 MUSB2_MASK_CSRL_RXFFLUSH);
3019 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3020 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
3021 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3022 MUSB2_MASK_CSRL_RXFFLUSH);
3023 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3024 }
3025 }
3026 /* reset data toggle */
3027 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3028 MUSB2_MASK_CSRL_RXDT_CLR);
3029 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3030 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3031
3032 /* set double/single buffering */
3033 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
3034 if (mps <= (sc->sc_hw_ep_profile[ep_no].
3035 max_out_frame_size / 2)) {
3036 /* double buffer */
3037 temp &= ~(1 << ep_no);
3038 } else {
3039 /* single buffer */
3040 temp |= (1 << ep_no);
3041 }
3042 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3043
3044 /* clear sent stall */
3045 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3046 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3047 }
3048 }
3049 }
3050
3051 static void
musbotg_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)3052 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3053 {
3054 struct musbotg_softc *sc;
3055 struct usb_endpoint_descriptor *ed;
3056
3057 DPRINTFN(4, "endpoint=%p\n", ep);
3058
3059 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3060
3061 /* check mode */
3062 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3063 /* not supported */
3064 return;
3065 }
3066 /* get softc */
3067 sc = MUSBOTG_BUS2SC(udev->bus);
3068
3069 /* get endpoint descriptor */
3070 ed = ep->edesc;
3071
3072 /* reset endpoint */
3073 musbotg_clear_stall_sub(sc,
3074 UGETW(ed->wMaxPacketSize),
3075 (ed->bEndpointAddress & UE_ADDR),
3076 (ed->bmAttributes & UE_XFERTYPE),
3077 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3078 }
3079
3080 usb_error_t
musbotg_init(struct musbotg_softc * sc)3081 musbotg_init(struct musbotg_softc *sc)
3082 {
3083 const struct musb_otg_ep_cfg *cfg;
3084 struct usb_hw_ep_profile *pf;
3085 int i;
3086 uint16_t offset;
3087 uint8_t nrx;
3088 uint8_t ntx;
3089 uint8_t temp;
3090 uint8_t fsize;
3091 uint8_t frx;
3092 uint8_t ftx;
3093 uint8_t dynfifo;
3094
3095 DPRINTFN(1, "start\n");
3096
3097 /* set up the bus structure */
3098 sc->sc_bus.usbrev = USB_REV_2_0;
3099 sc->sc_bus.methods = &musbotg_bus_methods;
3100
3101 /* Set a default endpoint configuration */
3102 if (sc->sc_ep_cfg == NULL)
3103 sc->sc_ep_cfg = musbotg_ep_default;
3104
3105 USB_BUS_LOCK(&sc->sc_bus);
3106
3107 /* turn on clocks */
3108
3109 if (sc->sc_clocks_on) {
3110 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3111 }
3112
3113 /* wait a little for things to stabilise */
3114 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3115
3116 /* disable all interrupts */
3117
3118 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3119 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3120
3121 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3122 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3123 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3124
3125 /* disable pullup */
3126
3127 musbotg_pull_common(sc, 0);
3128
3129 /* wait a little bit (10ms) */
3130 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3131
3132
3133 /* disable double packet buffering */
3134 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3135 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3136
3137 /* enable HighSpeed and ISO Update flags */
3138
3139 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3140 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3141
3142 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3143 /* clear Session bit, if set */
3144 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3145 temp &= ~MUSB2_MASK_SESS;
3146 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3147 } else {
3148 /* Enter session for Host mode */
3149 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3150 temp |= MUSB2_MASK_SESS;
3151 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3152 }
3153
3154 /* wait a little for things to stabilise */
3155 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3156
3157 DPRINTF("DEVCTL=0x%02x\n", temp);
3158
3159 /* disable testmode */
3160
3161 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3162
3163 /* set default value */
3164
3165 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3166
3167 /* select endpoint index 0 */
3168
3169 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3170
3171 if (sc->sc_ep_max == 0) {
3172 /* read out number of endpoints */
3173
3174 nrx =
3175 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3176
3177 ntx =
3178 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3179
3180 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3181 } else {
3182 nrx = ntx = sc->sc_ep_max;
3183 }
3184
3185 /* these numbers exclude the control endpoint */
3186
3187 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3188
3189 if (sc->sc_ep_max == 0) {
3190 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3191 }
3192 /* read out configuration data */
3193
3194 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3195
3196 DPRINTFN(2, "Config Data: 0x%02x\n",
3197 sc->sc_conf_data);
3198
3199 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3200
3201 if (dynfifo) {
3202 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3203 "assuming 16Kbytes of FIFO RAM\n");
3204 }
3205
3206 DPRINTFN(2, "HW version: 0x%04x\n",
3207 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3208
3209 /* initialise endpoint profiles */
3210
3211 offset = 0;
3212
3213 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3214 pf = sc->sc_hw_ep_profile + temp;
3215
3216 /* select endpoint */
3217 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3218
3219 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3220 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3221 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3222
3223 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3224 temp, ftx, frx, dynfifo);
3225
3226 if (dynfifo) {
3227 if (frx && (temp <= nrx)) {
3228 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3229 cfg = &sc->sc_ep_cfg[i];
3230 if (temp <= cfg->ep_end) {
3231 frx = cfg->ep_fifosz_shift;
3232 MUSB2_WRITE_1(sc,
3233 MUSB2_REG_RXFIFOSZ,
3234 cfg->ep_fifosz_reg);
3235 break;
3236 }
3237 }
3238
3239 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3240 offset >> 3);
3241
3242 offset += (1 << frx);
3243 }
3244 if (ftx && (temp <= ntx)) {
3245 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3246 cfg = &sc->sc_ep_cfg[i];
3247 if (temp <= cfg->ep_end) {
3248 ftx = cfg->ep_fifosz_shift;
3249 MUSB2_WRITE_1(sc,
3250 MUSB2_REG_TXFIFOSZ,
3251 cfg->ep_fifosz_reg);
3252 break;
3253 }
3254 }
3255
3256 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3257 offset >> 3);
3258
3259 offset += (1 << ftx);
3260 }
3261 }
3262
3263 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3264 pf->max_in_frame_size = 1 << ftx;
3265 pf->max_out_frame_size = 1 << frx;
3266 pf->is_simplex = 0; /* duplex */
3267 pf->support_multi_buffer = 1;
3268 pf->support_bulk = 1;
3269 pf->support_interrupt = 1;
3270 pf->support_isochronous = 1;
3271 pf->support_in = 1;
3272 pf->support_out = 1;
3273 } else if (frx && (temp <= nrx)) {
3274 pf->max_out_frame_size = 1 << frx;
3275 pf->max_in_frame_size = 0;
3276 pf->is_simplex = 1; /* simplex */
3277 pf->support_multi_buffer = 1;
3278 pf->support_bulk = 1;
3279 pf->support_interrupt = 1;
3280 pf->support_isochronous = 1;
3281 pf->support_out = 1;
3282 } else if (ftx && (temp <= ntx)) {
3283 pf->max_in_frame_size = 1 << ftx;
3284 pf->max_out_frame_size = 0;
3285 pf->is_simplex = 1; /* simplex */
3286 pf->support_multi_buffer = 1;
3287 pf->support_bulk = 1;
3288 pf->support_interrupt = 1;
3289 pf->support_isochronous = 1;
3290 pf->support_in = 1;
3291 }
3292 }
3293
3294 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3295
3296 /* turn on default interrupts */
3297
3298 if (sc->sc_mode == MUSB2_HOST_MODE)
3299 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3300 else
3301 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3302 MUSB2_MASK_IRESET);
3303
3304 musbotg_clocks_off(sc);
3305
3306 USB_BUS_UNLOCK(&sc->sc_bus);
3307
3308 /* catch any lost interrupts */
3309
3310 musbotg_do_poll(&sc->sc_bus);
3311
3312 return (0); /* success */
3313 }
3314
3315 void
musbotg_uninit(struct musbotg_softc * sc)3316 musbotg_uninit(struct musbotg_softc *sc)
3317 {
3318 USB_BUS_LOCK(&sc->sc_bus);
3319
3320 /* disable all interrupts */
3321 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3322 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3323 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3324
3325 sc->sc_flags.port_powered = 0;
3326 sc->sc_flags.status_vbus = 0;
3327 sc->sc_flags.status_bus_reset = 0;
3328 sc->sc_flags.status_suspend = 0;
3329 sc->sc_flags.change_suspend = 0;
3330 sc->sc_flags.change_connect = 1;
3331
3332 musbotg_pull_down(sc);
3333 musbotg_clocks_off(sc);
3334 USB_BUS_UNLOCK(&sc->sc_bus);
3335 }
3336
3337 static void
musbotg_do_poll(struct usb_bus * bus)3338 musbotg_do_poll(struct usb_bus *bus)
3339 {
3340 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3341
3342 USB_BUS_LOCK(&sc->sc_bus);
3343 musbotg_interrupt_poll(sc);
3344 USB_BUS_UNLOCK(&sc->sc_bus);
3345 }
3346
3347 /*------------------------------------------------------------------------*
3348 * musbotg bulk support
3349 *------------------------------------------------------------------------*/
3350 static void
musbotg_device_bulk_open(struct usb_xfer * xfer)3351 musbotg_device_bulk_open(struct usb_xfer *xfer)
3352 {
3353 return;
3354 }
3355
3356 static void
musbotg_device_bulk_close(struct usb_xfer * xfer)3357 musbotg_device_bulk_close(struct usb_xfer *xfer)
3358 {
3359 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3360 }
3361
3362 static void
musbotg_device_bulk_enter(struct usb_xfer * xfer)3363 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3364 {
3365 return;
3366 }
3367
3368 static void
musbotg_device_bulk_start(struct usb_xfer * xfer)3369 musbotg_device_bulk_start(struct usb_xfer *xfer)
3370 {
3371 /* setup TDs */
3372 musbotg_setup_standard_chain(xfer);
3373 musbotg_start_standard_chain(xfer);
3374 }
3375
3376 static const struct usb_pipe_methods musbotg_device_bulk_methods =
3377 {
3378 .open = musbotg_device_bulk_open,
3379 .close = musbotg_device_bulk_close,
3380 .enter = musbotg_device_bulk_enter,
3381 .start = musbotg_device_bulk_start,
3382 };
3383
3384 /*------------------------------------------------------------------------*
3385 * musbotg control support
3386 *------------------------------------------------------------------------*/
3387 static void
musbotg_device_ctrl_open(struct usb_xfer * xfer)3388 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3389 {
3390 return;
3391 }
3392
3393 static void
musbotg_device_ctrl_close(struct usb_xfer * xfer)3394 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3395 {
3396 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3397 }
3398
3399 static void
musbotg_device_ctrl_enter(struct usb_xfer * xfer)3400 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3401 {
3402 return;
3403 }
3404
3405 static void
musbotg_device_ctrl_start(struct usb_xfer * xfer)3406 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3407 {
3408 /* setup TDs */
3409 musbotg_setup_standard_chain(xfer);
3410 musbotg_start_standard_chain(xfer);
3411 }
3412
3413 static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3414 {
3415 .open = musbotg_device_ctrl_open,
3416 .close = musbotg_device_ctrl_close,
3417 .enter = musbotg_device_ctrl_enter,
3418 .start = musbotg_device_ctrl_start,
3419 };
3420
3421 /*------------------------------------------------------------------------*
3422 * musbotg interrupt support
3423 *------------------------------------------------------------------------*/
3424 static void
musbotg_device_intr_open(struct usb_xfer * xfer)3425 musbotg_device_intr_open(struct usb_xfer *xfer)
3426 {
3427 return;
3428 }
3429
3430 static void
musbotg_device_intr_close(struct usb_xfer * xfer)3431 musbotg_device_intr_close(struct usb_xfer *xfer)
3432 {
3433 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3434 }
3435
3436 static void
musbotg_device_intr_enter(struct usb_xfer * xfer)3437 musbotg_device_intr_enter(struct usb_xfer *xfer)
3438 {
3439 return;
3440 }
3441
3442 static void
musbotg_device_intr_start(struct usb_xfer * xfer)3443 musbotg_device_intr_start(struct usb_xfer *xfer)
3444 {
3445 /* setup TDs */
3446 musbotg_setup_standard_chain(xfer);
3447 musbotg_start_standard_chain(xfer);
3448 }
3449
3450 static const struct usb_pipe_methods musbotg_device_intr_methods =
3451 {
3452 .open = musbotg_device_intr_open,
3453 .close = musbotg_device_intr_close,
3454 .enter = musbotg_device_intr_enter,
3455 .start = musbotg_device_intr_start,
3456 };
3457
3458 /*------------------------------------------------------------------------*
3459 * musbotg full speed isochronous support
3460 *------------------------------------------------------------------------*/
3461 static void
musbotg_device_isoc_open(struct usb_xfer * xfer)3462 musbotg_device_isoc_open(struct usb_xfer *xfer)
3463 {
3464 return;
3465 }
3466
3467 static void
musbotg_device_isoc_close(struct usb_xfer * xfer)3468 musbotg_device_isoc_close(struct usb_xfer *xfer)
3469 {
3470 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3471 }
3472
3473 static void
musbotg_device_isoc_enter(struct usb_xfer * xfer)3474 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3475 {
3476 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3477 uint32_t temp;
3478 uint32_t nframes;
3479 uint32_t fs_frames;
3480
3481 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3482 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3483
3484 /* get the current frame index */
3485
3486 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3487
3488 /*
3489 * check if the frame index is within the window where the frames
3490 * will be inserted
3491 */
3492 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3493
3494 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3495 fs_frames = (xfer->nframes + 7) / 8;
3496 } else {
3497 fs_frames = xfer->nframes;
3498 }
3499
3500 if ((xfer->endpoint->is_synced == 0) ||
3501 (temp < fs_frames)) {
3502 /*
3503 * If there is data underflow or the pipe queue is
3504 * empty we schedule the transfer a few frames ahead
3505 * of the current frame position. Else two isochronous
3506 * transfers might overlap.
3507 */
3508 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3509 xfer->endpoint->is_synced = 1;
3510 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3511 }
3512 /*
3513 * compute how many milliseconds the insertion is ahead of the
3514 * current frame position:
3515 */
3516 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3517
3518 /*
3519 * pre-compute when the isochronous transfer will be finished:
3520 */
3521 xfer->isoc_time_complete =
3522 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3523 fs_frames;
3524
3525 /* compute frame number for next insertion */
3526 xfer->endpoint->isoc_next += fs_frames;
3527
3528 /* setup TDs */
3529 musbotg_setup_standard_chain(xfer);
3530 }
3531
3532 static void
musbotg_device_isoc_start(struct usb_xfer * xfer)3533 musbotg_device_isoc_start(struct usb_xfer *xfer)
3534 {
3535 /* start TD chain */
3536 musbotg_start_standard_chain(xfer);
3537 }
3538
3539 static const struct usb_pipe_methods musbotg_device_isoc_methods =
3540 {
3541 .open = musbotg_device_isoc_open,
3542 .close = musbotg_device_isoc_close,
3543 .enter = musbotg_device_isoc_enter,
3544 .start = musbotg_device_isoc_start,
3545 };
3546
3547 /*------------------------------------------------------------------------*
3548 * musbotg root control support
3549 *------------------------------------------------------------------------*
3550 * Simulate a hardware HUB by handling all the necessary requests.
3551 *------------------------------------------------------------------------*/
3552
3553 static const struct usb_device_descriptor musbotg_devd = {
3554 .bLength = sizeof(struct usb_device_descriptor),
3555 .bDescriptorType = UDESC_DEVICE,
3556 .bcdUSB = {0x00, 0x02},
3557 .bDeviceClass = UDCLASS_HUB,
3558 .bDeviceSubClass = UDSUBCLASS_HUB,
3559 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3560 .bMaxPacketSize = 64,
3561 .bcdDevice = {0x00, 0x01},
3562 .iManufacturer = 1,
3563 .iProduct = 2,
3564 .bNumConfigurations = 1,
3565 };
3566
3567 static const struct usb_device_qualifier musbotg_odevd = {
3568 .bLength = sizeof(struct usb_device_qualifier),
3569 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3570 .bcdUSB = {0x00, 0x02},
3571 .bDeviceClass = UDCLASS_HUB,
3572 .bDeviceSubClass = UDSUBCLASS_HUB,
3573 .bDeviceProtocol = UDPROTO_FSHUB,
3574 .bMaxPacketSize0 = 0,
3575 .bNumConfigurations = 0,
3576 };
3577
3578 static const struct musbotg_config_desc musbotg_confd = {
3579 .confd = {
3580 .bLength = sizeof(struct usb_config_descriptor),
3581 .bDescriptorType = UDESC_CONFIG,
3582 .wTotalLength[0] = sizeof(musbotg_confd),
3583 .bNumInterface = 1,
3584 .bConfigurationValue = 1,
3585 .iConfiguration = 0,
3586 .bmAttributes = UC_SELF_POWERED,
3587 .bMaxPower = 0,
3588 },
3589 .ifcd = {
3590 .bLength = sizeof(struct usb_interface_descriptor),
3591 .bDescriptorType = UDESC_INTERFACE,
3592 .bNumEndpoints = 1,
3593 .bInterfaceClass = UICLASS_HUB,
3594 .bInterfaceSubClass = UISUBCLASS_HUB,
3595 .bInterfaceProtocol = 0,
3596 },
3597 .endpd = {
3598 .bLength = sizeof(struct usb_endpoint_descriptor),
3599 .bDescriptorType = UDESC_ENDPOINT,
3600 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3601 .bmAttributes = UE_INTERRUPT,
3602 .wMaxPacketSize[0] = 8,
3603 .bInterval = 255,
3604 },
3605 };
3606
3607 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3608
3609 static const struct usb_hub_descriptor_min musbotg_hubd = {
3610 .bDescLength = sizeof(musbotg_hubd),
3611 .bDescriptorType = UDESC_HUB,
3612 .bNbrPorts = 1,
3613 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3614 .bPwrOn2PwrGood = 50,
3615 .bHubContrCurrent = 0,
3616 .DeviceRemovable = {0}, /* port is removable */
3617 };
3618
3619 #define STRING_VENDOR \
3620 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3621
3622 #define STRING_PRODUCT \
3623 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3624
3625 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3626 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3627
3628 static usb_error_t
musbotg_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)3629 musbotg_roothub_exec(struct usb_device *udev,
3630 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3631 {
3632 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3633 const void *ptr;
3634 uint16_t len;
3635 uint16_t value;
3636 uint16_t index;
3637 uint8_t reg;
3638 usb_error_t err;
3639
3640 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3641
3642 /* buffer reset */
3643 ptr = (const void *)&sc->sc_hub_temp;
3644 len = 0;
3645 err = 0;
3646
3647 value = UGETW(req->wValue);
3648 index = UGETW(req->wIndex);
3649
3650 /* demultiplex the control request */
3651
3652 switch (req->bmRequestType) {
3653 case UT_READ_DEVICE:
3654 switch (req->bRequest) {
3655 case UR_GET_DESCRIPTOR:
3656 goto tr_handle_get_descriptor;
3657 case UR_GET_CONFIG:
3658 goto tr_handle_get_config;
3659 case UR_GET_STATUS:
3660 goto tr_handle_get_status;
3661 default:
3662 goto tr_stalled;
3663 }
3664 break;
3665
3666 case UT_WRITE_DEVICE:
3667 switch (req->bRequest) {
3668 case UR_SET_ADDRESS:
3669 goto tr_handle_set_address;
3670 case UR_SET_CONFIG:
3671 goto tr_handle_set_config;
3672 case UR_CLEAR_FEATURE:
3673 goto tr_valid; /* nop */
3674 case UR_SET_DESCRIPTOR:
3675 goto tr_valid; /* nop */
3676 case UR_SET_FEATURE:
3677 default:
3678 goto tr_stalled;
3679 }
3680 break;
3681
3682 case UT_WRITE_ENDPOINT:
3683 switch (req->bRequest) {
3684 case UR_CLEAR_FEATURE:
3685 switch (UGETW(req->wValue)) {
3686 case UF_ENDPOINT_HALT:
3687 goto tr_handle_clear_halt;
3688 case UF_DEVICE_REMOTE_WAKEUP:
3689 goto tr_handle_clear_wakeup;
3690 default:
3691 goto tr_stalled;
3692 }
3693 break;
3694 case UR_SET_FEATURE:
3695 switch (UGETW(req->wValue)) {
3696 case UF_ENDPOINT_HALT:
3697 goto tr_handle_set_halt;
3698 case UF_DEVICE_REMOTE_WAKEUP:
3699 goto tr_handle_set_wakeup;
3700 default:
3701 goto tr_stalled;
3702 }
3703 break;
3704 case UR_SYNCH_FRAME:
3705 goto tr_valid; /* nop */
3706 default:
3707 goto tr_stalled;
3708 }
3709 break;
3710
3711 case UT_READ_ENDPOINT:
3712 switch (req->bRequest) {
3713 case UR_GET_STATUS:
3714 goto tr_handle_get_ep_status;
3715 default:
3716 goto tr_stalled;
3717 }
3718 break;
3719
3720 case UT_WRITE_INTERFACE:
3721 switch (req->bRequest) {
3722 case UR_SET_INTERFACE:
3723 goto tr_handle_set_interface;
3724 case UR_CLEAR_FEATURE:
3725 goto tr_valid; /* nop */
3726 case UR_SET_FEATURE:
3727 default:
3728 goto tr_stalled;
3729 }
3730 break;
3731
3732 case UT_READ_INTERFACE:
3733 switch (req->bRequest) {
3734 case UR_GET_INTERFACE:
3735 goto tr_handle_get_interface;
3736 case UR_GET_STATUS:
3737 goto tr_handle_get_iface_status;
3738 default:
3739 goto tr_stalled;
3740 }
3741 break;
3742
3743 case UT_WRITE_CLASS_INTERFACE:
3744 case UT_WRITE_VENDOR_INTERFACE:
3745 /* XXX forward */
3746 break;
3747
3748 case UT_READ_CLASS_INTERFACE:
3749 case UT_READ_VENDOR_INTERFACE:
3750 /* XXX forward */
3751 break;
3752
3753 case UT_WRITE_CLASS_DEVICE:
3754 switch (req->bRequest) {
3755 case UR_CLEAR_FEATURE:
3756 goto tr_valid;
3757 case UR_SET_DESCRIPTOR:
3758 case UR_SET_FEATURE:
3759 break;
3760 default:
3761 goto tr_stalled;
3762 }
3763 break;
3764
3765 case UT_WRITE_CLASS_OTHER:
3766 switch (req->bRequest) {
3767 case UR_CLEAR_FEATURE:
3768 goto tr_handle_clear_port_feature;
3769 case UR_SET_FEATURE:
3770 goto tr_handle_set_port_feature;
3771 case UR_CLEAR_TT_BUFFER:
3772 case UR_RESET_TT:
3773 case UR_STOP_TT:
3774 goto tr_valid;
3775
3776 default:
3777 goto tr_stalled;
3778 }
3779 break;
3780
3781 case UT_READ_CLASS_OTHER:
3782 switch (req->bRequest) {
3783 case UR_GET_TT_STATE:
3784 goto tr_handle_get_tt_state;
3785 case UR_GET_STATUS:
3786 goto tr_handle_get_port_status;
3787 default:
3788 goto tr_stalled;
3789 }
3790 break;
3791
3792 case UT_READ_CLASS_DEVICE:
3793 switch (req->bRequest) {
3794 case UR_GET_DESCRIPTOR:
3795 goto tr_handle_get_class_descriptor;
3796 case UR_GET_STATUS:
3797 goto tr_handle_get_class_status;
3798
3799 default:
3800 goto tr_stalled;
3801 }
3802 break;
3803 default:
3804 goto tr_stalled;
3805 }
3806 goto tr_valid;
3807
3808 tr_handle_get_descriptor:
3809 switch (value >> 8) {
3810 case UDESC_DEVICE:
3811 if (value & 0xff) {
3812 goto tr_stalled;
3813 }
3814 len = sizeof(musbotg_devd);
3815 ptr = (const void *)&musbotg_devd;
3816 goto tr_valid;
3817 case UDESC_DEVICE_QUALIFIER:
3818 if (value & 0xff) {
3819 goto tr_stalled;
3820 }
3821 len = sizeof(musbotg_odevd);
3822 ptr = (const void *)&musbotg_odevd;
3823 goto tr_valid;
3824 case UDESC_CONFIG:
3825 if (value & 0xff) {
3826 goto tr_stalled;
3827 }
3828 len = sizeof(musbotg_confd);
3829 ptr = (const void *)&musbotg_confd;
3830 goto tr_valid;
3831 case UDESC_STRING:
3832 switch (value & 0xff) {
3833 case 0: /* Language table */
3834 len = sizeof(usb_string_lang_en);
3835 ptr = (const void *)&usb_string_lang_en;
3836 goto tr_valid;
3837
3838 case 1: /* Vendor */
3839 len = sizeof(musbotg_vendor);
3840 ptr = (const void *)&musbotg_vendor;
3841 goto tr_valid;
3842
3843 case 2: /* Product */
3844 len = sizeof(musbotg_product);
3845 ptr = (const void *)&musbotg_product;
3846 goto tr_valid;
3847 default:
3848 break;
3849 }
3850 break;
3851 default:
3852 goto tr_stalled;
3853 }
3854 goto tr_stalled;
3855
3856 tr_handle_get_config:
3857 len = 1;
3858 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3859 goto tr_valid;
3860
3861 tr_handle_get_status:
3862 len = 2;
3863 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3864 goto tr_valid;
3865
3866 tr_handle_set_address:
3867 if (value & 0xFF00) {
3868 goto tr_stalled;
3869 }
3870 sc->sc_rt_addr = value;
3871 goto tr_valid;
3872
3873 tr_handle_set_config:
3874 if (value >= 2) {
3875 goto tr_stalled;
3876 }
3877 sc->sc_conf = value;
3878 goto tr_valid;
3879
3880 tr_handle_get_interface:
3881 len = 1;
3882 sc->sc_hub_temp.wValue[0] = 0;
3883 goto tr_valid;
3884
3885 tr_handle_get_tt_state:
3886 tr_handle_get_class_status:
3887 tr_handle_get_iface_status:
3888 tr_handle_get_ep_status:
3889 len = 2;
3890 USETW(sc->sc_hub_temp.wValue, 0);
3891 goto tr_valid;
3892
3893 tr_handle_set_halt:
3894 tr_handle_set_interface:
3895 tr_handle_set_wakeup:
3896 tr_handle_clear_wakeup:
3897 tr_handle_clear_halt:
3898 goto tr_valid;
3899
3900 tr_handle_clear_port_feature:
3901 if (index != 1) {
3902 goto tr_stalled;
3903 }
3904 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3905
3906 switch (value) {
3907 case UHF_PORT_SUSPEND:
3908 if (sc->sc_mode == MUSB2_HOST_MODE)
3909 musbotg_wakeup_host(sc);
3910 else
3911 musbotg_wakeup_peer(sc);
3912 break;
3913
3914 case UHF_PORT_ENABLE:
3915 sc->sc_flags.port_enabled = 0;
3916 break;
3917
3918 case UHF_C_PORT_ENABLE:
3919 sc->sc_flags.change_enabled = 0;
3920 break;
3921
3922 case UHF_C_PORT_OVER_CURRENT:
3923 sc->sc_flags.change_over_current = 0;
3924 break;
3925
3926 case UHF_C_PORT_RESET:
3927 sc->sc_flags.change_reset = 0;
3928 break;
3929
3930 case UHF_PORT_TEST:
3931 case UHF_PORT_INDICATOR:
3932 /* nops */
3933 break;
3934
3935 case UHF_PORT_POWER:
3936 sc->sc_flags.port_powered = 0;
3937 musbotg_pull_down(sc);
3938 musbotg_clocks_off(sc);
3939 break;
3940 case UHF_C_PORT_CONNECTION:
3941 sc->sc_flags.change_connect = 0;
3942 break;
3943 case UHF_C_PORT_SUSPEND:
3944 sc->sc_flags.change_suspend = 0;
3945 break;
3946 default:
3947 err = USB_ERR_IOERROR;
3948 goto done;
3949 }
3950 goto tr_valid;
3951
3952 tr_handle_set_port_feature:
3953 if (index != 1) {
3954 goto tr_stalled;
3955 }
3956 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3957
3958 switch (value) {
3959 case UHF_PORT_ENABLE:
3960 sc->sc_flags.port_enabled = 1;
3961 break;
3962 case UHF_PORT_SUSPEND:
3963 if (sc->sc_mode == MUSB2_HOST_MODE)
3964 musbotg_suspend_host(sc);
3965 break;
3966
3967 case UHF_PORT_RESET:
3968 if (sc->sc_mode == MUSB2_HOST_MODE) {
3969 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3970 reg |= MUSB2_MASK_RESET;
3971 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3972
3973 /* Wait for 20 msec */
3974 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3975
3976 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3977 reg &= ~MUSB2_MASK_RESET;
3978 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3979
3980 /* determine line speed */
3981 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3982 if (reg & MUSB2_MASK_HSMODE)
3983 sc->sc_flags.status_high_speed = 1;
3984 else
3985 sc->sc_flags.status_high_speed = 0;
3986
3987 sc->sc_flags.change_reset = 1;
3988 } else
3989 err = USB_ERR_IOERROR;
3990 break;
3991
3992 case UHF_PORT_TEST:
3993 case UHF_PORT_INDICATOR:
3994 /* nops */
3995 break;
3996 case UHF_PORT_POWER:
3997 sc->sc_flags.port_powered = 1;
3998 break;
3999 default:
4000 err = USB_ERR_IOERROR;
4001 goto done;
4002 }
4003 goto tr_valid;
4004
4005 tr_handle_get_port_status:
4006
4007 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
4008
4009 if (index != 1) {
4010 goto tr_stalled;
4011 }
4012 if (sc->sc_flags.status_vbus) {
4013 musbotg_clocks_on(sc);
4014 musbotg_pull_up(sc);
4015 } else {
4016 musbotg_pull_down(sc);
4017 musbotg_clocks_off(sc);
4018 }
4019
4020 /* Select Device Side Mode */
4021 if (sc->sc_mode == MUSB2_DEVICE_MODE)
4022 value = UPS_PORT_MODE_DEVICE;
4023 else
4024 value = 0;
4025
4026 if (sc->sc_flags.status_high_speed) {
4027 value |= UPS_HIGH_SPEED;
4028 }
4029 if (sc->sc_flags.port_powered) {
4030 value |= UPS_PORT_POWER;
4031 }
4032 if (sc->sc_flags.port_enabled) {
4033 value |= UPS_PORT_ENABLED;
4034 }
4035
4036 if (sc->sc_flags.port_over_current)
4037 value |= UPS_OVERCURRENT_INDICATOR;
4038
4039 if (sc->sc_flags.status_vbus &&
4040 sc->sc_flags.status_bus_reset) {
4041 value |= UPS_CURRENT_CONNECT_STATUS;
4042 }
4043 if (sc->sc_flags.status_suspend) {
4044 value |= UPS_SUSPEND;
4045 }
4046 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4047
4048 value = 0;
4049
4050 if (sc->sc_flags.change_connect) {
4051 value |= UPS_C_CONNECT_STATUS;
4052
4053 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4054 if (sc->sc_flags.status_vbus &&
4055 sc->sc_flags.status_bus_reset) {
4056 /* reset EP0 state */
4057 sc->sc_ep0_busy = 0;
4058 sc->sc_ep0_cmd = 0;
4059 }
4060 }
4061 }
4062 if (sc->sc_flags.change_suspend)
4063 value |= UPS_C_SUSPEND;
4064 if (sc->sc_flags.change_reset)
4065 value |= UPS_C_PORT_RESET;
4066 if (sc->sc_flags.change_over_current)
4067 value |= UPS_C_OVERCURRENT_INDICATOR;
4068
4069 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4070 len = sizeof(sc->sc_hub_temp.ps);
4071 goto tr_valid;
4072
4073 tr_handle_get_class_descriptor:
4074 if (value & 0xFF) {
4075 goto tr_stalled;
4076 }
4077 ptr = (const void *)&musbotg_hubd;
4078 len = sizeof(musbotg_hubd);
4079 goto tr_valid;
4080
4081 tr_stalled:
4082 err = USB_ERR_STALLED;
4083 tr_valid:
4084 done:
4085 *plength = len;
4086 *pptr = ptr;
4087 return (err);
4088 }
4089
4090 static void
musbotg_xfer_setup(struct usb_setup_params * parm)4091 musbotg_xfer_setup(struct usb_setup_params *parm)
4092 {
4093 struct musbotg_softc *sc;
4094 struct usb_xfer *xfer;
4095 void *last_obj;
4096 uint32_t ntd;
4097 uint32_t n;
4098 uint8_t ep_no;
4099
4100 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4101 xfer = parm->curr_xfer;
4102
4103 /*
4104 * NOTE: This driver does not use any of the parameters that
4105 * are computed from the following values. Just set some
4106 * reasonable dummies:
4107 */
4108 parm->hc_max_packet_size = 0x400;
4109 parm->hc_max_frame_size = 0xc00;
4110
4111 if ((parm->methods == &musbotg_device_isoc_methods) ||
4112 (parm->methods == &musbotg_device_intr_methods))
4113 parm->hc_max_packet_count = 3;
4114 else
4115 parm->hc_max_packet_count = 1;
4116
4117 usbd_transfer_setup_sub(parm);
4118
4119 /*
4120 * compute maximum number of TDs
4121 */
4122 if (parm->methods == &musbotg_device_ctrl_methods) {
4123
4124 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4125
4126 } else if (parm->methods == &musbotg_device_bulk_methods) {
4127
4128 ntd = xfer->nframes + 1 /* SYNC */ ;
4129
4130 } else if (parm->methods == &musbotg_device_intr_methods) {
4131
4132 ntd = xfer->nframes + 1 /* SYNC */ ;
4133
4134 } else if (parm->methods == &musbotg_device_isoc_methods) {
4135
4136 ntd = xfer->nframes + 1 /* SYNC */ ;
4137
4138 } else {
4139
4140 ntd = 0;
4141 }
4142
4143 /*
4144 * check if "usbd_transfer_setup_sub" set an error
4145 */
4146 if (parm->err) {
4147 return;
4148 }
4149 /*
4150 * allocate transfer descriptors
4151 */
4152 last_obj = NULL;
4153
4154 ep_no = xfer->endpointno & UE_ADDR;
4155
4156 /*
4157 * Check for a valid endpoint profile in USB device mode:
4158 */
4159 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4160 const struct usb_hw_ep_profile *pf;
4161
4162 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4163
4164 if (pf == NULL) {
4165 /* should not happen */
4166 parm->err = USB_ERR_INVAL;
4167 return;
4168 }
4169 }
4170
4171 /* align data */
4172 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4173
4174 for (n = 0; n != ntd; n++) {
4175
4176 struct musbotg_td *td;
4177
4178 if (parm->buf) {
4179
4180 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4181
4182 /* init TD */
4183 td->max_frame_size = xfer->max_frame_size;
4184 td->reg_max_packet = xfer->max_packet_size |
4185 ((xfer->max_packet_count - 1) << 11);
4186 td->ep_no = ep_no;
4187 td->obj_next = last_obj;
4188
4189 last_obj = td;
4190 }
4191 parm->size[0] += sizeof(*td);
4192 }
4193
4194 xfer->td_start[0] = last_obj;
4195 }
4196
4197 static void
musbotg_xfer_unsetup(struct usb_xfer * xfer)4198 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4199 {
4200 return;
4201 }
4202
4203 static void
musbotg_get_dma_delay(struct usb_device * udev,uint32_t * pus)4204 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4205 {
4206 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4207
4208 if (sc->sc_mode == MUSB2_HOST_MODE)
4209 *pus = 2000; /* microseconds */
4210 else
4211 *pus = 0;
4212 }
4213
4214 static void
musbotg_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)4215 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4216 struct usb_endpoint *ep)
4217 {
4218 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4219
4220 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4221 ep, udev->address,
4222 edesc->bEndpointAddress, udev->flags.usb_mode,
4223 sc->sc_rt_addr);
4224
4225 if (udev->device_index != sc->sc_rt_addr) {
4226 switch (edesc->bmAttributes & UE_XFERTYPE) {
4227 case UE_CONTROL:
4228 ep->methods = &musbotg_device_ctrl_methods;
4229 break;
4230 case UE_INTERRUPT:
4231 ep->methods = &musbotg_device_intr_methods;
4232 break;
4233 case UE_ISOCHRONOUS:
4234 ep->methods = &musbotg_device_isoc_methods;
4235 break;
4236 case UE_BULK:
4237 ep->methods = &musbotg_device_bulk_methods;
4238 break;
4239 default:
4240 /* do nothing */
4241 break;
4242 }
4243 }
4244 }
4245
4246 static void
musbotg_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)4247 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4248 {
4249 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4250
4251 switch (state) {
4252 case USB_HW_POWER_SUSPEND:
4253 musbotg_uninit(sc);
4254 break;
4255 case USB_HW_POWER_SHUTDOWN:
4256 musbotg_uninit(sc);
4257 break;
4258 case USB_HW_POWER_RESUME:
4259 musbotg_init(sc);
4260 break;
4261 default:
4262 break;
4263 }
4264 }
4265
4266 static const struct usb_bus_methods musbotg_bus_methods =
4267 {
4268 .endpoint_init = &musbotg_ep_init,
4269 .get_dma_delay = &musbotg_get_dma_delay,
4270 .xfer_setup = &musbotg_xfer_setup,
4271 .xfer_unsetup = &musbotg_xfer_unsetup,
4272 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4273 .xfer_stall = &musbotg_xfer_stall,
4274 .set_stall = &musbotg_set_stall,
4275 .clear_stall = &musbotg_clear_stall,
4276 .roothub_exec = &musbotg_roothub_exec,
4277 .xfer_poll = &musbotg_do_poll,
4278 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,
4279 };
4280