1 /* $NecBSD: tmc18c30.c,v 1.28.12.3 2001/06/19 04:35:48 honda Exp $ */
2 /* $NetBSD$ */
3
4 #define STG_DEBUG
5 #define STG_STATICS
6 #define STG_IO_CONTROL_FLAGS (STG_FIFO_INTERRUPTS | STG_WAIT_FOR_SELECT)
7
8 /*-
9 * SPDX-License-Identifier: BSD-3-Clause
10 *
11 * [NetBSD for NEC PC-98 series]
12 * Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001
13 * NetBSD/pc98 porting staff. All rights reserved.
14 * Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001
15 * Naofumi HONDA. All rights reserved.
16 * Copyright (c) 1996, 1997, 1998, 1999
17 * Kouichi Matsuda. All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. The name of the author may not be used to endorse or promote products
28 * derived from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
34 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
39 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bio.h>
50 #include <sys/buf.h>
51 #include <sys/queue.h>
52 #include <sys/malloc.h>
53 #include <sys/errno.h>
54 #include <sys/rman.h>
55
56 #include <machine/cpu.h>
57 #include <machine/bus.h>
58
59 #include <cam/scsi/scsi_low.h>
60 #include <dev/stg/tmc18c30reg.h>
61 #include <dev/stg/tmc18c30var.h>
62
63 /***************************************************
64 * USER SETTINGS
65 ***************************************************/
66 /* DEVICE CONFIGURATION FLAGS (MINOR)
67 *
68 * 0x01 DISCONNECT OFF
69 * 0x02 PARITY LINE OFF
70 * 0x04 IDENTIFY MSG OFF ( = single lun)
71 * 0x08 SYNC TRANSFER OFF
72 */
73 /* #define STG_SYNC_SUPPORT */ /* NOT YET but easy */
74
75 /* For the 512 fifo type: change below */
76 #define TMC18C30_FIFOSZ 0x800
77 #define TMC18C30_FCBSZ 0x200
78 #define TMC18C50_FIFOSZ 0x2000
79 #define TMC18C50_FCBSZ 0x400
80
81 #define STG_MAX_DATA_SIZE (64 * 1024)
82 #define STG_DELAY_MAX (2 * 1000 * 1000)
83 #define STG_DELAY_INTERVAL (1)
84 #define STG_DELAY_SELECT_POLLING_MAX (5 * 1000 * 1000)
85
86 /***************************************************
87 * PARAMS
88 ***************************************************/
89 #define STG_NTARGETS 8
90 #define STG_NLUNS 8
91
92 /***************************************************
93 * DEBUG
94 ***************************************************/
95 #ifdef STG_DEBUG
96 static int stg_debug;
97 #endif /* STG_DEBUG */
98
99 #ifdef STG_STATICS
100 static struct stg_statics {
101 int arbit_fail_0;
102 int arbit_fail_1;
103 int disconnect;
104 int reselect;
105 } stg_statics;
106 #endif /* STG_STATICS */
107
108 /***************************************************
109 * IO control flags
110 ***************************************************/
111 #define STG_FIFO_INTERRUPTS 0x0001
112 #define STG_WAIT_FOR_SELECT 0x0100
113
114 int stg_io_control = STG_IO_CONTROL_FLAGS;
115
116 /***************************************************
117 * DEVICE STRUCTURE
118 ***************************************************/
119 extern struct cfdriver stg_cd;
120
121 /**************************************************************
122 * DECLARE
123 **************************************************************/
124 /* static */
125 static void stg_pio_read(struct stg_softc *, struct targ_info *, u_int);
126 static void stg_pio_write(struct stg_softc *, struct targ_info *, u_int);
127 static int stg_xfer(struct stg_softc *, u_int8_t *, int, int, int);
128 static int stg_msg(struct stg_softc *, struct targ_info *, u_int);
129 static int stg_reselected(struct stg_softc *);
130 static int stg_disconnected(struct stg_softc *, struct targ_info *);
131 static __inline void stg_pdma_end(struct stg_softc *, struct targ_info *);
132 static int stghw_select_targ_wait(struct stg_softc *, int);
133 static int stghw_check(struct stg_softc *);
134 static void stghw_init(struct stg_softc *);
135 static int stg_negate_signal(struct stg_softc *, u_int8_t, u_char *);
136 static int stg_expect_signal(struct stg_softc *, u_int8_t, u_int8_t);
137 static int stg_world_start(struct stg_softc *, int);
138 static int stghw_start_selection(struct stg_softc *sc, struct slccb *);
139 static void stghw_bus_reset(struct stg_softc *);
140 static void stghw_attention(struct stg_softc *);
141 static int stg_target_nexus_establish(struct stg_softc *);
142 static int stg_lun_nexus_establish(struct stg_softc *);
143 static int stg_ccb_nexus_establish(struct stg_softc *);
144 static int stg_targ_init(struct stg_softc *, struct targ_info *, int);
145 static __inline void stghw_bcr_write_1(struct stg_softc *, u_int8_t);
146 static int stg_timeout(struct stg_softc *);
147 static void stg_selection_done_and_expect_msgout(struct stg_softc *);
148
149 struct scsi_low_funcs stgfuncs = {
150 SC_LOW_INIT_T stg_world_start,
151 SC_LOW_BUSRST_T stghw_bus_reset,
152 SC_LOW_TARG_INIT_T stg_targ_init,
153 SC_LOW_LUN_INIT_T NULL,
154
155 SC_LOW_SELECT_T stghw_start_selection,
156 SC_LOW_NEXUS_T stg_lun_nexus_establish,
157 SC_LOW_NEXUS_T stg_ccb_nexus_establish,
158
159 SC_LOW_ATTEN_T stghw_attention,
160 SC_LOW_MSG_T stg_msg,
161
162 SC_LOW_TIMEOUT_T stg_timeout,
163 SC_LOW_POLL_T stgintr,
164
165 NULL,
166 };
167
168 /****************************************************
169 * hwfuncs
170 ****************************************************/
171 static __inline void
stghw_bcr_write_1(struct stg_softc * sc,u_int8_t bcv)172 stghw_bcr_write_1(struct stg_softc *sc, u_int8_t bcv)
173 {
174
175 bus_write_1(sc->port_res, tmc_bctl, bcv);
176 sc->sc_busimg = bcv;
177 }
178
179 static int
stghw_check(sc)180 stghw_check(sc)
181 struct stg_softc *sc;
182 {
183 struct scsi_low_softc *slp = &sc->sc_sclow;
184 u_int fcbsize, fcb;
185 u_int16_t lsb, msb;
186
187 lsb = bus_read_1(sc->port_res, tmc_idlsb);
188 msb = bus_read_1(sc->port_res, tmc_idmsb);
189 switch (msb << 8 | lsb)
190 {
191 case 0x6127:
192 /* TMCCHIP_1800 not supported. (it's my policy) */
193 sc->sc_chip = TMCCHIP_1800;
194 return EINVAL;
195
196 case 0x60e9:
197 if (bus_read_1(sc->port_res, tmc_cfg2) & 0x02)
198 {
199 sc->sc_chip = TMCCHIP_18C30;
200 sc->sc_fsz = TMC18C30_FIFOSZ;
201 fcbsize = TMC18C30_FCBSZ;
202 }
203 else
204 {
205 sc->sc_chip = TMCCHIP_18C50;
206 sc->sc_fsz = TMC18C50_FIFOSZ;
207 fcbsize = TMC18C50_FCBSZ;
208 }
209 break;
210
211 default:
212 sc->sc_chip = TMCCHIP_UNK;
213 return ENODEV;
214 }
215
216 sc->sc_fcRinit = FCTL_INTEN;
217 sc->sc_fcWinit = FCTL_PARENB | FCTL_INTEN;
218
219 if (slp->sl_cfgflags & CFG_NOATTEN)
220 sc->sc_imsg = 0;
221 else
222 sc->sc_imsg = BCTL_ATN;
223 sc->sc_busc = BCTL_BUSEN;
224
225 sc->sc_wthold = fcbsize + 256;
226 sc->sc_rthold = fcbsize - 256;
227 sc->sc_maxwsize = sc->sc_fsz;
228
229 fcb = fcbsize / (sc->sc_fsz / 16);
230 sc->sc_icinit = ICTL_CD | ICTL_SEL | ICTL_ARBIT | fcb;
231 return 0;
232 }
233
234 static void
stghw_init(sc)235 stghw_init(sc)
236 struct stg_softc *sc;
237 {
238
239 bus_write_1(sc->port_res, tmc_ictl, 0);
240 stghw_bcr_write_1(sc, BCTL_BUSFREE);
241 bus_write_1(sc->port_res, tmc_fctl,
242 sc->sc_fcRinit | FCTL_CLRFIFO | FCTL_CLRINT);
243 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
244 bus_write_1(sc->port_res, tmc_ictl, sc->sc_icinit);
245
246 bus_write_1(sc->port_res, tmc_ssctl, 0);
247 }
248
249 static int
stg_targ_init(sc,ti,action)250 stg_targ_init(sc, ti, action)
251 struct stg_softc *sc;
252 struct targ_info *ti;
253 int action;
254 {
255 struct stg_targ_info *sti = (void *) ti;
256
257 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
258 {
259 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
260 ti->ti_maxsynch.period = 0;
261 ti->ti_maxsynch.offset = 0;
262 sti->sti_reg_synch = 0;
263 }
264 return 0;
265 }
266
267 /****************************************************
268 * scsi low interface
269 ****************************************************/
270 static void
stghw_attention(sc)271 stghw_attention(sc)
272 struct stg_softc *sc;
273 {
274
275 sc->sc_busc |= BCTL_ATN;
276 sc->sc_busimg |= BCTL_ATN;
277 bus_write_1(sc->port_res, tmc_bctl, sc->sc_busimg);
278 DELAY(10);
279 }
280
281 static void
stghw_bus_reset(sc)282 stghw_bus_reset(sc)
283 struct stg_softc *sc;
284 {
285
286 bus_write_1(sc->port_res, tmc_ictl, 0);
287 bus_write_1(sc->port_res, tmc_fctl, 0);
288 stghw_bcr_write_1(sc, BCTL_RST);
289 DELAY(100000);
290 stghw_bcr_write_1(sc, BCTL_BUSFREE);
291 }
292
293 static int
stghw_start_selection(sc,cb)294 stghw_start_selection(sc, cb)
295 struct stg_softc *sc;
296 struct slccb *cb;
297 {
298 struct targ_info *ti = cb->ti;
299 register u_int8_t stat;
300
301 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
302 sc->sc_dataout_timeout = 0;
303 sc->sc_ubf_timeout = 0;
304 stghw_bcr_write_1(sc, BCTL_BUSFREE);
305 bus_write_1(sc->port_res, tmc_ictl, sc->sc_icinit);
306
307 stat = bus_read_1(sc->port_res, tmc_astat);
308 if ((stat & ASTAT_INT) != 0)
309 {
310 return SCSI_LOW_START_FAIL;
311 }
312
313 bus_write_1(sc->port_res, tmc_scsiid, sc->sc_idbit);
314 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit | FCTL_ARBIT);
315
316 SCSI_LOW_SETUP_PHASE(ti, PH_ARBSTART);
317 return SCSI_LOW_START_OK;
318 }
319
320 static int
stg_world_start(sc,fdone)321 stg_world_start(sc, fdone)
322 struct stg_softc *sc;
323 int fdone;
324 {
325 struct scsi_low_softc *slp = &sc->sc_sclow;
326 int error;
327
328 if ((slp->sl_cfgflags & CFG_NOPARITY) == 0)
329 sc->sc_fcRinit |= FCTL_PARENB;
330 else
331 sc->sc_fcRinit &= ~FCTL_PARENB;
332
333 if ((error = stghw_check(sc)) != 0)
334 return error;
335
336 stghw_init(sc);
337 scsi_low_bus_reset(slp);
338 stghw_init(sc);
339
340 return 0;
341 }
342
343 static int
stg_msg(sc,ti,msg)344 stg_msg(sc, ti, msg)
345 struct stg_softc *sc;
346 struct targ_info *ti;
347 u_int msg;
348 {
349 struct stg_targ_info *sti = (void *) ti;
350 u_int period, offset;
351
352 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
353 {
354 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
355 {
356 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
357 return EINVAL;
358 }
359 return 0;
360 }
361
362 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
363 return 0;
364
365 period = ti->ti_maxsynch.period;
366 offset = ti->ti_maxsynch.offset;
367 period = period << 2;
368 if (period >= 200)
369 {
370 sti->sti_reg_synch = (period - 200) / 50;
371 if (period % 50)
372 sti->sti_reg_synch ++;
373 sti->sti_reg_synch |= SSCTL_SYNCHEN;
374 }
375 else if (period >= 100)
376 {
377 sti->sti_reg_synch = (period - 100) / 50;
378 if (period % 50)
379 sti->sti_reg_synch ++;
380 sti->sti_reg_synch |= SSCTL_SYNCHEN | SSCTL_FSYNCHEN;
381 }
382 bus_write_1(sc->port_res, tmc_ssctl, sti->sti_reg_synch);
383 return 0;
384 }
385
386 /**************************************************************
387 * General probe attach
388 **************************************************************/
389 int
stgprobesubr(struct resource * res,u_int dvcfg)390 stgprobesubr(struct resource *res, u_int dvcfg)
391 {
392 u_int16_t lsb, msb;
393
394 lsb = bus_read_1(res, tmc_idlsb);
395 msb = bus_read_1(res, tmc_idmsb);
396 switch (msb << 8 | lsb)
397 {
398 default:
399 return 0;
400 case 0x6127:
401 /* not support! */
402 return 0;
403 case 0x60e9:
404 return 1;
405 }
406 return 0;
407 }
408
409 void
stgattachsubr(sc)410 stgattachsubr(sc)
411 struct stg_softc *sc;
412 {
413 struct scsi_low_softc *slp = &sc->sc_sclow;
414
415 printf("\n");
416
417 sc->sc_idbit = (1 << slp->sl_hostid);
418 slp->sl_funcs = &stgfuncs;
419 sc->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
420
421 slp->sl_flags |= HW_READ_PADDING;
422 slp->sl_cfgflags |= CFG_ASYNC; /* XXX */
423
424 (void) scsi_low_attach(slp, 0, STG_NTARGETS, STG_NLUNS,
425 sizeof(struct stg_targ_info), 0);
426 gone_in(12, "stg(4) driver");
427 }
428
429 /**************************************************************
430 * PDMA functions
431 **************************************************************/
432 static __inline void
stg_pdma_end(sc,ti)433 stg_pdma_end(sc, ti)
434 struct stg_softc *sc;
435 struct targ_info *ti;
436 {
437 struct scsi_low_softc *slp = &sc->sc_sclow;
438 struct slccb *cb = slp->sl_Qnexus;
439 u_int len, tres;
440
441 slp->sl_flags &= ~HW_PDMASTART;
442 sc->sc_icinit &= ~ICTL_FIFO;
443 sc->sc_dataout_timeout = 0;
444
445 if (cb == NULL)
446 {
447 slp->sl_error |= PDMAERR;
448 goto out;
449 }
450
451 if (ti->ti_phase == PH_DATA)
452 {
453 len = bus_read_2(sc->port_res, tmc_fdcnt);
454 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
455 {
456 if (len != 0)
457 {
458 tres = len + slp->sl_scp.scp_datalen;
459 if (tres <= (u_int) cb->ccb_scp.scp_datalen)
460 {
461 slp->sl_scp.scp_data -= len;
462 slp->sl_scp.scp_datalen = tres;
463 }
464 else
465 {
466 slp->sl_error |= PDMAERR;
467 device_printf(slp->sl_dev,
468 "len %x >= datalen %x\n",
469 len, slp->sl_scp.scp_datalen);
470 }
471 }
472 }
473 else if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
474 {
475 if (len != 0)
476 {
477 slp->sl_error |= PDMAERR;
478 device_printf(slp->sl_dev,
479 "len %x left in fifo\n", len);
480 }
481 }
482 scsi_low_data_finish(slp);
483 }
484 else
485 {
486
487 device_printf(slp->sl_dev, "data phase miss\n");
488 slp->sl_error |= PDMAERR;
489 }
490
491 out:
492 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
493 }
494
495 static void
stg_pio_read(sc,ti,thold)496 stg_pio_read(sc, ti, thold)
497 struct stg_softc *sc;
498 struct targ_info *ti;
499 u_int thold;
500 {
501 struct scsi_low_softc *slp = &sc->sc_sclow;
502 struct sc_p *sp = &slp->sl_scp;
503 int tout;
504 u_int res;
505 u_int8_t stat;
506
507 if ((slp->sl_flags & HW_PDMASTART) == 0)
508 {
509 bus_write_1(sc->port_res, tmc_fctl,
510 sc->sc_fcRinit | FCTL_FIFOEN);
511 slp->sl_flags |= HW_PDMASTART;
512 }
513
514 tout = sc->sc_tmaxcnt;
515 while (tout -- > 0)
516 {
517 if (thold > 0)
518 {
519 res = bus_read_2(sc->port_res, tmc_fdcnt);
520 if (res < thold)
521 {
522 bus_write_1(sc->port_res, tmc_ictl,
523 sc->sc_icinit);
524 break;
525 }
526 }
527 else
528 {
529 stat = bus_read_1(sc->port_res, tmc_bstat);
530 res = bus_read_2(sc->port_res, tmc_fdcnt);
531 if (res == 0)
532 {
533 if ((stat & PHASE_MASK) != DATA_IN_PHASE)
534 break;
535 if (sp->scp_datalen <= 0)
536 break;
537 DELAY(1);
538 continue;
539 }
540 }
541
542 /* The assumtion res != 0 is valid here */
543 if (res > sp->scp_datalen)
544 {
545 if (res == (u_int) -1)
546 break;
547
548 slp->sl_error |= PDMAERR;
549 if ((slp->sl_flags & HW_READ_PADDING) == 0)
550 {
551 device_printf(slp->sl_dev,
552 "read padding required\n");
553 break;
554 }
555
556 sp->scp_datalen = 0;
557 if (res > STG_MAX_DATA_SIZE)
558 res = STG_MAX_DATA_SIZE;
559 while (res -- > 0)
560 {
561 (void) bus_read_1(sc->port_res, tmc_rfifo);
562 }
563 continue;
564 }
565
566 sp->scp_datalen -= res;
567 if (res & 1)
568 {
569 *sp->scp_data = bus_read_1(sc->port_res, tmc_rfifo);
570 sp->scp_data ++;
571 res --;
572 }
573
574 bus_read_multi_2(sc->port_res, tmc_rfifo,
575 (u_int16_t *) sp->scp_data, res >> 1);
576 sp->scp_data += res;
577 }
578
579 if (tout <= 0)
580 device_printf(slp->sl_dev, "pio read timeout\n");
581 }
582
583 static void
stg_pio_write(sc,ti,thold)584 stg_pio_write(sc, ti, thold)
585 struct stg_softc *sc;
586 struct targ_info *ti;
587 u_int thold;
588 {
589 struct scsi_low_softc *slp = &sc->sc_sclow;
590 struct sc_p *sp = &slp->sl_scp;
591 u_int res;
592 int tout;
593 register u_int8_t stat;
594
595 if ((slp->sl_flags & HW_PDMASTART) == 0)
596 {
597 stat = sc->sc_fcWinit | FCTL_FIFOEN | FCTL_FIFOW;
598 bus_write_1(sc->port_res, tmc_fctl, stat | FCTL_CLRFIFO);
599 bus_write_1(sc->port_res, tmc_fctl, stat);
600 slp->sl_flags |= HW_PDMASTART;
601 }
602
603 tout = sc->sc_tmaxcnt;
604 while (tout -- > 0)
605 {
606 stat = bus_read_1(sc->port_res, tmc_bstat);
607 if ((stat & PHASE_MASK) != DATA_OUT_PHASE)
608 break;
609
610 if (sp->scp_datalen <= 0)
611 {
612 if (sc->sc_dataout_timeout == 0)
613 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ;
614 break;
615 }
616
617 if (thold > 0)
618 {
619 res = bus_read_2(sc->port_res, tmc_fdcnt);
620 if (res > thold)
621 {
622 bus_write_1(sc->port_res, tmc_ictl,
623 sc->sc_icinit);
624 break;
625 }
626 }
627 else
628 {
629 res = bus_read_2(sc->port_res, tmc_fdcnt);
630 if (res > sc->sc_maxwsize / 2)
631 {
632 DELAY(1);
633 continue;
634 }
635 }
636
637 if (res == (u_int) -1)
638 break;
639 res = sc->sc_maxwsize - res;
640 if (res > sp->scp_datalen)
641 res = sp->scp_datalen;
642
643 sp->scp_datalen -= res;
644 if ((res & 0x1) != 0)
645 {
646 bus_write_1(sc->port_res, tmc_wfifo, *sp->scp_data);
647 sp->scp_data ++;
648 res --;
649 }
650
651 bus_write_multi_2(sc->port_res, tmc_wfifo,
652 (u_int16_t *) sp->scp_data, res >> 1);
653 sp->scp_data += res;
654 }
655
656 if (tout <= 0)
657 device_printf(slp->sl_dev, "pio write timeout\n");
658 }
659
660 static int
stg_negate_signal(struct stg_softc * sc,u_int8_t mask,u_char * s)661 stg_negate_signal(struct stg_softc *sc, u_int8_t mask, u_char *s)
662 {
663 struct scsi_low_softc *slp = &sc->sc_sclow;
664 int wc;
665 u_int8_t regv;
666
667 for (wc = 0; wc < STG_DELAY_MAX / STG_DELAY_INTERVAL; wc ++)
668 {
669 regv = bus_read_1(sc->port_res, tmc_bstat);
670 if (regv == (u_int8_t) -1)
671 return -1;
672 if ((regv & mask) == 0)
673 return 1;
674
675 DELAY(STG_DELAY_INTERVAL);
676 }
677
678 device_printf(slp->sl_dev, "%s stg_negate_signal timeout\n", s);
679 return -1;
680 }
681
682 static int
stg_expect_signal(struct stg_softc * sc,u_int8_t phase,u_int8_t mask)683 stg_expect_signal(struct stg_softc *sc, u_int8_t phase, u_int8_t mask)
684 {
685 struct scsi_low_softc *slp = &sc->sc_sclow;
686 int wc;
687 u_int8_t ph;
688
689 phase &= PHASE_MASK;
690 for (wc = 0; wc < STG_DELAY_MAX / STG_DELAY_INTERVAL; wc ++)
691 {
692 ph = bus_read_1(sc->port_res, tmc_bstat);
693 if (ph == (u_int8_t) -1)
694 return -1;
695 if ((ph & PHASE_MASK) != phase)
696 return 0;
697 if ((ph & mask) != 0)
698 return 1;
699
700 DELAY(STG_DELAY_INTERVAL);
701 }
702
703 device_printf(slp->sl_dev, "stg_expect_signal timeout\n");
704 return -1;
705 }
706
707 static int
stg_xfer(sc,buf,len,phase,clear_atn)708 stg_xfer(sc, buf, len, phase, clear_atn)
709 struct stg_softc *sc;
710 u_int8_t *buf;
711 int len;
712 int phase;
713 int clear_atn;
714 {
715 int rv, ptr;
716
717 if (phase & BSTAT_IO)
718 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
719 else
720 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcWinit);
721
722 for (ptr = 0; len > 0; len --)
723 {
724 rv = stg_expect_signal(sc, phase, BSTAT_REQ);
725 if (rv <= 0)
726 goto bad;
727
728 if (len == 1 && clear_atn != 0)
729 {
730 sc->sc_busc &= ~BCTL_ATN;
731 stghw_bcr_write_1(sc, sc->sc_busc);
732 SCSI_LOW_DEASSERT_ATN(&sc->sc_sclow);
733 }
734
735 if (phase & BSTAT_IO)
736 {
737 buf[ptr ++] = bus_read_1(sc->port_res, tmc_rdata);
738 }
739 else
740 {
741 bus_write_1(sc->port_res, tmc_wdata, buf[ptr ++]);
742 }
743
744 stg_negate_signal(sc, BSTAT_ACK, "xfer<ACK>");
745 }
746
747 bad:
748 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
749 return len;
750 }
751
752 /**************************************************************
753 * disconnect & reselect (HW low)
754 **************************************************************/
755 static int
stg_reselected(sc)756 stg_reselected(sc)
757 struct stg_softc *sc;
758 {
759 struct scsi_low_softc *slp = &sc->sc_sclow;
760 int tout;
761 u_int sid;
762 u_int8_t regv;
763
764 if (slp->sl_selid != NULL)
765 {
766 /* XXX:
767 * Selection vs Reselection conflicts.
768 */
769 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
770 stghw_bcr_write_1(sc, BCTL_BUSFREE);
771 }
772 else if (slp->sl_Tnexus != NULL)
773 {
774 device_printf(slp->sl_dev, "unexpected termination\n");
775 stg_disconnected(sc, slp->sl_Tnexus);
776 }
777
778 /* XXX:
779 * We should ack the reselection as soon as possible,
780 * because the target would abort the current reselection seq
781 * due to reselection timeout.
782 */
783 tout = STG_DELAY_SELECT_POLLING_MAX;
784 while (tout -- > 0)
785 {
786 regv = bus_read_1(sc->port_res, tmc_bstat);
787 if ((regv & (BSTAT_IO | BSTAT_SEL | BSTAT_BSY)) ==
788 (BSTAT_IO | BSTAT_SEL))
789 {
790 DELAY(1);
791 regv = bus_read_1(sc->port_res, tmc_bstat);
792 if ((regv & (BSTAT_IO | BSTAT_SEL | BSTAT_BSY)) ==
793 (BSTAT_IO | BSTAT_SEL))
794 goto reselect_start;
795 }
796 DELAY(1);
797 }
798 device_printf(slp->sl_dev, "reselction timeout I\n");
799 return EJUSTRETURN;
800
801 reselect_start:
802 sid = (u_int) bus_read_1(sc->port_res, tmc_scsiid);
803 if ((sid & sc->sc_idbit) == 0)
804 {
805 /* not us */
806 return EJUSTRETURN;
807 }
808
809 bus_write_1(sc->port_res, tmc_fctl,
810 sc->sc_fcRinit | FCTL_CLRFIFO | FCTL_CLRINT);
811 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
812 stghw_bcr_write_1(sc, sc->sc_busc | BCTL_BSY);
813
814 while (tout -- > 0)
815 {
816 regv = bus_read_1(sc->port_res, tmc_bstat);
817 if ((regv & (BSTAT_SEL | BSTAT_BSY)) == BSTAT_BSY)
818 goto reselected;
819 DELAY(1);
820 }
821 device_printf(slp->sl_dev, "reselction timeout II\n");
822 return EJUSTRETURN;
823
824 reselected:
825 sid &= ~sc->sc_idbit;
826 sid = ffs(sid) - 1;
827 if (scsi_low_reselected(slp, sid) == NULL)
828 return EJUSTRETURN;
829
830 #ifdef STG_STATICS
831 stg_statics.reselect ++;
832 #endif /* STG_STATICS */
833 return EJUSTRETURN;
834 }
835
836 static int
stg_disconnected(sc,ti)837 stg_disconnected(sc, ti)
838 struct stg_softc *sc;
839 struct targ_info *ti;
840 {
841 struct scsi_low_softc *slp = &sc->sc_sclow;
842
843 /* clear bus status & fifo */
844 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit | FCTL_CLRFIFO);
845 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
846 stghw_bcr_write_1(sc, BCTL_BUSFREE);
847 sc->sc_icinit &= ~ICTL_FIFO;
848 sc->sc_busc &= ~BCTL_ATN;
849 sc->sc_dataout_timeout = 0;
850 sc->sc_ubf_timeout = 0;
851
852 #ifdef STG_STATICS
853 stg_statics.disconnect ++;
854 #endif /* STG_STATICS */
855 scsi_low_disconnected(slp, ti);
856 return 1;
857 }
858
859 /**************************************************************
860 * SEQUENCER
861 **************************************************************/
862 static int
stg_target_nexus_establish(sc)863 stg_target_nexus_establish(sc)
864 struct stg_softc *sc;
865 {
866 struct scsi_low_softc *slp = &sc->sc_sclow;
867 struct targ_info *ti = slp->sl_Tnexus;
868 struct stg_targ_info *sti = (void *) ti;
869
870 bus_write_1(sc->port_res, tmc_ssctl, sti->sti_reg_synch);
871 if ((stg_io_control & STG_FIFO_INTERRUPTS) != 0)
872 {
873 sc->sc_icinit |= ICTL_FIFO;
874 }
875 return 0;
876 }
877
878 static int
stg_lun_nexus_establish(sc)879 stg_lun_nexus_establish(sc)
880 struct stg_softc *sc;
881 {
882
883 return 0;
884 }
885
886 static int
stg_ccb_nexus_establish(sc)887 stg_ccb_nexus_establish(sc)
888 struct stg_softc *sc;
889 {
890 struct scsi_low_softc *slp = &sc->sc_sclow;
891 struct slccb *cb = slp->sl_Qnexus;
892
893 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
894 return 0;
895 }
896
897 #define STGHW_SELECT_INTERVAL 10
898
899 static int
stghw_select_targ_wait(sc,mu)900 stghw_select_targ_wait(sc, mu)
901 struct stg_softc *sc;
902 int mu;
903 {
904
905 mu = mu / STGHW_SELECT_INTERVAL;
906 while (mu -- > 0)
907 {
908 if ((bus_read_1(sc->port_res, tmc_bstat) & BSTAT_BSY) == 0)
909 {
910 DELAY(STGHW_SELECT_INTERVAL);
911 continue;
912 }
913 DELAY(1);
914 if ((bus_read_1(sc->port_res, tmc_bstat) & BSTAT_BSY) != 0)
915 {
916 return 0;
917 }
918 }
919 return ENXIO;
920 }
921
922 static void
stg_selection_done_and_expect_msgout(sc)923 stg_selection_done_and_expect_msgout(sc)
924 struct stg_softc *sc;
925 {
926 struct scsi_low_softc *slp = &sc->sc_sclow;
927
928 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit | FCTL_CLRFIFO);
929 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
930 stghw_bcr_write_1(sc, sc->sc_imsg | sc->sc_busc);
931 SCSI_LOW_ASSERT_ATN(slp);
932 }
933
934 int
stgintr(arg)935 stgintr(arg)
936 void *arg;
937 {
938 struct stg_softc *sc = arg;
939 struct scsi_low_softc *slp = &sc->sc_sclow;
940 struct targ_info *ti;
941 struct buf *bp;
942 u_int derror, flags;
943 int len;
944 u_int8_t status, astatus, regv;
945
946 /*******************************************
947 * interrupt check
948 *******************************************/
949 if (slp->sl_flags & HW_INACTIVE)
950 return 0;
951
952 astatus = bus_read_1(sc->port_res, tmc_astat);
953 status = bus_read_1(sc->port_res, tmc_bstat);
954
955 if ((astatus & ASTAT_STATMASK) == 0 || astatus == (u_int8_t) -1)
956 return 0;
957
958 bus_write_1(sc->port_res, tmc_ictl, 0);
959 if (astatus & ASTAT_SCSIRST)
960 {
961 bus_write_1(sc->port_res, tmc_fctl,
962 sc->sc_fcRinit | FCTL_CLRFIFO);
963 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
964 bus_write_1(sc->port_res, tmc_ictl, 0);
965
966 scsi_low_restart(slp, SCSI_LOW_RESTART_SOFT,
967 "bus reset (power off?)");
968 return 1;
969 }
970
971 /*******************************************
972 * debug section
973 *******************************************/
974 #ifdef STG_DEBUG
975 if (stg_debug)
976 {
977 scsi_low_print(slp, NULL);
978 device_printf(slp->sl_dev, "st %x ist %x\n\n",
979 status, astatus);
980 #ifdef KDB
981 if (stg_debug > 1)
982 kdb_enter(KDB_WHY_CAM, "stg");
983 #endif /* KDB */
984 }
985 #endif /* STG_DEBUG */
986
987 /*******************************************
988 * reselection & nexus
989 *******************************************/
990 if ((status & RESEL_PHASE_MASK)== PHASE_RESELECTED)
991 {
992 if (stg_reselected(sc) == EJUSTRETURN)
993 goto out;
994 }
995
996 if ((ti = slp->sl_Tnexus) == NULL)
997 return 0;
998
999 derror = 0;
1000 if ((astatus & ASTAT_PARERR) != 0 && ti->ti_phase != PH_ARBSTART &&
1001 (sc->sc_fcRinit & FCTL_PARENB) != 0)
1002 {
1003 slp->sl_error |= PARITYERR;
1004 derror = SCSI_LOW_DATA_PE;
1005 if ((status & PHASE_MASK) == MESSAGE_IN_PHASE)
1006 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_PARITY, 0);
1007 else
1008 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ERROR, 1);
1009 }
1010
1011 /*******************************************
1012 * aribitration & selection
1013 *******************************************/
1014 switch (ti->ti_phase)
1015 {
1016 case PH_ARBSTART:
1017 if ((astatus & ASTAT_ARBIT) == 0)
1018 {
1019 #ifdef STG_STATICS
1020 stg_statics.arbit_fail_0 ++;
1021 #endif /* STG_STATICS */
1022 goto arb_fail;
1023 }
1024
1025 status = bus_read_1(sc->port_res, tmc_bstat);
1026 if ((status & BSTAT_IO) != 0)
1027 {
1028 /* XXX:
1029 * Selection vs Reselection conflicts.
1030 */
1031 #ifdef STG_STATICS
1032 stg_statics.arbit_fail_1 ++;
1033 #endif /* STG_STATICS */
1034 arb_fail:
1035 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
1036 stghw_bcr_write_1(sc, BCTL_BUSFREE);
1037 scsi_low_arbit_fail(slp, slp->sl_Qnexus);
1038 goto out;
1039 }
1040
1041 /*
1042 * selection assert start.
1043 */
1044 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
1045 scsi_low_arbit_win(slp);
1046
1047 bus_write_1(sc->port_res, tmc_scsiid,
1048 sc->sc_idbit | (1 << ti->ti_id));
1049 stghw_bcr_write_1(sc, sc->sc_imsg | sc->sc_busc | BCTL_SEL);
1050 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcWinit);
1051 if ((stg_io_control & STG_WAIT_FOR_SELECT) != 0)
1052 {
1053 /* selection abort delay 200 + 100 micro sec */
1054 if (stghw_select_targ_wait(sc, 300) == 0)
1055 {
1056 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1057 stg_selection_done_and_expect_msgout(sc);
1058 }
1059 }
1060 goto out;
1061
1062 case PH_SELSTART:
1063 if ((status & BSTAT_BSY) == 0)
1064 {
1065 /* selection timeout delay 250 ms */
1066 if (stghw_select_targ_wait(sc, 250 * 1000) != 0)
1067 {
1068 stg_disconnected(sc, ti);
1069 goto out;
1070 }
1071 }
1072
1073 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1074 stg_selection_done_and_expect_msgout(sc);
1075 goto out;
1076
1077 case PH_SELECTED:
1078 if ((status & BSTAT_REQ) == 0)
1079 goto out;
1080 stg_target_nexus_establish(sc);
1081 break;
1082
1083 case PH_RESEL:
1084 if ((status & BSTAT_REQ) == 0)
1085 goto out;
1086
1087 /* clear a busy line */
1088 bus_write_1(sc->port_res, tmc_fctl, sc->sc_fcRinit);
1089 stghw_bcr_write_1(sc, sc->sc_busc);
1090 stg_target_nexus_establish(sc);
1091 if ((status & PHASE_MASK) != MESSAGE_IN_PHASE)
1092 {
1093 device_printf(slp->sl_dev,
1094 "unexpected phase after reselect\n");
1095 slp->sl_error |= FATALIO;
1096 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ABORT, 1);
1097 goto out;
1098 }
1099 break;
1100 }
1101
1102 /*******************************************
1103 * data phase
1104 *******************************************/
1105 if ((slp->sl_flags & HW_PDMASTART) && STG_IS_PHASE_DATA(status) == 0)
1106 {
1107 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1108 stg_pio_read(sc, ti, 0);
1109
1110 stg_pdma_end(sc, ti);
1111 }
1112
1113 /*******************************************
1114 * scsi seq
1115 *******************************************/
1116 switch (status & PHASE_MASK)
1117 {
1118 case COMMAND_PHASE:
1119 if (stg_expect_signal(sc, COMMAND_PHASE, BSTAT_REQ) <= 0)
1120 break;
1121
1122 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1123 if (scsi_low_cmd(slp, ti) != 0)
1124 {
1125 scsi_low_attention(slp);
1126 }
1127
1128 if (stg_xfer(sc, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen,
1129 COMMAND_PHASE, 0) != 0)
1130 {
1131 device_printf(slp->sl_dev, "CMDOUT short\n");
1132 }
1133 break;
1134
1135 case DATA_OUT_PHASE:
1136 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1137 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1138 {
1139 scsi_low_attention(slp);
1140 }
1141
1142 if ((sc->sc_icinit & ICTL_FIFO) != 0)
1143 stg_pio_write(sc, ti, sc->sc_wthold);
1144 else
1145 stg_pio_write(sc, ti, 0);
1146 break;
1147
1148 case DATA_IN_PHASE:
1149 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1150 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1151 {
1152 scsi_low_attention(slp);
1153 }
1154
1155 if ((sc->sc_icinit & ICTL_FIFO) != 0)
1156 stg_pio_read(sc, ti, sc->sc_rthold);
1157 else
1158 stg_pio_read(sc, ti, 0);
1159 break;
1160
1161 case STATUS_PHASE:
1162 regv = stg_expect_signal(sc, STATUS_PHASE, BSTAT_REQ);
1163 if (regv <= 0)
1164 break;
1165
1166 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1167 regv = bus_read_1(sc->port_res, tmc_sdna);
1168 if (scsi_low_statusin(slp, ti, regv | derror) != 0)
1169 {
1170 scsi_low_attention(slp);
1171 }
1172 if (regv != bus_read_1(sc->port_res, tmc_rdata))
1173 {
1174 device_printf(slp->sl_dev, "STATIN: data mismatch\n");
1175 }
1176 stg_negate_signal(sc, BSTAT_ACK, "statin<ACK>");
1177 break;
1178
1179 case MESSAGE_OUT_PHASE:
1180 if (stg_expect_signal(sc, MESSAGE_OUT_PHASE, BSTAT_REQ) <= 0)
1181 break;
1182
1183 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1184 flags = (ti->ti_ophase != ti->ti_phase) ?
1185 SCSI_LOW_MSGOUT_INIT : 0;
1186 len = scsi_low_msgout(slp, ti, flags);
1187
1188 if (len > 1 && slp->sl_atten == 0)
1189 {
1190 scsi_low_attention(slp);
1191 }
1192
1193 if (stg_xfer(sc, ti->ti_msgoutstr, len, MESSAGE_OUT_PHASE,
1194 slp->sl_clear_atten) != 0)
1195 {
1196 device_printf(slp->sl_dev, "MSGOUT short\n");
1197 }
1198 else
1199 {
1200 if (slp->sl_msgphase >= MSGPH_ABORT)
1201 {
1202 stg_disconnected(sc, ti);
1203 }
1204 }
1205 break;
1206
1207 case MESSAGE_IN_PHASE:
1208 /* confirm phase and req signal */
1209 if (stg_expect_signal(sc, MESSAGE_IN_PHASE, BSTAT_REQ) <= 0)
1210 break;
1211
1212 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1213
1214 /* read data with NOACK */
1215 regv = bus_read_1(sc->port_res, tmc_sdna);
1216
1217 if (scsi_low_msgin(slp, ti, derror | regv) == 0)
1218 {
1219 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1220 {
1221 scsi_low_attention(slp);
1222 }
1223 }
1224
1225 /* read data with ACK */
1226 if (regv != bus_read_1(sc->port_res, tmc_rdata))
1227 {
1228 device_printf(slp->sl_dev, "MSGIN: data mismatch\n");
1229 }
1230
1231 /* wait for the ack negated */
1232 stg_negate_signal(sc, BSTAT_ACK, "msgin<ACK>");
1233
1234 if (slp->sl_msgphase != 0 && slp->sl_msgphase < MSGPH_ABORT)
1235 {
1236 stg_disconnected(sc, ti);
1237 }
1238 break;
1239
1240 case BUSFREE_PHASE:
1241 device_printf(slp->sl_dev, "unexpected disconnect\n");
1242 stg_disconnected(sc, ti);
1243 break;
1244
1245 default:
1246 slp->sl_error |= FATALIO;
1247 device_printf(slp->sl_dev, "unknown phase bus %x intr %x\n",
1248 status, astatus);
1249 break;
1250 }
1251
1252 out:
1253 bus_write_1(sc->port_res, tmc_ictl, sc->sc_icinit);
1254 return 1;
1255 }
1256
1257 static int
stg_timeout(sc)1258 stg_timeout(sc)
1259 struct stg_softc *sc;
1260 {
1261 struct scsi_low_softc *slp = &sc->sc_sclow;
1262 int tout, count;
1263 u_int8_t status;
1264
1265 if (slp->sl_Tnexus == NULL)
1266 return 0;
1267
1268 status = bus_read_1(sc->port_res, tmc_bstat);
1269 if ((status & PHASE_MASK) == 0)
1270 {
1271 if (sc->sc_ubf_timeout ++ == 0)
1272 return 0;
1273
1274 device_printf(slp->sl_dev, "unexpected bus free detected\n");
1275 slp->sl_error |= FATALIO;
1276 scsi_low_print(slp, slp->sl_Tnexus);
1277 stg_disconnected(sc, slp->sl_Tnexus);
1278 return 0;
1279 }
1280
1281 switch (status & PHASE_MASK)
1282 {
1283 case DATA_OUT_PHASE:
1284 if (sc->sc_dataout_timeout == 0)
1285 break;
1286 if ((status & BSTAT_REQ) == 0)
1287 break;
1288 if (bus_read_2(sc->port_res, tmc_fdcnt) != 0)
1289 break;
1290 if ((-- sc->sc_dataout_timeout) > 0)
1291 break;
1292
1293 slp->sl_error |= PDMAERR;
1294 if ((slp->sl_flags & HW_WRITE_PADDING) == 0)
1295 {
1296 device_printf(slp->sl_dev, "write padding required\n");
1297 break;
1298 }
1299
1300 bus_write_1(sc->port_res, tmc_ictl, 0);
1301
1302 tout = STG_DELAY_MAX;
1303 while (tout --)
1304 {
1305 status = bus_read_1(sc->port_res, tmc_bstat);
1306 if ((status & PHASE_MASK) != DATA_OUT_PHASE)
1307 break;
1308
1309 if (bus_read_2(sc->port_res, tmc_fdcnt) != 0)
1310 {
1311 DELAY(1);
1312 continue;
1313 }
1314
1315 for (count = sc->sc_maxwsize; count > 0; count --)
1316 bus_write_1(sc->port_res, tmc_wfifo, 0);
1317 }
1318
1319 status = bus_read_1(sc->port_res, tmc_bstat);
1320 if ((status & PHASE_MASK) == DATA_OUT_PHASE)
1321 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ;
1322
1323 bus_write_1(sc->port_res, tmc_ictl, sc->sc_icinit);
1324 break;
1325
1326 default:
1327 break;
1328 }
1329 return 0;
1330 }
1331