1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2010 Alexander Motin <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/malloc.h>
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/sbuf.h>
40 #include <vm/uma.h>
41 #include <machine/stdarg.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
44 #include <sys/rman.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include "mvs.h"
48
49 /* local prototypes */
50 static int mvs_setup_interrupt(device_t dev);
51 static void mvs_intr(void *data);
52 static int mvs_suspend(device_t dev);
53 static int mvs_resume(device_t dev);
54 static int mvs_ctlr_setup(device_t dev);
55
56 static struct {
57 uint32_t id;
58 uint8_t rev;
59 const char *name;
60 int ports;
61 int quirks;
62 } mvs_ids[] = {
63 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI},
64 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI},
65 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI},
66 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI},
67 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII},
68 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII},
69 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE},
70 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII},
71 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII},
72 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT},
73 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII},
74 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT},
75 {0x00000000, 0x00, NULL, 0, 0}
76 };
77
78 static int
mvs_probe(device_t dev)79 mvs_probe(device_t dev)
80 {
81 int i;
82 uint32_t devid = pci_get_devid(dev);
83 uint8_t revid = pci_get_revid(dev);
84
85 for (i = 0; mvs_ids[i].id != 0; i++) {
86 if (mvs_ids[i].id == devid &&
87 mvs_ids[i].rev <= revid) {
88 device_set_descf(dev, "%s SATA controller",
89 mvs_ids[i].name);
90 return (BUS_PROBE_DEFAULT);
91 }
92 }
93 return (ENXIO);
94 }
95
96 static int
mvs_attach(device_t dev)97 mvs_attach(device_t dev)
98 {
99 struct mvs_controller *ctlr = device_get_softc(dev);
100 device_t child;
101 int error, unit, i;
102 uint32_t devid = pci_get_devid(dev);
103 uint8_t revid = pci_get_revid(dev);
104
105 ctlr->dev = dev;
106 i = 0;
107 while (mvs_ids[i].id != 0 &&
108 (mvs_ids[i].id != devid ||
109 mvs_ids[i].rev > revid))
110 i++;
111 ctlr->channels = mvs_ids[i].ports;
112 ctlr->quirks = mvs_ids[i].quirks;
113 ctlr->ccc = 0;
114 resource_int_value(device_get_name(dev),
115 device_get_unit(dev), "ccc", &ctlr->ccc);
116 ctlr->cccc = 8;
117 resource_int_value(device_get_name(dev),
118 device_get_unit(dev), "cccc", &ctlr->cccc);
119 if (ctlr->ccc == 0 || ctlr->cccc == 0) {
120 ctlr->ccc = 0;
121 ctlr->cccc = 0;
122 }
123 if (ctlr->ccc > 100000)
124 ctlr->ccc = 100000;
125 device_printf(dev,
126 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
127 ((ctlr->quirks & MVS_Q_GENI) ? "I" :
128 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
129 ctlr->channels,
130 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
131 ((ctlr->quirks & MVS_Q_GENI) ?
132 "not supported" : "supported"),
133 ((ctlr->quirks & MVS_Q_GENIIE) ?
134 " with FBS" : ""));
135 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
136 /* We should have a memory BAR(0). */
137 ctlr->r_rid = PCIR_BAR(0);
138 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
139 &ctlr->r_rid, RF_ACTIVE)))
140 return ENXIO;
141 /* Setup our own memory management for channels. */
142 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
143 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
144 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
145 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
146 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
147 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
148 return (error);
149 }
150 if ((error = rman_manage_region(&ctlr->sc_iomem,
151 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
152 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
153 rman_fini(&ctlr->sc_iomem);
154 return (error);
155 }
156 pci_enable_busmaster(dev);
157 mvs_ctlr_setup(dev);
158 /* Setup interrupts. */
159 if (mvs_setup_interrupt(dev)) {
160 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
161 rman_fini(&ctlr->sc_iomem);
162 return ENXIO;
163 }
164 /* Attach all channels on this controller */
165 for (unit = 0; unit < ctlr->channels; unit++) {
166 child = device_add_child(dev, "mvsch", -1);
167 if (child == NULL)
168 device_printf(dev, "failed to add channel device\n");
169 else
170 device_set_ivars(child, (void *)(intptr_t)unit);
171 }
172 bus_generic_attach(dev);
173 return 0;
174 }
175
176 static int
mvs_detach(device_t dev)177 mvs_detach(device_t dev)
178 {
179 struct mvs_controller *ctlr = device_get_softc(dev);
180
181 /* Detach & delete all children */
182 device_delete_children(dev);
183
184 /* Free interrupt. */
185 if (ctlr->irq.r_irq) {
186 bus_teardown_intr(dev, ctlr->irq.r_irq,
187 ctlr->irq.handle);
188 bus_release_resource(dev, SYS_RES_IRQ,
189 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
190 }
191 pci_release_msi(dev);
192 /* Free memory. */
193 rman_fini(&ctlr->sc_iomem);
194 if (ctlr->r_mem)
195 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
196 mtx_destroy(&ctlr->mtx);
197 return (0);
198 }
199
200 static int
mvs_ctlr_setup(device_t dev)201 mvs_ctlr_setup(device_t dev)
202 {
203 struct mvs_controller *ctlr = device_get_softc(dev);
204 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
205
206 /* Mask chip interrupts */
207 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
208 /* Mask PCI interrupts */
209 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
210 /* Clear PCI interrupts */
211 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
212 if (ccc && bootverbose) {
213 device_printf(dev,
214 "CCC with %dus/%dcmd enabled\n",
215 ctlr->ccc, ctlr->cccc);
216 }
217 ccc *= 150;
218 /* Configure chip-global CCC */
219 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
220 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
221 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
222 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
223 if (ccc)
224 ccim |= IC_ALL_PORTS_COAL_DONE;
225 ccc = 0;
226 cccc = 0;
227 }
228 for (i = 0; i < ctlr->channels / 4; i++) {
229 /* Configure per-HC CCC */
230 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
231 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
232 if (ccc)
233 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT));
234 /* Clear HC interrupts */
235 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
236 }
237 /* Enable chip interrupts */
238 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
239 IC_ERR_HC0 | IC_ERR_HC1;
240 ctlr->mim = ctlr->gmim | ctlr->pmim;
241 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
242 /* Enable PCI interrupts */
243 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
244 return (0);
245 }
246
247 static void
mvs_edma(device_t dev,device_t child,int mode)248 mvs_edma(device_t dev, device_t child, int mode)
249 {
250 struct mvs_controller *ctlr = device_get_softc(dev);
251 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
252 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ;
253
254 if (ctlr->ccc == 0)
255 return;
256 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */
257 mtx_lock(&ctlr->mtx);
258 if (mode == MVS_EDMA_OFF)
259 ctlr->pmim |= bit;
260 else
261 ctlr->pmim &= ~bit;
262 ctlr->mim = ctlr->gmim | ctlr->pmim;
263 if (!ctlr->msia)
264 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
265 mtx_unlock(&ctlr->mtx);
266 }
267
268 static int
mvs_suspend(device_t dev)269 mvs_suspend(device_t dev)
270 {
271 struct mvs_controller *ctlr = device_get_softc(dev);
272
273 bus_generic_suspend(dev);
274 /* Mask chip interrupts */
275 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
276 /* Mask PCI interrupts */
277 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
278 return 0;
279 }
280
281 static int
mvs_resume(device_t dev)282 mvs_resume(device_t dev)
283 {
284
285 mvs_ctlr_setup(dev);
286 return (bus_generic_resume(dev));
287 }
288
289 static int
mvs_setup_interrupt(device_t dev)290 mvs_setup_interrupt(device_t dev)
291 {
292 struct mvs_controller *ctlr = device_get_softc(dev);
293 int msi = 0;
294
295 /* Process hints. */
296 resource_int_value(device_get_name(dev),
297 device_get_unit(dev), "msi", &msi);
298 if (msi < 0)
299 msi = 0;
300 else if (msi > 0)
301 msi = min(1, pci_msi_count(dev));
302 /* Allocate MSI if needed/present. */
303 if (msi && pci_alloc_msi(dev, &msi) != 0)
304 msi = 0;
305 ctlr->msi = msi;
306 /* Allocate all IRQs. */
307 ctlr->irq.r_irq_rid = msi ? 1 : 0;
308 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
309 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
310 device_printf(dev, "unable to map interrupt\n");
311 return (ENXIO);
312 }
313 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
314 mvs_intr, ctlr, &ctlr->irq.handle))) {
315 device_printf(dev, "unable to setup interrupt\n");
316 bus_release_resource(dev, SYS_RES_IRQ,
317 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
318 ctlr->irq.r_irq = NULL;
319 return (ENXIO);
320 }
321 return (0);
322 }
323
324 /*
325 * Common case interrupt handler.
326 */
327 static void
mvs_intr(void * data)328 mvs_intr(void *data)
329 {
330 struct mvs_controller *ctlr = data;
331 struct mvs_intr_arg arg;
332 void (*function)(void *);
333 int p;
334 u_int32_t ic, aic;
335
336 ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
337 if (ctlr->msi) {
338 /* We have to mask MSI during processing. */
339 mtx_lock(&ctlr->mtx);
340 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
341 ctlr->msia = 1; /* Deny MIM update during processing. */
342 mtx_unlock(&ctlr->mtx);
343 } else if (ic == 0)
344 return;
345 /* Acknowledge all-ports CCC interrupt. */
346 if (ic & IC_ALL_PORTS_COAL_DONE)
347 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
348 for (p = 0; p < ctlr->channels; p++) {
349 if ((p & 3) == 0) {
350 if (p != 0)
351 ic >>= 1;
352 if ((ic & IC_HC0) == 0) {
353 p += 3;
354 ic >>= 8;
355 continue;
356 }
357 /* Acknowledge interrupts of this HC. */
358 aic = 0;
359 if (ic & (IC_DONE_IRQ << 0))
360 aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
361 if (ic & (IC_DONE_IRQ << 2))
362 aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
363 if (ic & (IC_DONE_IRQ << 4))
364 aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
365 if (ic & (IC_DONE_IRQ << 6))
366 aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
367 if (ic & IC_HC0_COAL_DONE)
368 aic |= HC_IC_COAL;
369 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
370 }
371 /* Call per-port interrupt handler. */
372 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
373 if ((arg.cause != 0) &&
374 (function = ctlr->interrupt[p].function)) {
375 arg.arg = ctlr->interrupt[p].argument;
376 function(&arg);
377 }
378 ic >>= 2;
379 }
380 if (ctlr->msi) {
381 /* Unmasking MSI triggers next interrupt, if needed. */
382 mtx_lock(&ctlr->mtx);
383 ctlr->msia = 0; /* Allow MIM update. */
384 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
385 mtx_unlock(&ctlr->mtx);
386 }
387 }
388
389 static struct resource *
mvs_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)390 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
391 rman_res_t start, rman_res_t end, rman_res_t count,
392 u_int flags)
393 {
394 struct mvs_controller *ctlr = device_get_softc(dev);
395 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
396 struct resource *res = NULL;
397 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03);
398 rman_res_t st;
399
400 switch (type) {
401 case SYS_RES_MEMORY:
402 st = rman_get_start(ctlr->r_mem);
403 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
404 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
405 if (res) {
406 bus_space_handle_t bsh;
407 bus_space_tag_t bst;
408 bsh = rman_get_bushandle(ctlr->r_mem);
409 bst = rman_get_bustag(ctlr->r_mem);
410 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
411 rman_set_bushandle(res, bsh);
412 rman_set_bustag(res, bst);
413 }
414 break;
415 case SYS_RES_IRQ:
416 if (*rid == ATA_IRQ_RID)
417 res = ctlr->irq.r_irq;
418 break;
419 }
420 return (res);
421 }
422
423 static int
mvs_release_resource(device_t dev,device_t child,int type,int rid,struct resource * r)424 mvs_release_resource(device_t dev, device_t child, int type, int rid,
425 struct resource *r)
426 {
427
428 switch (type) {
429 case SYS_RES_MEMORY:
430 rman_release_resource(r);
431 return (0);
432 case SYS_RES_IRQ:
433 if (rid != ATA_IRQ_RID)
434 return ENOENT;
435 return (0);
436 }
437 return (EINVAL);
438 }
439
440 static int
mvs_setup_intr(device_t dev,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * function,void * argument,void ** cookiep)441 mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
442 int flags, driver_filter_t *filter, driver_intr_t *function,
443 void *argument, void **cookiep)
444 {
445 struct mvs_controller *ctlr = device_get_softc(dev);
446 int unit = (intptr_t)device_get_ivars(child);
447
448 if (filter != NULL) {
449 printf("mvs.c: we cannot use a filter here\n");
450 return (EINVAL);
451 }
452 ctlr->interrupt[unit].function = function;
453 ctlr->interrupt[unit].argument = argument;
454 return (0);
455 }
456
457 static int
mvs_teardown_intr(device_t dev,device_t child,struct resource * irq,void * cookie)458 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
459 void *cookie)
460 {
461 struct mvs_controller *ctlr = device_get_softc(dev);
462 int unit = (intptr_t)device_get_ivars(child);
463
464 ctlr->interrupt[unit].function = NULL;
465 ctlr->interrupt[unit].argument = NULL;
466 return (0);
467 }
468
469 static int
mvs_print_child(device_t dev,device_t child)470 mvs_print_child(device_t dev, device_t child)
471 {
472 int retval;
473
474 retval = bus_print_child_header(dev, child);
475 retval += printf(" at channel %d",
476 (int)(intptr_t)device_get_ivars(child));
477 retval += bus_print_child_footer(dev, child);
478
479 return (retval);
480 }
481
482 static int
mvs_child_location(device_t dev,device_t child,struct sbuf * sb)483 mvs_child_location(device_t dev, device_t child, struct sbuf *sb)
484 {
485
486 sbuf_printf(sb, "channel=%d",
487 (int)(intptr_t)device_get_ivars(child));
488 return (0);
489 }
490
491 static bus_dma_tag_t
mvs_get_dma_tag(device_t bus,device_t child)492 mvs_get_dma_tag(device_t bus, device_t child)
493 {
494
495 return (bus_get_dma_tag(bus));
496 }
497
498 static device_method_t mvs_methods[] = {
499 DEVMETHOD(device_probe, mvs_probe),
500 DEVMETHOD(device_attach, mvs_attach),
501 DEVMETHOD(device_detach, mvs_detach),
502 DEVMETHOD(device_suspend, mvs_suspend),
503 DEVMETHOD(device_resume, mvs_resume),
504 DEVMETHOD(bus_print_child, mvs_print_child),
505 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource),
506 DEVMETHOD(bus_release_resource, mvs_release_resource),
507 DEVMETHOD(bus_setup_intr, mvs_setup_intr),
508 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
509 DEVMETHOD(bus_child_location, mvs_child_location),
510 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag),
511 DEVMETHOD(mvs_edma, mvs_edma),
512 { 0, 0 }
513 };
514 static driver_t mvs_driver = {
515 "mvs",
516 mvs_methods,
517 sizeof(struct mvs_controller)
518 };
519 DRIVER_MODULE(mvs, pci, mvs_driver, 0, 0);
520 MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids,
521 nitems(mvs_ids) - 1);
522 MODULE_VERSION(mvs, 1);
523 MODULE_DEPEND(mvs, cam, 1, 1, 1);
524