1 /*- 2 * Hardware specification of various 8696x based Ethernet cards. 3 * Contributed by M. Sekiguchi <[email protected]> 4 * 5 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 6 * 7 * This software may be used, modified, copied, distributed, and sold, 8 * in both source and binary form provided that the above copyright, 9 * these terms and the following disclaimer are retained. The name of 10 * the author and/or the contributor may not be used to endorse or 11 * promote products derived from this software without specific prior 12 * written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 29 /* 30 * Registers on FMV-180 series' ISA bus interface ASIC. 31 * I'm not sure the following register names are appropriate. 32 * Doesn't it look silly, eh? FIXME. 33 */ 34 35 #define FE_FMV0 16 /* Card status register #0 */ 36 #define FE_FMV1 17 /* Card status register #1 */ 37 #define FE_FMV2 18 /* Card config register #0 */ 38 #define FE_FMV3 19 /* Card config register #1 */ 39 #define FE_FMV4 20 /* Station address #1 */ 40 #define FE_FMV5 21 /* Station address #2 */ 41 #define FE_FMV6 22 /* Station address #3 */ 42 #define FE_FMV7 23 /* Station address #4 */ 43 #define FE_FMV8 24 /* Station address #5 */ 44 #define FE_FMV9 25 /* Station address #6 */ 45 #define FE_FMV10 26 /* Buffer RAM control register */ 46 #define FE_FMV11 27 /* Buffer RAM data register */ 47 48 /* 49 * FMV-180 series' ASIC register values. 50 */ 51 52 /* FMV0: Card status register #0: Misc info? */ 53 #define FE_FMV0_MEDIA 0x07 /* Supported physical media. */ 54 #define FE_FMV0_PRRDY 0x10 /* ??? */ 55 #define FE_FMV0_PRERR 0x20 /* ??? */ 56 #define FE_FMV0_ERRDY 0x40 /* ??? */ 57 #define FE_FMV0_IREQ 0x80 /* ??? */ 58 59 #define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */ 60 #define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */ 61 #define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */ 62 63 /* Card status register #1: Hardware revision. */ 64 #define FE_FMV1_REV 0x0F /* Card revision */ 65 #define FE_FMV1_UPPER 0xF0 /* Usage unknown */ 66 67 /* Card config register #0: I/O port address assignment. */ 68 #define FE_FMV2_IOS 0x07 /* I/O selection. */ 69 #define FE_FMV2_MES 0x38 /* ??? boot ROM? */ 70 #define FE_FMV2_IRS 0xC0 /* IRQ selection. */ 71 72 #define FE_FMV2_IOS_SHIFT 0 73 #define FE_FMV2_MES_SHIFT 3 74 #define FE_FMV2_IRS_SHIFT 6 75 76 /* Card config register #1: IRQ enable */ 77 #define FE_FMV3_IRQENB 0x80 /* IRQ enable. */ 78 79 80 /* 81 * Register(?) specific to AT1700/RE2000. 82 */ 83 84 #define FE_ATI_RESET 0x1F /* Write to reset the 86965. */ 85 86 /* EEPROM allocation (offsets) of AT1700/RE2000. */ 87 #define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */ 88 #define FE_ATI_EEP_MEDIA 0x18 /* Media type. */ 89 #define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */ 90 #define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */ 91 #define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */ 92 93 /* Value for FE_ATI_EEP_MODEL. */ 94 #define FE_ATI_MODEL_AT1700T 0x00 95 #define FE_ATI_MODEL_AT1700BT 0x01 96 #define FE_ATI_MODEL_AT1700FT 0x02 97 #define FE_ATI_MODEL_AT1700AT 0x03 98 99 100 /* 101 * Registers on MBH10302. 102 */ 103 104 #define FE_MBH0 0x10 /* ??? Including interrupt. */ 105 #define FE_MBH1 0x11 /* ??? */ 106 #define FE_MBH10 0x1A /* Station address. (10 - 15) */ 107 108 /* Values to be set in MBH0 register. */ 109 #define FE_MBH0_MAGIC 0x0D /* Just a magic constant? */ 110 #define FE_MBH0_INTR 0x10 /* Master interrupt control. */ 111 112 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */ 113 #define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */ 114 115 116 /* 117 * Fujitsu MB86965 JLI mode support routines. 118 */ 119 120 /* Datasheet for 86965 explicitly states that it only supports serial 121 * EEPROM with 16 words (32 bytes) capacity. (I.e., 93C06.) However, 122 * ones with 64 words (128 bytes) are available in the marked, namely 123 * 93C46, and are also fully compatible with 86965. It is known that 124 * some boards (e.g., ICL) actually have 93C46 on them and use extra 125 * storage to keep various config info. */ 126 #define JLI_EEPROM_SIZE 128 127 128 129 /* 130 * SSi 78Q8377A support routines. 131 */ 132 #define SSI_EEPROM_SIZE 512 133 #define SSI_DIN 0x01 134 #define SSI_DAT 0x01 135 #define SSI_CSL 0x02 136 #define SSI_CLK 0x04 137 #define SSI_EEP 0x10 138 139 #define FE_SSI_EEP_IRQ 9 /* Irq ??? */ 140 #define FE_SSI_EEP_ADDR 16 /* Station(MAC) address */ 141 #define FE_SSI_EEP_DUPLEX 25 /* Duplex mode ??? */ 142 143 144 /* 145 * TDK/LANX boards support routines. 146 */ 147 148 /* AX012/AX013 equips an X24C01 chip, which has 128 bytes of memory cells. */ 149 #define LNX_EEPROM_SIZE 128 150 151 /* Bit assignments and command definitions for the serial EEPROM 152 interface register in LANX ASIC. */ 153 #define LNX_SDA_HI 0x08 /* Drive SDA line high (logical 1.) */ 154 #define LNX_SDA_LO 0x00 /* Drive SDA line low (logical 0.) */ 155 #define LNX_SDA_FL 0x08 /* Float (don't drive) SDA line. */ 156 #define LNX_SDA_IN 0x01 /* Mask for reading SDA line. */ 157 #define LNX_CLK_HI 0x04 /* Drive clock line high (active.) */ 158 #define LNX_CLK_LO 0x00 /* Drive clock line low (inactive.) */ 159