1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 Nate Lawson (SDG)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/cpu.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/module.h>
36 #include <sys/pcpu.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
39
40 #include <dev/pci/pcivar.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <sys/rman.h>
44
45 #include "cpufreq_if.h"
46
47 /*
48 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
49 * transition available on the ICH2M, 3M, and 4M. It is different from
50 * the newer Pentium-M SpeedStep feature. It offers only two levels of
51 * frequency/voltage. Often, the BIOS will select one of the levels via
52 * SMM code during the power-on process (i.e., choose a lower level if the
53 * system is off AC power.)
54 */
55
56 struct ichss_softc {
57 device_t dev;
58 int bm_rid; /* Bus-mastering control (PM2REG). */
59 struct resource *bm_reg;
60 int ctrl_rid; /* Control/status register. */
61 struct resource *ctrl_reg;
62 struct cf_setting sets[2]; /* Only two settings. */
63 };
64
65 /* Supported PCI IDs. */
66 #define PCI_VENDOR_INTEL 0x8086
67 #define PCI_DEV_82801BA 0x244c /* ICH2M */
68 #define PCI_DEV_82801CA 0x248c /* ICH3M */
69 #define PCI_DEV_82801DB 0x24cc /* ICH4M */
70 #define PCI_DEV_82815_MC 0x1130 /* Unsupported/buggy part */
71
72 /* PCI config registers for finding PMBASE and enabling SpeedStep. */
73 #define ICHSS_PMBASE_OFFSET 0x40
74 #define ICHSS_PMCFG_OFFSET 0xa0
75
76 /* Values and masks. */
77 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */
78 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */
79 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */
80 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */
81 #define ICHSS_BM_DISABLE 0x1
82
83 /* Offsets from PMBASE for various registers. */
84 #define ICHSS_BM_OFFSET 0x20
85 #define ICHSS_CTRL_OFFSET 0x50
86
87 #define ICH_GET_REG(reg) \
88 (bus_space_read_1(rman_get_bustag((reg)), \
89 rman_get_bushandle((reg)), 0))
90 #define ICH_SET_REG(reg, val) \
91 (bus_space_write_1(rman_get_bustag((reg)), \
92 rman_get_bushandle((reg)), 0, (val)))
93
94 static void ichss_identify(driver_t *driver, device_t parent);
95 static int ichss_probe(device_t dev);
96 static int ichss_attach(device_t dev);
97 static int ichss_detach(device_t dev);
98 static int ichss_settings(device_t dev, struct cf_setting *sets,
99 int *count);
100 static int ichss_set(device_t dev, const struct cf_setting *set);
101 static int ichss_get(device_t dev, struct cf_setting *set);
102 static int ichss_type(device_t dev, int *type);
103
104 static device_method_t ichss_methods[] = {
105 /* Device interface */
106 DEVMETHOD(device_identify, ichss_identify),
107 DEVMETHOD(device_probe, ichss_probe),
108 DEVMETHOD(device_attach, ichss_attach),
109 DEVMETHOD(device_detach, ichss_detach),
110
111 /* cpufreq interface */
112 DEVMETHOD(cpufreq_drv_set, ichss_set),
113 DEVMETHOD(cpufreq_drv_get, ichss_get),
114 DEVMETHOD(cpufreq_drv_type, ichss_type),
115 DEVMETHOD(cpufreq_drv_settings, ichss_settings),
116 DEVMETHOD_END
117 };
118
119 static driver_t ichss_driver = {
120 "ichss", ichss_methods, sizeof(struct ichss_softc)
121 };
122
123 DRIVER_MODULE(ichss, cpu, ichss_driver, 0, 0);
124
125 static device_t ich_device;
126
127 #if 0
128 #define DPRINT(x...) printf(x)
129 #else
130 #define DPRINT(x...)
131 #endif
132
133 static void
ichss_identify(driver_t * driver,device_t parent)134 ichss_identify(driver_t *driver, device_t parent)
135 {
136 device_t child;
137 uint32_t pmbase;
138
139 if (resource_disabled("ichss", 0))
140 return;
141
142 /*
143 * It appears that ICH SpeedStep only requires a single CPU to
144 * set the value (since the chipset is shared by all CPUs.)
145 * Thus, we only add a child to cpu 0.
146 */
147 if (device_get_unit(parent) != 0)
148 return;
149
150 /* Avoid duplicates. */
151 if (device_find_child(parent, "ichss", -1))
152 return;
153
154 /*
155 * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0.
156 * E.g. see Section 6.1 "PCI Devices and Functions" and table 6.1 of
157 * Intel(r) 82801BA I/O Controller Hub 2 (ICH2) and Intel(r) 82801BAM
158 * I/O Controller Hub 2 Mobile (ICH2-M).
159 */
160 ich_device = pci_find_bsf(0, 0x1f, 0);
161 if (ich_device == NULL ||
162 pci_get_vendor(ich_device) != PCI_VENDOR_INTEL ||
163 (pci_get_device(ich_device) != PCI_DEV_82801BA &&
164 pci_get_device(ich_device) != PCI_DEV_82801CA &&
165 pci_get_device(ich_device) != PCI_DEV_82801DB))
166 return;
167
168 /*
169 * Certain systems with ICH2 and an Intel 82815_MC host bridge
170 * where the host bridge's revision is < 5 lockup if SpeedStep
171 * is used.
172 */
173 if (pci_get_device(ich_device) == PCI_DEV_82801BA) {
174 device_t hostb;
175
176 hostb = pci_find_bsf(0, 0, 0);
177 if (hostb != NULL &&
178 pci_get_vendor(hostb) == PCI_VENDOR_INTEL &&
179 pci_get_device(hostb) == PCI_DEV_82815_MC &&
180 pci_get_revid(hostb) < 5)
181 return;
182 }
183
184 /* Find the PMBASE register from our PCI config header. */
185 pmbase = pci_read_config(ich_device, ICHSS_PMBASE_OFFSET,
186 sizeof(pmbase));
187 if ((pmbase & ICHSS_IO_REG) == 0) {
188 printf("ichss: invalid PMBASE memory type\n");
189 return;
190 }
191 pmbase &= ICHSS_PMBASE_MASK;
192 if (pmbase == 0) {
193 printf("ichss: invalid zero PMBASE address\n");
194 return;
195 }
196 DPRINT("ichss: PMBASE is %#x\n", pmbase);
197
198 child = BUS_ADD_CHILD(parent, 20, "ichss", 0);
199 if (child == NULL) {
200 device_printf(parent, "add SpeedStep child failed\n");
201 return;
202 }
203
204 /* Add the bus master arbitration and control registers. */
205 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET,
206 1);
207 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET,
208 1);
209 }
210
211 static int
ichss_probe(device_t dev)212 ichss_probe(device_t dev)
213 {
214 device_t est_dev, perf_dev;
215 int error, type;
216
217 /*
218 * If the ACPI perf driver has attached and is not just offering
219 * info, let it manage things. Also, if Enhanced SpeedStep is
220 * available, don't attach.
221 */
222 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
223 if (perf_dev && device_is_attached(perf_dev)) {
224 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
225 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
226 return (ENXIO);
227 }
228 est_dev = device_find_child(device_get_parent(dev), "est", -1);
229 if (est_dev && device_is_attached(est_dev))
230 return (ENXIO);
231
232 device_set_desc(dev, "SpeedStep ICH");
233 return (-1000);
234 }
235
236 static int
ichss_attach(device_t dev)237 ichss_attach(device_t dev)
238 {
239 struct ichss_softc *sc;
240 uint16_t ss_en;
241
242 sc = device_get_softc(dev);
243 sc->dev = dev;
244
245 sc->bm_rid = 0;
246 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
247 RF_ACTIVE);
248 if (sc->bm_reg == NULL) {
249 device_printf(dev, "failed to alloc BM arb register\n");
250 return (ENXIO);
251 }
252 sc->ctrl_rid = 1;
253 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
254 &sc->ctrl_rid, RF_ACTIVE);
255 if (sc->ctrl_reg == NULL) {
256 device_printf(dev, "failed to alloc control register\n");
257 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
258 sc->bm_reg);
259 return (ENXIO);
260 }
261
262 /* Activate SpeedStep control if not already enabled. */
263 ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
264 if ((ss_en & ICHSS_ENABLE) == 0) {
265 device_printf(dev, "enabling SpeedStep support\n");
266 pci_write_config(ich_device, ICHSS_PMCFG_OFFSET,
267 ss_en | ICHSS_ENABLE, sizeof(ss_en));
268 }
269
270 /* Setup some defaults for our exported settings. */
271 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
272 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
273 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
274 sc->sets[0].lat = 1000;
275 sc->sets[0].dev = dev;
276 sc->sets[1] = sc->sets[0];
277 cpufreq_register(dev);
278
279 return (0);
280 }
281
282 static int
ichss_detach(device_t dev)283 ichss_detach(device_t dev)
284 {
285 /* TODO: teardown BM and CTRL registers. */
286 return (ENXIO);
287 }
288
289 static int
ichss_settings(device_t dev,struct cf_setting * sets,int * count)290 ichss_settings(device_t dev, struct cf_setting *sets, int *count)
291 {
292 struct ichss_softc *sc;
293 struct cf_setting set;
294 int first, i;
295
296 if (sets == NULL || count == NULL)
297 return (EINVAL);
298 if (*count < 2) {
299 *count = 2;
300 return (E2BIG);
301 }
302 sc = device_get_softc(dev);
303
304 /*
305 * Estimate frequencies for both levels, temporarily switching to
306 * the other one if we haven't calibrated it yet.
307 */
308 ichss_get(dev, &set);
309 for (i = 0; i < 2; i++) {
310 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
311 first = (i == 0) ? 1 : 0;
312 ichss_set(dev, &sc->sets[i]);
313 ichss_set(dev, &sc->sets[first]);
314 }
315 }
316
317 bcopy(sc->sets, sets, sizeof(sc->sets));
318 *count = 2;
319
320 return (0);
321 }
322
323 static int
ichss_set(device_t dev,const struct cf_setting * set)324 ichss_set(device_t dev, const struct cf_setting *set)
325 {
326 struct ichss_softc *sc;
327 uint8_t bmval, new_val, old_val, req_val;
328 uint64_t rate;
329 register_t regs;
330
331 /* Look up appropriate bit value based on frequency. */
332 sc = device_get_softc(dev);
333 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
334 req_val = 0;
335 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
336 req_val = ICHSS_CTRL_BIT;
337 else
338 return (EINVAL);
339 DPRINT("ichss: requested setting %d\n", req_val);
340
341 /* Disable interrupts and get the other register contents. */
342 regs = intr_disable();
343 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
344
345 /*
346 * Disable bus master arbitration, write the new value to the control
347 * register, and then re-enable bus master arbitration.
348 */
349 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;
350 ICH_SET_REG(sc->bm_reg, bmval);
351 ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
352 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);
353
354 /* Get the new value and re-enable interrupts. */
355 new_val = ICH_GET_REG(sc->ctrl_reg);
356 intr_restore(regs);
357
358 /* Check if the desired state was indeed selected. */
359 if (req_val != (new_val & ICHSS_CTRL_BIT)) {
360 device_printf(sc->dev, "transition to %d failed\n", req_val);
361 return (ENXIO);
362 }
363
364 /* Re-initialize our cycle counter if we don't know this new state. */
365 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {
366 cpu_est_clockrate(0, &rate);
367 sc->sets[req_val].freq = rate / 1000000;
368 DPRINT("ichss: set calibrated new rate of %d\n",
369 sc->sets[req_val].freq);
370 }
371
372 return (0);
373 }
374
375 static int
ichss_get(device_t dev,struct cf_setting * set)376 ichss_get(device_t dev, struct cf_setting *set)
377 {
378 struct ichss_softc *sc;
379 uint64_t rate;
380 uint8_t state;
381
382 sc = device_get_softc(dev);
383 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
384
385 /* If we haven't changed settings yet, estimate the current value. */
386 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
387 cpu_est_clockrate(0, &rate);
388 sc->sets[state].freq = rate / 1000000;
389 DPRINT("ichss: get calibrated new rate of %d\n",
390 sc->sets[state].freq);
391 }
392 *set = sc->sets[state];
393
394 return (0);
395 }
396
397 static int
ichss_type(device_t dev,int * type)398 ichss_type(device_t dev, int *type)
399 {
400
401 if (type == NULL)
402 return (EINVAL);
403
404 *type = CPUFREQ_TYPE_ABSOLUTE;
405 return (0);
406 }
407