1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * Driver for the Atheros Wireless LAN controller.
37 *
38 * This software is derived from work of Atsushi Onoe; his contribution
39 * is greatly appreciated.
40 */
41
42 #include "opt_inet.h"
43 #include "opt_ath.h"
44 /*
45 * This is needed for register operations which are performed
46 * by the driver - eg, calls to ath_hal_gettsf32().
47 *
48 * It's also required for any AH_DEBUG checks in here, eg the
49 * module dependencies.
50 */
51 #include "opt_ah.h"
52 #include "opt_wlan.h"
53
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
57 #include <sys/mbuf.h>
58 #include <sys/malloc.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/kernel.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/errno.h>
65 #include <sys/callout.h>
66 #include <sys/bus.h>
67 #include <sys/endian.h>
68 #include <sys/kthread.h>
69 #include <sys/taskqueue.h>
70 #include <sys/priv.h>
71 #include <sys/module.h>
72 #include <sys/ktr.h>
73 #include <sys/smp.h> /* for mp_ncpus */
74
75 #include <machine/bus.h>
76
77 #include <net/if.h>
78 #include <net/if_var.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_types.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_llc.h>
85
86 #include <net80211/ieee80211_var.h>
87 #include <net80211/ieee80211_regdomain.h>
88 #ifdef IEEE80211_SUPPORT_SUPERG
89 #include <net80211/ieee80211_superg.h>
90 #endif
91 #ifdef IEEE80211_SUPPORT_TDMA
92 #include <net80211/ieee80211_tdma.h>
93 #endif
94
95 #include <net/bpf.h>
96
97 #ifdef INET
98 #include <netinet/in.h>
99 #include <netinet/if_ether.h>
100 #endif
101
102 #include <dev/ath/if_athvar.h>
103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
104 #include <dev/ath/ath_hal/ah_diagcodes.h>
105
106 #include <dev/ath/if_ath_debug.h>
107 #include <dev/ath/if_ath_misc.h>
108 #include <dev/ath/if_ath_tsf.h>
109 #include <dev/ath/if_ath_tx.h>
110 #include <dev/ath/if_ath_sysctl.h>
111 #include <dev/ath/if_ath_led.h>
112 #include <dev/ath/if_ath_keycache.h>
113 #include <dev/ath/if_ath_rx.h>
114 #include <dev/ath/if_ath_beacon.h>
115 #include <dev/ath/if_athdfs.h>
116 #include <dev/ath/if_ath_descdma.h>
117
118 #ifdef ATH_TX99_DIAG
119 #include <dev/ath/ath_tx99/ath_tx99.h>
120 #endif
121
122 #ifdef ATH_DEBUG_ALQ
123 #include <dev/ath/if_ath_alq.h>
124 #endif
125
126 #include <dev/ath/if_ath_lna_div.h>
127
128 /*
129 * Calculate the receive filter according to the
130 * operating mode and state:
131 *
132 * o always accept unicast, broadcast, and multicast traffic
133 * o accept PHY error frames when hardware doesn't have MIB support
134 * to count and we need them for ANI (sta mode only until recently)
135 * and we are not scanning (ANI is disabled)
136 * NB: older hal's add rx filter bits out of sight and we need to
137 * blindly preserve them
138 * o probe request frames are accepted only when operating in
139 * hostap, adhoc, mesh, or monitor modes
140 * o enable promiscuous mode
141 * - when in monitor mode
142 * - if interface marked PROMISC (assumes bridge setting is filtered)
143 * o accept beacons:
144 * - when operating in station mode for collecting rssi data when
145 * the station is otherwise quiet, or
146 * - when operating in adhoc mode so the 802.11 layer creates
147 * node table entries for peers,
148 * - when scanning
149 * - when doing s/w beacon miss (e.g. for ap+sta)
150 * - when operating in ap mode in 11g to detect overlapping bss that
151 * require protection
152 * - when operating in mesh mode to detect neighbors
153 * o accept control frames:
154 * - when in monitor mode
155 * XXX HT protection for 11n
156 */
157 u_int32_t
ath_calcrxfilter(struct ath_softc * sc)158 ath_calcrxfilter(struct ath_softc *sc)
159 {
160 struct ieee80211com *ic = &sc->sc_ic;
161 u_int32_t rfilt;
162
163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
164 if (!sc->sc_needmib && !sc->sc_scanning)
165 rfilt |= HAL_RX_FILTER_PHYERR;
166 if (ic->ic_opmode != IEEE80211_M_STA)
167 rfilt |= HAL_RX_FILTER_PROBEREQ;
168 /* XXX ic->ic_monvaps != 0? */
169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0)
170 rfilt |= HAL_RX_FILTER_PROM;
171
172 /*
173 * Only listen to all beacons if we're scanning.
174 *
175 * Otherwise we only really need to hear beacons from
176 * our own BSSID.
177 *
178 * IBSS? software beacon miss? Just receive all beacons.
179 * We need to hear beacons/probe requests from everyone so
180 * we can merge ibss.
181 */
182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) {
183 rfilt |= HAL_RX_FILTER_BEACON;
184 } else if (ic->ic_opmode == IEEE80211_M_STA) {
185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) {
186 rfilt |= HAL_RX_FILTER_MYBEACON;
187 } else { /* scanning, non-mybeacon chips */
188 rfilt |= HAL_RX_FILTER_BEACON;
189 }
190 }
191
192 /*
193 * NB: We don't recalculate the rx filter when
194 * ic_protmode changes; otherwise we could do
195 * this only when ic_protmode != NONE.
196 */
197 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
199 rfilt |= HAL_RX_FILTER_BEACON;
200
201 /*
202 * Enable hardware PS-POLL RX only for hostap mode;
203 * STA mode sends PS-POLL frames but never
204 * receives them.
205 */
206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
207 0, NULL) == HAL_OK &&
208 ic->ic_opmode == IEEE80211_M_HOSTAP)
209 rfilt |= HAL_RX_FILTER_PSPOLL;
210
211 if (sc->sc_nmeshvaps) {
212 rfilt |= HAL_RX_FILTER_BEACON;
213 if (sc->sc_hasbmatch)
214 rfilt |= HAL_RX_FILTER_BSSID;
215 else
216 rfilt |= HAL_RX_FILTER_PROM;
217 }
218 if (ic->ic_opmode == IEEE80211_M_MONITOR)
219 rfilt |= HAL_RX_FILTER_CONTROL;
220
221 /*
222 * Enable RX of compressed BAR frames only when doing
223 * 802.11n. Required for A-MPDU.
224 */
225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
226 rfilt |= HAL_RX_FILTER_COMPBAR;
227
228 /*
229 * Enable radar PHY errors if requested by the
230 * DFS module.
231 */
232 if (sc->sc_dodfs)
233 rfilt |= HAL_RX_FILTER_PHYRADAR;
234
235 /*
236 * Enable spectral PHY errors if requested by the
237 * spectral module.
238 */
239 if (sc->sc_dospectral)
240 rfilt |= HAL_RX_FILTER_PHYRADAR;
241
242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n",
243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]);
244 return rfilt;
245 }
246
247 static int
ath_legacy_rxbuf_init(struct ath_softc * sc,struct ath_buf * bf)248 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
249 {
250 struct ath_hal *ah = sc->sc_ah;
251 int error;
252 struct mbuf *m;
253 struct ath_desc *ds;
254
255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */
256
257 m = bf->bf_m;
258 if (m == NULL) {
259 /*
260 * NB: by assigning a page to the rx dma buffer we
261 * implicitly satisfy the Atheros requirement that
262 * this buffer be cache-line-aligned and sized to be
263 * multiple of the cache line size. Not doing this
264 * causes weird stuff to happen (for the 5210 at least).
265 */
266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
267 if (m == NULL) {
268 DPRINTF(sc, ATH_DEBUG_ANY,
269 "%s: no mbuf/cluster\n", __func__);
270 sc->sc_stats.ast_rx_nombuf++;
271 return ENOMEM;
272 }
273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
274
275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
276 bf->bf_dmamap, m,
277 bf->bf_segs, &bf->bf_nseg,
278 BUS_DMA_NOWAIT);
279 if (error != 0) {
280 DPRINTF(sc, ATH_DEBUG_ANY,
281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
282 __func__, error);
283 sc->sc_stats.ast_rx_busdma++;
284 m_freem(m);
285 return error;
286 }
287 KASSERT(bf->bf_nseg == 1,
288 ("multi-segment packet; nseg %u", bf->bf_nseg));
289 bf->bf_m = m;
290 }
291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
292
293 /*
294 * Setup descriptors. For receive we always terminate
295 * the descriptor list with a self-linked entry so we'll
296 * not get overrun under high load (as can happen with a
297 * 5212 when ANI processing enables PHY error frames).
298 *
299 * To insure the last descriptor is self-linked we create
300 * each descriptor as self-linked and add it to the end. As
301 * each additional descriptor is added the previous self-linked
302 * entry is ``fixed'' naturally. This should be safe even
303 * if DMA is happening. When processing RX interrupts we
304 * never remove/process the last, self-linked, entry on the
305 * descriptor list. This insures the hardware always has
306 * someplace to write a new frame.
307 */
308 /*
309 * 11N: we can no longer afford to self link the last descriptor.
310 * MAC acknowledges BA status as long as it copies frames to host
311 * buffer (or rx fifo). This can incorrectly acknowledge packets
312 * to a sender if last desc is self-linked.
313 */
314 ds = bf->bf_desc;
315 if (sc->sc_rxslink)
316 ds->ds_link = bf->bf_daddr; /* link to self */
317 else
318 ds->ds_link = 0; /* terminate the list */
319 ds->ds_data = bf->bf_segs[0].ds_addr;
320 ath_hal_setuprxdesc(ah, ds
321 , m->m_len /* buffer size */
322 , 0
323 );
324
325 if (sc->sc_rxlink != NULL)
326 *sc->sc_rxlink = bf->bf_daddr;
327 sc->sc_rxlink = &ds->ds_link;
328 return 0;
329 }
330
331 /*
332 * Intercept management frames to collect beacon rssi data
333 * and to do ibss merges.
334 */
335 void
ath_recv_mgmt(struct ieee80211_node * ni,struct mbuf * m,int subtype,const struct ieee80211_rx_stats * rxs,int rssi,int nf)336 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf)
338 {
339 struct ieee80211vap *vap = ni->ni_vap;
340 struct ath_softc *sc = vap->iv_ic->ic_softc;
341 uint64_t tsf_beacon_old, tsf_beacon;
342 uint64_t nexttbtt;
343 int64_t tsf_delta;
344 int32_t tsf_delta_bmiss;
345 int32_t tsf_remainder;
346 uint64_t tsf_beacon_target;
347 int tsf_intval;
348
349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data);
351
352 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
353 tsf_intval = 1;
354 if (ni->ni_intval > 0) {
355 tsf_intval = TU_TO_TSF(ni->ni_intval);
356 }
357 #undef TU_TO_TSF
358
359 /*
360 * Call up first so subsequent work can use information
361 * potentially stored in the node (e.g. for ibss merge).
362 */
363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf);
364 switch (subtype) {
365 case IEEE80211_FC0_SUBTYPE_BEACON:
366 /*
367 * Always update the per-node beacon RSSI if we're hearing
368 * beacons from that node.
369 */
370 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi);
371
372 /*
373 * Only do the following processing if it's for
374 * the current BSS.
375 *
376 * In scan and IBSS mode we receive all beacons,
377 * which means we need to filter out stuff
378 * that isn't for us or we'll end up constantly
379 * trying to sync / merge to BSSes that aren't
380 * actually us.
381 */
382 if ((vap->iv_opmode != IEEE80211_M_HOSTAP) &&
383 IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) {
384 /* update rssi statistics for use by the hal */
385 /* XXX unlocked check against vap->iv_bss? */
386 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
387
388 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
389 tsf_beacon |= le32dec(ni->ni_tstamp.data);
390
391 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah);
392
393 /*
394 * Let's calculate the delta and remainder, so we can see
395 * if the beacon timer from the AP is varying by more than
396 * a few TU. (Which would be a huge, huge problem.)
397 */
398 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old;
399
400 tsf_delta_bmiss = tsf_delta / tsf_intval;
401
402 /*
403 * If our delta is greater than half the beacon interval,
404 * let's round the bmiss value up to the next beacon
405 * interval. Ie, we're running really, really early
406 * on the next beacon.
407 */
408 if (tsf_delta % tsf_intval > (tsf_intval / 2))
409 tsf_delta_bmiss ++;
410
411 tsf_beacon_target = tsf_beacon_old +
412 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval);
413
414 /*
415 * The remainder using '%' is between 0 .. intval-1.
416 * If we're actually running too fast, then the remainder
417 * will be some large number just under intval-1.
418 * So we need to look at whether we're running
419 * before or after the target beacon interval
420 * and if we are, modify how we do the remainder
421 * calculation.
422 */
423 if (tsf_beacon < tsf_beacon_target) {
424 tsf_remainder =
425 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval));
426 } else {
427 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval;
428 }
429
430 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n",
431 __func__,
432 ieee80211_get_vap_ifname(vap),
433 (unsigned long long) tsf_beacon_old,
434 (unsigned int) (tsf_beacon_old >> 10),
435 (unsigned long long) tsf_beacon,
436 (unsigned int ) (tsf_beacon >> 10),
437 (unsigned long long) tsf_beacon_target,
438 (unsigned int) (tsf_beacon_target >> 10),
439 (long long) tsf_delta,
440 tsf_delta_bmiss,
441 tsf_remainder);
442
443 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: ni=%6D bssid=%6D tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n",
444 __func__,
445 ieee80211_get_vap_ifname(vap),
446 ni->ni_bssid, ":",
447 vap->iv_bss->ni_bssid, ":",
448 (unsigned long long) tsf_beacon,
449 (unsigned int) (tsf_beacon >> 10),
450 (unsigned long long) nexttbtt,
451 (unsigned int) (nexttbtt >> 10),
452 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval);
453
454 /*
455 * We only do syncbeacon on STA VAPs; not on IBSS;
456 * but don't do it with swbmiss enabled or we
457 * may end up overwriting AP mode beacon config.
458 *
459 * The driver (and net80211) should be smarter about
460 * this..
461 */
462 if (vap->iv_opmode == IEEE80211_M_STA &&
463 sc->sc_syncbeacon &&
464 (!sc->sc_swbmiss) &&
465 ni == vap->iv_bss &&
466 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) {
467 DPRINTF(sc, ATH_DEBUG_BEACON,
468 "%s: syncbeacon=1; syncing\n",
469 __func__);
470 /*
471 * Resync beacon timers using the tsf of the beacon
472 * frame we just received.
473 */
474 ath_beacon_config(sc, vap);
475 sc->sc_syncbeacon = 0;
476 }
477 }
478
479 /* fall thru... */
480 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
481 if (vap->iv_opmode == IEEE80211_M_IBSS &&
482 vap->iv_state == IEEE80211_S_RUN &&
483 ieee80211_ibss_merge_check(ni)) {
484 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
485 uint64_t tsf = ath_extend_tsf(sc, rstamp,
486 ath_hal_gettsf64(sc->sc_ah));
487 /*
488 * Handle ibss merge as needed; check the tsf on the
489 * frame before attempting the merge. The 802.11 spec
490 * says the station should change it's bssid to match
491 * the oldest station with the same ssid, where oldest
492 * is determined by the tsf. Note that hardware
493 * reconfiguration happens through callback to
494 * ath_newstate as the state machine will go from
495 * RUN -> RUN when this happens.
496 */
497 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
498 DPRINTF(sc, ATH_DEBUG_STATE,
499 "ibss merge, rstamp %u tsf %ju "
500 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
501 (uintmax_t)ni->ni_tstamp.tsf);
502 (void) ieee80211_ibss_merge(ni);
503 }
504 }
505 break;
506 }
507 }
508
509 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
510 static void
ath_rx_tap_vendor(struct ath_softc * sc,struct mbuf * m,const struct ath_rx_status * rs,u_int64_t tsf,int16_t nf)511 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m,
512 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
513 {
514
515 /* Fill in the extension bitmap */
516 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
517
518 /* Fill in the vendor header */
519 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
520 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
521 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
522
523 /* XXX what should this be? */
524 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
525 sc->sc_rx_th.wr_vh.vh_skip_len =
526 htole16(sizeof(struct ath_radiotap_vendor_hdr));
527
528 /* General version info */
529 sc->sc_rx_th.wr_v.vh_version = 1;
530
531 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
532
533 /* rssi */
534 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
535 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
536 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
537 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
538 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
539 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
540
541 /* evm */
542 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
543 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
544 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
545 /* These are only populated from the AR9300 or later */
546 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
547 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
548
549 /* direction */
550 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX;
551
552 /* RX rate */
553 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate;
554
555 /* RX flags */
556 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags;
557
558 if (rs->rs_isaggr)
559 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR;
560 if (rs->rs_moreaggr)
561 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR;
562
563 /* phyerr info */
564 if (rs->rs_status & HAL_RXERR_PHY) {
565 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
566 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR;
567 } else {
568 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
569 }
570 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
571 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
572 }
573 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
574
575 static void
ath_rx_tap(struct ath_softc * sc,struct mbuf * m,const struct ath_rx_status * rs,u_int64_t tsf,int16_t nf)576 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
577 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
578 {
579 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
580 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
581 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
582 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
583 const HAL_RATE_TABLE *rt;
584 uint8_t rix;
585
586 rt = sc->sc_currates;
587 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
588 rix = rt->rateCodeToIndex[rs->rs_rate];
589 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
590 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
591
592 /* 802.11 specific flags */
593 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
594 if (rs->rs_status & HAL_RXERR_PHY) {
595 /*
596 * PHY error - make sure the channel flags
597 * reflect the actual channel configuration,
598 * not the received frame.
599 */
600 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
601 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
602 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
603 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
604 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
605 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
606 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
607 struct ieee80211com *ic = &sc->sc_ic;
608
609 if ((rs->rs_flags & HAL_RX_2040) == 0)
610 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
611 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
612 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
613 else
614 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
615
616 if (rs->rs_flags & HAL_RX_GI)
617 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
618 }
619
620 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
621 if (rs->rs_status & HAL_RXERR_CRC)
622 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
623 /* XXX propagate other error flags from descriptor */
624 sc->sc_rx_th.wr_antnoise = nf;
625 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
626 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
627 #undef CHAN_HT
628 #undef CHAN_HT20
629 #undef CHAN_HT40U
630 #undef CHAN_HT40D
631 }
632
633 static void
ath_handle_micerror(struct ieee80211com * ic,struct ieee80211_frame * wh,int keyix)634 ath_handle_micerror(struct ieee80211com *ic,
635 struct ieee80211_frame *wh, int keyix)
636 {
637 struct ieee80211_node *ni;
638
639 /* XXX recheck MIC to deal w/ chips that lie */
640 /* XXX discard MIC errors on !data frames */
641 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
642 if (ni != NULL) {
643 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
644 ieee80211_free_node(ni);
645 }
646 }
647
648 /*
649 * Process a single packet.
650 *
651 * The mbuf must already be synced, unmapped and removed from bf->bf_m
652 * by this stage.
653 *
654 * The mbuf must be consumed by this routine - either passed up the
655 * net80211 stack, put on the holding queue, or freed.
656 */
657 int
ath_rx_pkt(struct ath_softc * sc,struct ath_rx_status * rs,HAL_STATUS status,uint64_t tsf,int nf,HAL_RX_QUEUE qtype,struct ath_buf * bf,struct mbuf * m)658 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
659 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf,
660 struct mbuf *m)
661 {
662 uint64_t rstamp;
663 /* XXX TODO: make this an mbuf tag? */
664 struct ieee80211_rx_stats rxs;
665 int len, type, i;
666 struct ieee80211com *ic = &sc->sc_ic;
667 struct ieee80211_node *ni;
668 int is_good = 0;
669 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
670
671 NET_EPOCH_ASSERT();
672
673 /*
674 * Calculate the correct 64 bit TSF given
675 * the TSF64 register value and rs_tstamp.
676 */
677 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
678
679 /* 802.11 return codes - These aren't specifically errors */
680 if (rs->rs_flags & HAL_RX_GI)
681 sc->sc_stats.ast_rx_halfgi++;
682 if (rs->rs_flags & HAL_RX_2040)
683 sc->sc_stats.ast_rx_2040++;
684 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
685 sc->sc_stats.ast_rx_pre_crc_err++;
686 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
687 sc->sc_stats.ast_rx_post_crc_err++;
688 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
689 sc->sc_stats.ast_rx_decrypt_busy_err++;
690 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
691 sc->sc_stats.ast_rx_hi_rx_chain++;
692 if (rs->rs_flags & HAL_RX_STBC)
693 sc->sc_stats.ast_rx_stbc++;
694
695 if (rs->rs_status != 0) {
696 if (rs->rs_status & HAL_RXERR_CRC)
697 sc->sc_stats.ast_rx_crcerr++;
698 if (rs->rs_status & HAL_RXERR_FIFO)
699 sc->sc_stats.ast_rx_fifoerr++;
700 if (rs->rs_status & HAL_RXERR_PHY) {
701 sc->sc_stats.ast_rx_phyerr++;
702 /* Process DFS radar events */
703 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
704 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
705 /* Now pass it to the radar processing code */
706 ath_dfs_process_phy_err(sc, m, rstamp, rs);
707 }
708
709 /*
710 * Be suitably paranoid about receiving phy errors
711 * out of the stats array bounds
712 */
713 if (rs->rs_phyerr < ATH_IOCTL_STATS_NUM_RX_PHYERR)
714 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
715 goto rx_error; /* NB: don't count in ierrors */
716 }
717 if (rs->rs_status & HAL_RXERR_DECRYPT) {
718 /*
719 * Decrypt error. If the error occurred
720 * because there was no hardware key, then
721 * let the frame through so the upper layers
722 * can process it. This is necessary for 5210
723 * parts which have no way to setup a ``clear''
724 * key cache entry.
725 *
726 * XXX do key cache faulting
727 */
728 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
729 goto rx_accept;
730 sc->sc_stats.ast_rx_badcrypt++;
731 }
732 /*
733 * Similar as above - if the failure was a keymiss
734 * just punt it up to the upper layers for now.
735 */
736 if (rs->rs_status & HAL_RXERR_KEYMISS) {
737 sc->sc_stats.ast_rx_keymiss++;
738 goto rx_accept;
739 }
740 if (rs->rs_status & HAL_RXERR_MIC) {
741 sc->sc_stats.ast_rx_badmic++;
742 /*
743 * Do minimal work required to hand off
744 * the 802.11 header for notification.
745 */
746 /* XXX frag's and qos frames */
747 len = rs->rs_datalen;
748 if (len >= sizeof (struct ieee80211_frame)) {
749 ath_handle_micerror(ic,
750 mtod(m, struct ieee80211_frame *),
751 sc->sc_splitmic ?
752 rs->rs_keyix-32 : rs->rs_keyix);
753 }
754 }
755 counter_u64_add(ic->ic_ierrors, 1);
756 rx_error:
757 /*
758 * Cleanup any pending partial frame.
759 */
760 if (re->m_rxpending != NULL) {
761 m_freem(re->m_rxpending);
762 re->m_rxpending = NULL;
763 }
764 /*
765 * When a tap is present pass error frames
766 * that have been requested. By default we
767 * pass decrypt+mic errors but others may be
768 * interesting (e.g. crc).
769 */
770 if (ieee80211_radiotap_active(ic) &&
771 (rs->rs_status & sc->sc_monpass)) {
772 /* NB: bpf needs the mbuf length setup */
773 len = rs->rs_datalen;
774 m->m_pkthdr.len = m->m_len = len;
775 ath_rx_tap(sc, m, rs, rstamp, nf);
776 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
777 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
778 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
779 ieee80211_radiotap_rx_all(ic, m);
780 }
781 /* XXX pass MIC errors up for s/w reclaculation */
782 m_freem(m); m = NULL;
783 goto rx_next;
784 }
785 rx_accept:
786 len = rs->rs_datalen;
787 m->m_len = len;
788
789 if (rs->rs_more) {
790 /*
791 * Frame spans multiple descriptors; save
792 * it for the next completed descriptor, it
793 * will be used to construct a jumbogram.
794 */
795 if (re->m_rxpending != NULL) {
796 /* NB: max frame size is currently 2 clusters */
797 sc->sc_stats.ast_rx_toobig++;
798 m_freem(re->m_rxpending);
799 }
800 m->m_pkthdr.len = len;
801 re->m_rxpending = m;
802 m = NULL;
803 goto rx_next;
804 } else if (re->m_rxpending != NULL) {
805 /*
806 * This is the second part of a jumbogram,
807 * chain it to the first mbuf, adjust the
808 * frame length, and clear the rxpending state.
809 */
810 re->m_rxpending->m_next = m;
811 re->m_rxpending->m_pkthdr.len += len;
812 m = re->m_rxpending;
813 re->m_rxpending = NULL;
814 } else {
815 /*
816 * Normal single-descriptor receive; setup packet length.
817 */
818 m->m_pkthdr.len = len;
819 }
820
821 /*
822 * Validate rs->rs_antenna.
823 *
824 * Some users w/ AR9285 NICs have reported crashes
825 * here because rs_antenna field is bogusly large.
826 * Let's enforce the maximum antenna limit of 8
827 * (and it shouldn't be hard coded, but that's a
828 * separate problem) and if there's an issue, print
829 * out an error and adjust rs_antenna to something
830 * sensible.
831 *
832 * This code should be removed once the actual
833 * root cause of the issue has been identified.
834 * For example, it may be that the rs_antenna
835 * field is only valid for the last frame of
836 * an aggregate and it just happens that it is
837 * "mostly" right. (This is a general statement -
838 * the majority of the statistics are only valid
839 * for the last frame in an aggregate.
840 */
841 if (rs->rs_antenna >= ATH_IOCTL_STATS_NUM_RX_ANTENNA) {
842 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
843 __func__, rs->rs_antenna);
844 #ifdef ATH_DEBUG
845 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
846 #endif /* ATH_DEBUG */
847 rs->rs_antenna = 0; /* XXX better than nothing */
848 }
849
850 /*
851 * If this is an AR9285/AR9485, then the receive and LNA
852 * configuration is stored in RSSI[2] / EXTRSSI[2].
853 * We can extract this out to build a much better
854 * receive antenna profile.
855 *
856 * Yes, this just blurts over the above RX antenna field
857 * for now. It's fine, the AR9285 doesn't really use
858 * that.
859 *
860 * Later on we should store away the fine grained LNA
861 * information and keep separate counters just for
862 * that. It'll help when debugging the AR9285/AR9485
863 * combined diversity code.
864 */
865 if (sc->sc_rx_lnamixer) {
866 rs->rs_antenna = 0;
867
868 /* Bits 0:1 - the LNA configuration used */
869 rs->rs_antenna |=
870 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED)
871 >> HAL_RX_LNA_CFG_USED_S);
872
873 /* Bit 2 - the external RX antenna switch */
874 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG)
875 rs->rs_antenna |= 0x4;
876 }
877
878 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
879
880 /*
881 * Populate the rx status block. When there are bpf
882 * listeners we do the additional work to provide
883 * complete status. Otherwise we fill in only the
884 * material required by ieee80211_input. Note that
885 * noise setting is filled in above.
886 */
887 if (ieee80211_radiotap_active(ic)) {
888 ath_rx_tap(sc, m, rs, rstamp, nf);
889 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
890 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
891 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
892 }
893
894 /*
895 * From this point on we assume the frame is at least
896 * as large as ieee80211_frame_min; verify that.
897 */
898 if (len < IEEE80211_MIN_LEN) {
899 if (!ieee80211_radiotap_active(ic)) {
900 DPRINTF(sc, ATH_DEBUG_RECV,
901 "%s: short packet %d\n", __func__, len);
902 sc->sc_stats.ast_rx_tooshort++;
903 } else {
904 /* NB: in particular this captures ack's */
905 ieee80211_radiotap_rx_all(ic, m);
906 }
907 m_freem(m); m = NULL;
908 goto rx_next;
909 }
910
911 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
912 const HAL_RATE_TABLE *rt = sc->sc_currates;
913 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
914
915 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
916 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
917 }
918
919 m_adj(m, -IEEE80211_CRC_LEN);
920
921 /*
922 * Locate the node for sender, track state, and then
923 * pass the (referenced) node up to the 802.11 layer
924 * for its use.
925 */
926 ni = ieee80211_find_rxnode_withkey(ic,
927 mtod(m, const struct ieee80211_frame_min *),
928 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
929 IEEE80211_KEYIX_NONE : rs->rs_keyix);
930 sc->sc_lastrs = rs;
931
932 if (rs->rs_isaggr)
933 sc->sc_stats.ast_rx_agg++;
934
935 /*
936 * Populate the per-chain RSSI values where appropriate.
937 */
938 bzero(&rxs, sizeof(rxs));
939 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI |
940 IEEE80211_R_C_CHAIN |
941 IEEE80211_R_C_NF |
942 IEEE80211_R_C_RSSI |
943 IEEE80211_R_TSF64 |
944 IEEE80211_R_TSF_START; /* XXX TODO: validate */
945 rxs.c_rssi = rs->rs_rssi;
946 rxs.c_nf = nf;
947 rxs.c_chain = 3; /* XXX TODO: check */
948 rxs.c_rx_tsf = rstamp;
949
950 for (i = 0; i < 3; i++) {
951 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i];
952 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i];
953 /*
954 * XXX note: we currently don't track
955 * per-chain noisefloor.
956 */
957 rxs.c_nf_ctl[i] = nf;
958 rxs.c_nf_ext[i] = nf;
959 }
960
961 if (ni != NULL) {
962 /*
963 * Only punt packets for ampdu reorder processing for
964 * 11n nodes; net80211 enforces that M_AMPDU is only
965 * set for 11n nodes.
966 */
967 if (ni->ni_flags & IEEE80211_NODE_HT)
968 m->m_flags |= M_AMPDU;
969
970 /*
971 * Inform rate control about the received RSSI.
972 * It can then use this information to potentially drastically
973 * alter the available rate based on the RSSI estimate.
974 *
975 * This is super important when associating to a far away station;
976 * you don't want to waste time trying higher rates at some low
977 * packet exchange rate (like during DHCP) just to establish
978 * that higher MCS rates aren't available.
979 */
980 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi,
981 rs->rs_rssi);
982 ath_rate_update_rx_rssi(sc, ATH_NODE(ni),
983 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi));
984
985 /*
986 * Sending station is known, dispatch directly.
987 */
988 (void) ieee80211_add_rx_params(m, &rxs);
989 type = ieee80211_input_mimo(ni, m);
990 ieee80211_free_node(ni);
991 m = NULL;
992 /*
993 * Arrange to update the last rx timestamp only for
994 * frames from our ap when operating in station mode.
995 * This assumes the rx key is always setup when
996 * associated.
997 */
998 if (ic->ic_opmode == IEEE80211_M_STA &&
999 rs->rs_keyix != HAL_RXKEYIX_INVALID)
1000 is_good = 1;
1001 } else {
1002 (void) ieee80211_add_rx_params(m, &rxs);
1003 type = ieee80211_input_mimo_all(ic, m);
1004 m = NULL;
1005 }
1006
1007 /*
1008 * At this point we have passed the frame up the stack; thus
1009 * the mbuf is no longer ours.
1010 */
1011
1012 /*
1013 * Track legacy station RX rssi and do any rx antenna management.
1014 */
1015 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
1016 if (sc->sc_diversity) {
1017 /*
1018 * When using fast diversity, change the default rx
1019 * antenna if diversity chooses the other antenna 3
1020 * times in a row.
1021 */
1022 if (sc->sc_defant != rs->rs_antenna) {
1023 if (++sc->sc_rxotherant >= 3)
1024 ath_setdefantenna(sc, rs->rs_antenna);
1025 } else
1026 sc->sc_rxotherant = 0;
1027 }
1028
1029 /* Handle slow diversity if enabled */
1030 if (sc->sc_dolnadiv) {
1031 ath_lna_rx_comb_scan(sc, rs, ticks, hz);
1032 }
1033
1034 if (sc->sc_softled) {
1035 /*
1036 * Blink for any data frame. Otherwise do a
1037 * heartbeat-style blink when idle. The latter
1038 * is mainly for station mode where we depend on
1039 * periodic beacon frames to trigger the poll event.
1040 */
1041 if (type == IEEE80211_FC0_TYPE_DATA) {
1042 const HAL_RATE_TABLE *rt = sc->sc_currates;
1043 ath_led_event(sc,
1044 rt->rateCodeToIndex[rs->rs_rate]);
1045 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
1046 ath_led_event(sc, 0);
1047 }
1048 rx_next:
1049 /*
1050 * Debugging - complain if we didn't NULL the mbuf pointer
1051 * here.
1052 */
1053 if (m != NULL) {
1054 device_printf(sc->sc_dev,
1055 "%s: mbuf %p should've been freed!\n",
1056 __func__,
1057 m);
1058 }
1059 return (is_good);
1060 }
1061
1062 #define ATH_RX_MAX 128
1063
1064 /*
1065 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like
1066 * the EDMA code does.
1067 *
1068 * XXX TODO: then, do all of the RX list management stuff inside
1069 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA
1070 * code is doing it right.
1071 */
1072 static void
ath_rx_proc(struct ath_softc * sc,int resched)1073 ath_rx_proc(struct ath_softc *sc, int resched)
1074 {
1075 #define PA2DESC(_sc, _pa) \
1076 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1077 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1078 struct ath_buf *bf;
1079 struct ath_hal *ah = sc->sc_ah;
1080 #ifdef IEEE80211_SUPPORT_SUPERG
1081 struct ieee80211com *ic = &sc->sc_ic;
1082 #endif
1083 struct ath_desc *ds;
1084 struct ath_rx_status *rs;
1085 struct mbuf *m;
1086 int ngood;
1087 HAL_STATUS status;
1088 int16_t nf;
1089 u_int64_t tsf;
1090 int npkts = 0;
1091 int kickpcu = 0;
1092 int ret;
1093
1094 NET_EPOCH_ASSERT();
1095
1096 /* XXX we must not hold the ATH_LOCK here */
1097 ATH_UNLOCK_ASSERT(sc);
1098 ATH_PCU_UNLOCK_ASSERT(sc);
1099
1100 ATH_PCU_LOCK(sc);
1101 sc->sc_rxproc_cnt++;
1102 kickpcu = sc->sc_kickpcu;
1103 ATH_PCU_UNLOCK(sc);
1104
1105 ATH_LOCK(sc);
1106 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1107 ATH_UNLOCK(sc);
1108
1109 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
1110 ngood = 0;
1111 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
1112 sc->sc_stats.ast_rx_noise = nf;
1113 tsf = ath_hal_gettsf64(ah);
1114 do {
1115 /*
1116 * Don't process too many packets at a time; give the
1117 * TX thread time to also run - otherwise the TX
1118 * latency can jump by quite a bit, causing throughput
1119 * degredation.
1120 */
1121 if (!kickpcu && npkts >= ATH_RX_MAX)
1122 break;
1123
1124 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1125 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
1126 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__);
1127 break;
1128 } else if (bf == NULL) {
1129 /*
1130 * End of List:
1131 * this can happen for non-self-linked RX chains
1132 */
1133 sc->sc_stats.ast_rx_hitqueueend++;
1134 break;
1135 }
1136 m = bf->bf_m;
1137 if (m == NULL) { /* NB: shouldn't happen */
1138 /*
1139 * If mbuf allocation failed previously there
1140 * will be no mbuf; try again to re-populate it.
1141 */
1142 /* XXX make debug msg */
1143 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__);
1144 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1145 goto rx_proc_next;
1146 }
1147 ds = bf->bf_desc;
1148 if (ds->ds_link == bf->bf_daddr) {
1149 /* NB: never process the self-linked entry at the end */
1150 sc->sc_stats.ast_rx_hitqueueend++;
1151 break;
1152 }
1153 /* XXX sync descriptor memory */
1154 /*
1155 * Must provide the virtual address of the current
1156 * descriptor, the physical address, and the virtual
1157 * address of the next descriptor in the h/w chain.
1158 * This allows the HAL to look ahead to see if the
1159 * hardware is done with a descriptor by checking the
1160 * done bit in the following descriptor and the address
1161 * of the current descriptor the DMA engine is working
1162 * on. All this is necessary because of our use of
1163 * a self-linked list to avoid rx overruns.
1164 */
1165 rs = &bf->bf_status.ds_rxstat;
1166 status = ath_hal_rxprocdesc(ah, ds,
1167 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1168 #ifdef ATH_DEBUG
1169 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
1170 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
1171 #endif
1172
1173 #ifdef ATH_DEBUG_ALQ
1174 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
1175 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
1176 sc->sc_rx_statuslen, (char *) ds);
1177 #endif /* ATH_DEBUG_ALQ */
1178
1179 if (status == HAL_EINPROGRESS)
1180 break;
1181
1182 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1183 npkts++;
1184
1185 /*
1186 * Process a single frame.
1187 */
1188 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
1189 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1190 bf->bf_m = NULL;
1191 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m))
1192 ngood++;
1193 rx_proc_next:
1194 /*
1195 * If there's a holding buffer, insert that onto
1196 * the RX list; the hardware is now definitely not pointing
1197 * to it now.
1198 */
1199 ret = 0;
1200 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) {
1201 TAILQ_INSERT_TAIL(&sc->sc_rxbuf,
1202 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf,
1203 bf_list);
1204 ret = ath_rxbuf_init(sc,
1205 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf);
1206 }
1207 /*
1208 * Next, throw our buffer into the holding entry. The hardware
1209 * may use the descriptor to read the link pointer before
1210 * DMAing the next descriptor in to write out a packet.
1211 */
1212 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf;
1213 } while (ret == 0);
1214
1215 /* rx signal state monitoring */
1216 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
1217 if (ngood)
1218 sc->sc_lastrx = tsf;
1219
1220 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
1221 /* Queue DFS tasklet if needed */
1222 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
1223 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
1224
1225 /*
1226 * Now that all the RX frames were handled that
1227 * need to be handled, kick the PCU if there's
1228 * been an RXEOL condition.
1229 */
1230 if (resched && kickpcu) {
1231 ATH_PCU_LOCK(sc);
1232 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
1233 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
1234 __func__, npkts);
1235
1236 /*
1237 * Go through the process of fully tearing down
1238 * the RX buffers and reinitialising them.
1239 *
1240 * There's a hardware bug that causes the RX FIFO
1241 * to get confused under certain conditions and
1242 * constantly write over the same frame, leading
1243 * the RX driver code here to get heavily confused.
1244 */
1245 /*
1246 * XXX Has RX DMA stopped enough here to just call
1247 * ath_startrecv()?
1248 * XXX Do we need to use the holding buffer to restart
1249 * RX DMA by appending entries to the final
1250 * descriptor? Quite likely.
1251 */
1252 #if 1
1253 ath_startrecv(sc);
1254 #else
1255 /*
1256 * Disabled for now - it'd be nice to be able to do
1257 * this in order to limit the amount of CPU time spent
1258 * reinitialising the RX side (and thus minimise RX
1259 * drops) however there's a hardware issue that
1260 * causes things to get too far out of whack.
1261 */
1262 /*
1263 * XXX can we hold the PCU lock here?
1264 * Are there any net80211 buffer calls involved?
1265 */
1266 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1267 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1268 ath_hal_rxena(ah); /* enable recv descriptors */
1269 ath_mode_init(sc); /* set filters, etc. */
1270 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */
1271 #endif
1272
1273 ath_hal_intrset(ah, sc->sc_imask);
1274 sc->sc_kickpcu = 0;
1275 ATH_PCU_UNLOCK(sc);
1276 }
1277
1278 #ifdef IEEE80211_SUPPORT_SUPERG
1279 if (resched)
1280 ieee80211_ff_age_all(ic, 100);
1281 #endif
1282
1283 /*
1284 * Put the hardware to sleep again if we're done with it.
1285 */
1286 ATH_LOCK(sc);
1287 ath_power_restore_power_state(sc);
1288 ATH_UNLOCK(sc);
1289
1290 /*
1291 * If we hit the maximum number of frames in this round,
1292 * reschedule for another immediate pass. This gives
1293 * the TX and TX completion routines time to run, which
1294 * will reduce latency.
1295 */
1296 if (npkts >= ATH_RX_MAX)
1297 sc->sc_rx.recv_sched(sc, resched);
1298
1299 ATH_PCU_LOCK(sc);
1300 sc->sc_rxproc_cnt--;
1301 ATH_PCU_UNLOCK(sc);
1302 }
1303 #undef PA2DESC
1304 #undef ATH_RX_MAX
1305
1306 /*
1307 * Only run the RX proc if it's not already running.
1308 * Since this may get run as part of the reset/flush path,
1309 * the task can't clash with an existing, running tasklet.
1310 */
1311 static void
ath_legacy_rx_tasklet(void * arg,int npending)1312 ath_legacy_rx_tasklet(void *arg, int npending)
1313 {
1314 struct ath_softc *sc = arg;
1315 struct epoch_tracker et;
1316
1317 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1318 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1319 ATH_PCU_LOCK(sc);
1320 if (sc->sc_inreset_cnt > 0) {
1321 device_printf(sc->sc_dev,
1322 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1323 ATH_PCU_UNLOCK(sc);
1324 return;
1325 }
1326 ATH_PCU_UNLOCK(sc);
1327
1328 NET_EPOCH_ENTER(et);
1329 ath_rx_proc(sc, 1);
1330 NET_EPOCH_EXIT(et);
1331 }
1332
1333 static void
ath_legacy_flushrecv(struct ath_softc * sc)1334 ath_legacy_flushrecv(struct ath_softc *sc)
1335 {
1336 struct epoch_tracker et;
1337 NET_EPOCH_ENTER(et);
1338 ath_rx_proc(sc, 0);
1339 NET_EPOCH_EXIT(et);
1340 }
1341
1342 static void
ath_legacy_flush_rxpending(struct ath_softc * sc)1343 ath_legacy_flush_rxpending(struct ath_softc *sc)
1344 {
1345
1346 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1347
1348 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1349 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1350 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1351 }
1352 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1353 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1354 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1355 }
1356 }
1357
1358 static int
ath_legacy_flush_rxholdbf(struct ath_softc * sc)1359 ath_legacy_flush_rxholdbf(struct ath_softc *sc)
1360 {
1361 struct ath_buf *bf;
1362
1363 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1364 /*
1365 * If there are RX holding buffers, free them here and return
1366 * them to the list.
1367 *
1368 * XXX should just verify that bf->bf_m is NULL, as it must
1369 * be at this point!
1370 */
1371 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf;
1372 if (bf != NULL) {
1373 if (bf->bf_m != NULL)
1374 m_freem(bf->bf_m);
1375 bf->bf_m = NULL;
1376 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1377 (void) ath_rxbuf_init(sc, bf);
1378 }
1379 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL;
1380
1381 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf;
1382 if (bf != NULL) {
1383 if (bf->bf_m != NULL)
1384 m_freem(bf->bf_m);
1385 bf->bf_m = NULL;
1386 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1387 (void) ath_rxbuf_init(sc, bf);
1388 }
1389 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL;
1390
1391 return (0);
1392 }
1393
1394 /*
1395 * Disable the receive h/w in preparation for a reset.
1396 */
1397 static void
ath_legacy_stoprecv(struct ath_softc * sc,int dodelay)1398 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1399 {
1400 #define PA2DESC(_sc, _pa) \
1401 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1402 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1403 struct ath_hal *ah = sc->sc_ah;
1404
1405 ATH_RX_LOCK(sc);
1406
1407 ath_hal_stoppcurecv(ah); /* disable PCU */
1408 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1409 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1410 /*
1411 * TODO: see if this particular DELAY() is required; it may be
1412 * masking some missing FIFO flush or DMA sync.
1413 */
1414 #if 0
1415 if (dodelay)
1416 #endif
1417 DELAY(3000); /* 3ms is long enough for 1 frame */
1418 #ifdef ATH_DEBUG
1419 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1420 struct ath_buf *bf;
1421 u_int ix;
1422
1423 device_printf(sc->sc_dev,
1424 "%s: rx queue %p, link %p\n",
1425 __func__,
1426 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1427 sc->sc_rxlink);
1428 ix = 0;
1429 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1430 struct ath_desc *ds = bf->bf_desc;
1431 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1432 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1433 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1434 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1435 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1436 ix++;
1437 }
1438 }
1439 #endif
1440
1441 (void) ath_legacy_flush_rxpending(sc);
1442 (void) ath_legacy_flush_rxholdbf(sc);
1443
1444 sc->sc_rxlink = NULL; /* just in case */
1445
1446 ATH_RX_UNLOCK(sc);
1447 #undef PA2DESC
1448 }
1449
1450 /*
1451 * XXX TODO: something was calling startrecv without calling
1452 * stoprecv. Let's figure out what/why. It was showing up
1453 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.)
1454 */
1455
1456 /*
1457 * Enable the receive h/w following a reset.
1458 */
1459 static int
ath_legacy_startrecv(struct ath_softc * sc)1460 ath_legacy_startrecv(struct ath_softc *sc)
1461 {
1462 struct ath_hal *ah = sc->sc_ah;
1463 struct ath_buf *bf;
1464
1465 ATH_RX_LOCK(sc);
1466
1467 /*
1468 * XXX should verify these are already all NULL!
1469 */
1470 sc->sc_rxlink = NULL;
1471 (void) ath_legacy_flush_rxpending(sc);
1472 (void) ath_legacy_flush_rxholdbf(sc);
1473
1474 /*
1475 * Re-chain all of the buffers in the RX buffer list.
1476 */
1477 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1478 int error = ath_rxbuf_init(sc, bf);
1479 if (error != 0) {
1480 DPRINTF(sc, ATH_DEBUG_RECV,
1481 "%s: ath_rxbuf_init failed %d\n",
1482 __func__, error);
1483 return error;
1484 }
1485 }
1486
1487 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1488 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1489 ath_hal_rxena(ah); /* enable recv descriptors */
1490 ath_mode_init(sc); /* set filters, etc. */
1491 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */
1492
1493 ATH_RX_UNLOCK(sc);
1494 return 0;
1495 }
1496
1497 static int
ath_legacy_dma_rxsetup(struct ath_softc * sc)1498 ath_legacy_dma_rxsetup(struct ath_softc *sc)
1499 {
1500 int error;
1501
1502 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1503 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1504 if (error != 0)
1505 return (error);
1506
1507 return (0);
1508 }
1509
1510 static int
ath_legacy_dma_rxteardown(struct ath_softc * sc)1511 ath_legacy_dma_rxteardown(struct ath_softc *sc)
1512 {
1513
1514 if (sc->sc_rxdma.dd_desc_len != 0)
1515 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1516 return (0);
1517 }
1518
1519 static void
ath_legacy_recv_sched(struct ath_softc * sc,int dosched)1520 ath_legacy_recv_sched(struct ath_softc *sc, int dosched)
1521 {
1522
1523 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1524 }
1525
1526 static void
ath_legacy_recv_sched_queue(struct ath_softc * sc,HAL_RX_QUEUE q,int dosched)1527 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q,
1528 int dosched)
1529 {
1530
1531 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1532 }
1533
1534 void
ath_recv_setup_legacy(struct ath_softc * sc)1535 ath_recv_setup_legacy(struct ath_softc *sc)
1536 {
1537
1538 /* Sensible legacy defaults */
1539 /*
1540 * XXX this should be changed to properly support the
1541 * exact RX descriptor size for each HAL.
1542 */
1543 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1544
1545 sc->sc_rx.recv_start = ath_legacy_startrecv;
1546 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1547 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1548 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1549 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1550
1551 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1552 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1553 sc->sc_rx.recv_sched = ath_legacy_recv_sched;
1554 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue;
1555 }
1556