1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #ifndef __CNXK_WORKER_H__
6 #define __CNXK_WORKER_H__
7
8 #include "cnxk_eventdev.h"
9
10 /* SSO Operations */
11
12 static __rte_always_inline void
cnxk_sso_hws_add_work(const uint64_t event_ptr,const uint32_t tag,const uint8_t new_tt,const uintptr_t grp_base)13 cnxk_sso_hws_add_work(const uint64_t event_ptr, const uint32_t tag,
14 const uint8_t new_tt, const uintptr_t grp_base)
15 {
16 uint64_t add_work0;
17
18 add_work0 = tag | ((uint64_t)(new_tt) << 32);
19 roc_store_pair(add_work0, event_ptr, grp_base);
20 }
21
22 static __rte_always_inline void
cnxk_sso_hws_swtag_desched(uint32_t tag,uint8_t new_tt,uint16_t grp,uintptr_t swtag_desched_op)23 cnxk_sso_hws_swtag_desched(uint32_t tag, uint8_t new_tt, uint16_t grp,
24 uintptr_t swtag_desched_op)
25 {
26 uint64_t val;
27
28 val = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34);
29 __atomic_store_n((uint64_t *)swtag_desched_op, val, __ATOMIC_RELEASE);
30 }
31
32 static __rte_always_inline void
cnxk_sso_hws_swtag_norm(uint32_t tag,uint8_t new_tt,uintptr_t swtag_norm_op)33 cnxk_sso_hws_swtag_norm(uint32_t tag, uint8_t new_tt, uintptr_t swtag_norm_op)
34 {
35 uint64_t val;
36
37 val = tag | ((uint64_t)(new_tt & 0x3) << 32);
38 plt_write64(val, swtag_norm_op);
39 }
40
41 static __rte_always_inline void
cnxk_sso_hws_swtag_untag(uintptr_t swtag_untag_op)42 cnxk_sso_hws_swtag_untag(uintptr_t swtag_untag_op)
43 {
44 plt_write64(0, swtag_untag_op);
45 }
46
47 static __rte_always_inline void
cnxk_sso_hws_swtag_flush(uint64_t base)48 cnxk_sso_hws_swtag_flush(uint64_t base)
49 {
50 /* Ensure that there is no previous flush is pending. */
51 while (plt_read64(base + SSOW_LF_GWS_PENDSTATE) & BIT_ULL(56))
52 ;
53 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) ==
54 SSO_TT_EMPTY)
55 return;
56 plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
57 }
58
59 static __rte_always_inline uint64_t
cnxk_sso_hws_swtag_wait(uintptr_t tag_op)60 cnxk_sso_hws_swtag_wait(uintptr_t tag_op)
61 {
62 uint64_t swtp;
63 #ifdef RTE_ARCH_ARM64
64
65 asm volatile(PLT_CPU_FEATURE_PREAMBLE
66 " ldr %[swtb], [%[swtp_loc]] \n"
67 " tbz %[swtb], 62, done%= \n"
68 " sevl \n"
69 "rty%=: wfe \n"
70 " ldr %[swtb], [%[swtp_loc]] \n"
71 " tbnz %[swtb], 62, rty%= \n"
72 "done%=: \n"
73 : [swtb] "=&r"(swtp)
74 : [swtp_loc] "r"(tag_op));
75 #else
76 /* Wait for the SWTAG/SWTAG_FULL operation */
77 do {
78 swtp = plt_read64(tag_op);
79 } while (swtp & BIT_ULL(62));
80 #endif
81
82 return swtp;
83 }
84
85 static __rte_always_inline void
cnxk_sso_hws_desched(uint64_t u64,uint64_t base)86 cnxk_sso_hws_desched(uint64_t u64, uint64_t base)
87 {
88 plt_write64(u64, base + SSOW_LF_GWS_OP_UPD_WQP_GRP1);
89 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
90 }
91
92 #endif
93