1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2021 Broadcom All rights reserved. */
3
4 #include <inttypes.h>
5 #include <stdbool.h>
6
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
11 #include <rte_vect.h>
12
13 #include "bnxt.h"
14 #include "bnxt_cpr.h"
15 #include "bnxt_ring.h"
16
17 #include "bnxt_txq.h"
18 #include "bnxt_txr.h"
19 #include "bnxt_rxtx_vec_common.h"
20
21 /*
22 * RX Ring handling
23 */
24
25 #define GET_OL_FLAGS(rss_flags, ol_idx, errors, pi, ol_flags) \
26 { \
27 uint32_t tmp, of; \
28 \
29 of = vgetq_lane_u32((rss_flags), (pi)) | \
30 rxr->ol_flags_table[vgetq_lane_u32((ol_idx), (pi))]; \
31 \
32 tmp = vgetq_lane_u32((errors), (pi)); \
33 if (tmp) \
34 of |= rxr->ol_flags_err_table[tmp]; \
35 (ol_flags) = of; \
36 }
37
38 #define GET_DESC_FIELDS(rxcmp, rxcmp1, shuf_msk, ptype_idx, pkt_idx, ret) \
39 { \
40 uint32_t ptype; \
41 uint16_t vlan_tci; \
42 uint32x4_t r; \
43 \
44 /* Set mbuf pkt_len, data_len, and rss_hash fields. */ \
45 r = vreinterpretq_u32_u8(vqtbl1q_u8(vreinterpretq_u8_u32(rxcmp), \
46 (shuf_msk))); \
47 \
48 /* Set packet type. */ \
49 ptype = bnxt_ptype_table[vgetq_lane_u32((ptype_idx), (pkt_idx))]; \
50 r = vsetq_lane_u32(ptype, r, 0); \
51 \
52 /* Set vlan_tci. */ \
53 vlan_tci = vgetq_lane_u32((rxcmp1), 1); \
54 r = vreinterpretq_u32_u16(vsetq_lane_u16(vlan_tci, \
55 vreinterpretq_u16_u32(r), 5)); \
56 (ret) = r; \
57 }
58
59 static void
descs_to_mbufs(uint32x4_t mm_rxcmp[4],uint32x4_t mm_rxcmp1[4],uint64x2_t mb_init,struct rte_mbuf ** mbuf,struct bnxt_rx_ring_info * rxr)60 descs_to_mbufs(uint32x4_t mm_rxcmp[4], uint32x4_t mm_rxcmp1[4],
61 uint64x2_t mb_init, struct rte_mbuf **mbuf,
62 struct bnxt_rx_ring_info *rxr)
63 {
64 const uint8x16_t shuf_msk = {
65 0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type (zeroes) */
66 2, 3, 0xFF, 0xFF, /* pkt_len */
67 2, 3, /* data_len */
68 0xFF, 0xFF, /* vlan_tci (zeroes) */
69 12, 13, 14, 15 /* rss hash */
70 };
71 const uint32x4_t flags_type_mask =
72 vdupq_n_u32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
73 const uint32x4_t flags2_mask1 =
74 vdupq_n_u32(CMPL_FLAGS2_VLAN_TUN_MSK);
75 const uint32x4_t flags2_mask2 =
76 vdupq_n_u32(RX_PKT_CMPL_FLAGS2_IP_TYPE);
77 const uint32x4_t rss_mask =
78 vdupq_n_u32(RX_PKT_CMPL_FLAGS_RSS_VALID);
79 const uint32x4_t flags2_index_mask = vdupq_n_u32(0x1F);
80 const uint32x4_t flags2_error_mask = vdupq_n_u32(0x0F);
81 uint32x4_t flags_type, flags2, index, errors, rss_flags;
82 uint32x4_t tmp, ptype_idx, is_tunnel;
83 uint64x2_t t0, t1;
84 uint32_t ol_flags;
85
86 /* Validate ptype table indexing at build time. */
87 bnxt_check_ptype_constants();
88
89 /* Compute packet type table indexes for four packets */
90 t0 = vreinterpretq_u64_u32(vzip1q_u32(mm_rxcmp[0], mm_rxcmp[1]));
91 t1 = vreinterpretq_u64_u32(vzip1q_u32(mm_rxcmp[2], mm_rxcmp[3]));
92
93 flags_type = vreinterpretq_u32_u64(vcombine_u64(vget_low_u64(t0),
94 vget_low_u64(t1)));
95 ptype_idx = vshrq_n_u32(vandq_u32(flags_type, flags_type_mask),
96 RX_PKT_CMPL_FLAGS_ITYPE_SFT -
97 BNXT_PTYPE_TBL_TYPE_SFT);
98
99 t0 = vreinterpretq_u64_u32(vzip1q_u32(mm_rxcmp1[0], mm_rxcmp1[1]));
100 t1 = vreinterpretq_u64_u32(vzip1q_u32(mm_rxcmp1[2], mm_rxcmp1[3]));
101
102 flags2 = vreinterpretq_u32_u64(vcombine_u64(vget_low_u64(t0),
103 vget_low_u64(t1)));
104
105 ptype_idx = vorrq_u32(ptype_idx,
106 vshrq_n_u32(vandq_u32(flags2, flags2_mask1),
107 RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT -
108 BNXT_PTYPE_TBL_VLAN_SFT));
109 ptype_idx = vorrq_u32(ptype_idx,
110 vshrq_n_u32(vandq_u32(flags2, flags2_mask2),
111 RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT -
112 BNXT_PTYPE_TBL_IP_VER_SFT));
113
114 /* Extract RSS valid flags for four packets. */
115 rss_flags = vshrq_n_u32(vandq_u32(flags_type, rss_mask), 9);
116
117 flags2 = vandq_u32(flags2, flags2_index_mask);
118
119 /* Extract errors_v2 fields for four packets. */
120 t0 = vreinterpretq_u64_u32(vzip2q_u32(mm_rxcmp1[0], mm_rxcmp1[1]));
121 t1 = vreinterpretq_u64_u32(vzip2q_u32(mm_rxcmp1[2], mm_rxcmp1[3]));
122
123 errors = vreinterpretq_u32_u64(vcombine_u64(vget_low_u64(t0),
124 vget_low_u64(t1)));
125
126 /* Compute ol_flags and checksum error indexes for four packets. */
127 is_tunnel = vandq_u32(flags2, vdupq_n_u32(4));
128 is_tunnel = vshlq_n_u32(is_tunnel, 3);
129 errors = vandq_u32(vshrq_n_u32(errors, 4), flags2_error_mask);
130 errors = vandq_u32(errors, flags2);
131
132 index = vbicq_u32(flags2, errors);
133 errors = vorrq_u32(errors, vshrq_n_u32(is_tunnel, 1));
134 index = vorrq_u32(index, is_tunnel);
135
136 /* Update mbuf rearm_data for four packets. */
137 GET_OL_FLAGS(rss_flags, index, errors, 0, ol_flags);
138 vst1q_u32((uint32_t *)&mbuf[0]->rearm_data,
139 vsetq_lane_u32(ol_flags, vreinterpretq_u32_u64(mb_init), 2));
140 GET_OL_FLAGS(rss_flags, index, errors, 1, ol_flags);
141 vst1q_u32((uint32_t *)&mbuf[1]->rearm_data,
142 vsetq_lane_u32(ol_flags, vreinterpretq_u32_u64(mb_init), 2));
143 GET_OL_FLAGS(rss_flags, index, errors, 2, ol_flags);
144 vst1q_u32((uint32_t *)&mbuf[2]->rearm_data,
145 vsetq_lane_u32(ol_flags, vreinterpretq_u32_u64(mb_init), 2));
146 GET_OL_FLAGS(rss_flags, index, errors, 3, ol_flags);
147 vst1q_u32((uint32_t *)&mbuf[3]->rearm_data,
148 vsetq_lane_u32(ol_flags, vreinterpretq_u32_u64(mb_init), 2));
149
150 /* Update mbuf rx_descriptor_fields1 for four packets. */
151 GET_DESC_FIELDS(mm_rxcmp[0], mm_rxcmp1[0], shuf_msk, ptype_idx, 0, tmp);
152 vst1q_u32((uint32_t *)&mbuf[0]->rx_descriptor_fields1, tmp);
153 GET_DESC_FIELDS(mm_rxcmp[1], mm_rxcmp1[1], shuf_msk, ptype_idx, 1, tmp);
154 vst1q_u32((uint32_t *)&mbuf[1]->rx_descriptor_fields1, tmp);
155 GET_DESC_FIELDS(mm_rxcmp[2], mm_rxcmp1[2], shuf_msk, ptype_idx, 2, tmp);
156 vst1q_u32((uint32_t *)&mbuf[2]->rx_descriptor_fields1, tmp);
157 GET_DESC_FIELDS(mm_rxcmp[3], mm_rxcmp1[3], shuf_msk, ptype_idx, 3, tmp);
158 vst1q_u32((uint32_t *)&mbuf[3]->rx_descriptor_fields1, tmp);
159 }
160
161 static uint16_t
recv_burst_vec_neon(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)162 recv_burst_vec_neon(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
163 {
164 struct bnxt_rx_queue *rxq = rx_queue;
165 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
166 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
167 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size;
168 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size;
169 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
170 uint64_t valid, desc_valid_mask = ~0UL;
171 const uint32x4_t info3_v_mask = vdupq_n_u32(CMPL_BASE_V);
172 uint32_t raw_cons = cpr->cp_raw_cons;
173 uint32_t cons, mbcons;
174 int nb_rx_pkts = 0;
175 const uint64x2_t mb_init = {rxq->mbuf_initializer, 0};
176 const uint32x4_t valid_target =
177 vdupq_n_u32(!!(raw_cons & cp_ring_size));
178 int i;
179
180 /* If Rx Q was stopped return */
181 if (unlikely(!rxq->rx_started))
182 return 0;
183
184 if (rxq->rxrearm_nb >= rxq->rx_free_thresh)
185 bnxt_rxq_rearm(rxq, rxr);
186
187 cons = raw_cons & (cp_ring_size - 1);
188 mbcons = (raw_cons / 2) & (rx_ring_size - 1);
189
190 /* Prefetch first four descriptor pairs. */
191 rte_prefetch0(&cp_desc_ring[cons]);
192 rte_prefetch0(&cp_desc_ring[cons + 4]);
193
194 /* Ensure that we do not go past the ends of the rings. */
195 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,
196 (cp_ring_size - cons) / 2));
197 /*
198 * If we are at the end of the ring, ensure that descriptors after the
199 * last valid entry are not treated as valid. Otherwise, force the
200 * maximum number of packets to receive to be a multiple of the per-
201 * loop count.
202 */
203 if (nb_pkts < BNXT_RX_DESCS_PER_LOOP_VEC128) {
204 desc_valid_mask >>=
205 16 * (BNXT_RX_DESCS_PER_LOOP_VEC128 - nb_pkts);
206 } else {
207 nb_pkts =
208 RTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC128);
209 }
210
211 /* Handle RX burst request */
212 for (i = 0; i < nb_pkts; i += BNXT_RX_DESCS_PER_LOOP_VEC128,
213 cons += BNXT_RX_DESCS_PER_LOOP_VEC128 * 2,
214 mbcons += BNXT_RX_DESCS_PER_LOOP_VEC128) {
215 uint32x4_t rxcmp1[BNXT_RX_DESCS_PER_LOOP_VEC128];
216 uint32x4_t rxcmp[BNXT_RX_DESCS_PER_LOOP_VEC128];
217 uint32x4_t info3_v;
218 uint64x2_t t0, t1;
219 uint32_t num_valid;
220
221 /* Copy four mbuf pointers to output array. */
222 t0 = vld1q_u64((void *)&rxr->rx_buf_ring[mbcons]);
223 t1 = vld1q_u64((void *)&rxr->rx_buf_ring[mbcons + 2]);
224 vst1q_u64((void *)&rx_pkts[i], t0);
225 vst1q_u64((void *)&rx_pkts[i + 2], t1);
226
227 /* Prefetch four descriptor pairs for next iteration. */
228 if (i + BNXT_RX_DESCS_PER_LOOP_VEC128 < nb_pkts) {
229 rte_prefetch0(&cp_desc_ring[cons + 8]);
230 rte_prefetch0(&cp_desc_ring[cons + 12]);
231 }
232
233 /*
234 * Load the four current descriptors into NEON registers.
235 * IO barriers are used to ensure consistent state.
236 */
237 rxcmp1[3] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 7]);
238 rte_io_rmb();
239 /* Reload lower 64b of descriptors to make it ordered after info3_v. */
240 rxcmp1[3] = vreinterpretq_u32_u64(vld1q_lane_u64
241 ((void *)&cpr->cp_desc_ring[cons + 7],
242 vreinterpretq_u64_u32(rxcmp1[3]), 0));
243 rxcmp[3] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 6]);
244
245 rxcmp1[2] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 5]);
246 rte_io_rmb();
247 rxcmp1[2] = vreinterpretq_u32_u64(vld1q_lane_u64
248 ((void *)&cpr->cp_desc_ring[cons + 5],
249 vreinterpretq_u64_u32(rxcmp1[2]), 0));
250 rxcmp[2] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 4]);
251
252 t1 = vreinterpretq_u64_u32(vzip2q_u32(rxcmp1[2], rxcmp1[3]));
253
254 rxcmp1[1] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 3]);
255 rte_io_rmb();
256 rxcmp1[1] = vreinterpretq_u32_u64(vld1q_lane_u64
257 ((void *)&cpr->cp_desc_ring[cons + 3],
258 vreinterpretq_u64_u32(rxcmp1[1]), 0));
259 rxcmp[1] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 2]);
260
261 rxcmp1[0] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 1]);
262 rte_io_rmb();
263 rxcmp1[0] = vreinterpretq_u32_u64(vld1q_lane_u64
264 ((void *)&cpr->cp_desc_ring[cons + 1],
265 vreinterpretq_u64_u32(rxcmp1[0]), 0));
266 rxcmp[0] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 0]);
267
268 t0 = vreinterpretq_u64_u32(vzip2q_u32(rxcmp1[0], rxcmp1[1]));
269
270 /* Isolate descriptor status flags. */
271 info3_v = vreinterpretq_u32_u64(vcombine_u64(vget_low_u64(t0),
272 vget_low_u64(t1)));
273 info3_v = vandq_u32(info3_v, info3_v_mask);
274 info3_v = veorq_u32(info3_v, valid_target);
275
276 /*
277 * Pack the 128-bit array of valid descriptor flags into 64
278 * bits and count the number of set bits in order to determine
279 * the number of valid descriptors.
280 */
281 valid = vget_lane_u64(vreinterpret_u64_u16(vqmovn_u32(info3_v)),
282 0);
283 /*
284 * At this point, 'valid' is a 64-bit value containing four
285 * 16-bit fields, each of which is either 0x0001 or 0x0000.
286 * Compute number of valid descriptors from the index of
287 * the highest non-zero field.
288 */
289 num_valid = (sizeof(uint64_t) / sizeof(uint16_t)) -
290 (__builtin_clzl(valid & desc_valid_mask) / 16);
291
292 if (num_valid == 0)
293 break;
294
295 descs_to_mbufs(rxcmp, rxcmp1, mb_init, &rx_pkts[nb_rx_pkts],
296 rxr);
297 nb_rx_pkts += num_valid;
298
299 if (num_valid < BNXT_RX_DESCS_PER_LOOP_VEC128)
300 break;
301 }
302
303 if (nb_rx_pkts) {
304 rxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts);
305
306 rxq->rxrearm_nb += nb_rx_pkts;
307 cpr->cp_raw_cons += 2 * nb_rx_pkts;
308 bnxt_db_cq(cpr);
309 }
310
311 return nb_rx_pkts;
312 }
313
314 uint16_t
bnxt_recv_pkts_vec(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)315 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
316 {
317 uint16_t cnt = 0;
318
319 while (nb_pkts > RTE_BNXT_MAX_RX_BURST) {
320 uint16_t burst;
321
322 burst = recv_burst_vec_neon(rx_queue, rx_pkts + cnt,
323 RTE_BNXT_MAX_RX_BURST);
324
325 cnt += burst;
326 nb_pkts -= burst;
327
328 if (burst < RTE_BNXT_MAX_RX_BURST)
329 return cnt;
330 }
331
332 return cnt + recv_burst_vec_neon(rx_queue, rx_pkts + cnt, nb_pkts);
333 }
334
335 static void
bnxt_handle_tx_cp_vec(struct bnxt_tx_queue * txq)336 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
337 {
338 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
339 uint32_t raw_cons = cpr->cp_raw_cons;
340 uint32_t cons;
341 uint32_t nb_tx_pkts = 0;
342 struct tx_cmpl *txcmp;
343 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
344 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
345 uint32_t ring_mask = cp_ring_struct->ring_mask;
346
347 do {
348 cons = RING_CMPL(ring_mask, raw_cons);
349 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
350
351 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
352 break;
353
354 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
355 nb_tx_pkts += txcmp->opaque;
356 else
357 RTE_LOG_DP(ERR, PMD,
358 "Unhandled CMP type %02x\n",
359 CMP_TYPE(txcmp));
360 raw_cons = NEXT_RAW_CMP(raw_cons);
361 } while (nb_tx_pkts < ring_mask);
362
363 if (nb_tx_pkts) {
364 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
365 bnxt_tx_cmp_vec_fast(txq, nb_tx_pkts);
366 else
367 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
368 cpr->cp_raw_cons = raw_cons;
369 bnxt_db_cq(cpr);
370 }
371 }
372
373 static uint16_t
bnxt_xmit_fixed_burst_vec(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)374 bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
375 uint16_t nb_pkts)
376 {
377 struct bnxt_tx_queue *txq = tx_queue;
378 struct bnxt_tx_ring_info *txr = txq->tx_ring;
379 uint16_t tx_prod, tx_raw_prod = txr->tx_raw_prod;
380 struct rte_mbuf *tx_mbuf;
381 struct tx_bd_long *txbd = NULL;
382 struct rte_mbuf **tx_buf;
383 uint16_t to_send;
384
385 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
386
387 if (unlikely(nb_pkts == 0))
388 return 0;
389
390 /* Handle TX burst request */
391 to_send = nb_pkts;
392 while (to_send) {
393 tx_mbuf = *tx_pkts++;
394 rte_prefetch0(tx_mbuf);
395
396 tx_prod = RING_IDX(txr->tx_ring_struct, tx_raw_prod);
397 tx_buf = &txr->tx_buf_ring[tx_prod];
398 *tx_buf = tx_mbuf;
399
400 txbd = &txr->tx_desc_ring[tx_prod];
401 txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
402 txbd->len = tx_mbuf->data_len;
403 txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
404 TX_BD_FLAGS_NOCMPL);
405 tx_raw_prod = RING_NEXT(tx_raw_prod);
406 to_send--;
407 }
408
409 /* Request a completion for last packet in burst */
410 if (txbd) {
411 txbd->opaque = nb_pkts;
412 txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
413 }
414
415 rte_compiler_barrier();
416 bnxt_db_write(&txr->tx_db, tx_raw_prod);
417
418 txr->tx_raw_prod = tx_raw_prod;
419
420 return nb_pkts;
421 }
422
423 uint16_t
bnxt_xmit_pkts_vec(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)424 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
425 uint16_t nb_pkts)
426 {
427 int nb_sent = 0;
428 struct bnxt_tx_queue *txq = tx_queue;
429
430 /* Tx queue was stopped; wait for it to be restarted */
431 if (unlikely(!txq->tx_started)) {
432 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
433 return 0;
434 }
435
436 /* Handle TX completions */
437 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
438 bnxt_handle_tx_cp_vec(txq);
439
440 while (nb_pkts) {
441 uint16_t ret, num;
442
443 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
444 ret = bnxt_xmit_fixed_burst_vec(tx_queue,
445 &tx_pkts[nb_sent],
446 num);
447 nb_sent += ret;
448 nb_pkts -= ret;
449 if (ret < num)
450 break;
451 }
452
453 return nb_sent;
454 }
455
456 int __rte_cold
bnxt_rxq_vec_setup(struct bnxt_rx_queue * rxq)457 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
458 {
459 return bnxt_rxq_vec_setup_common(rxq);
460 }
461