1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11
3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11
4
5declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a, <2 x i16> %b, float %c, i1 %clamp)
6
7define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_clamp(
8; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
9; GFX11:       ; %bb.0: ; %entry
10; GFX11-NEXT:    s_load_b256 s[0:7], s[0:1], 0x24
11; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
12; GFX11-NEXT:    s_load_b32 s6, s[6:7], 0x0
13; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
14; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
15; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
16; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
17; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
18; GFX11-NEXT:    v_dot2_f32_bf16 v0, s2, s3, v0 clamp
19; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
20; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
21; GFX11-NEXT:    s_endpgm
22    float addrspace(1)* %r,
23    <2 x i16> addrspace(1)* %a,
24    <2 x i16> addrspace(1)* %b,
25    float addrspace(1)* %c) {
26entry:
27  %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
28  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
29  %c.val = load float, float addrspace(1)* %c
30  %r.val = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a.val, <2 x i16> %b.val, float %c.val, i1 1)
31  store float %r.val, float addrspace(1)* %r
32  ret void
33}
34
35
36define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_no_clamp(
37; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_no_clamp:
38; GFX11:       ; %bb.0: ; %entry
39; GFX11-NEXT:    s_load_b256 s[0:7], s[0:1], 0x24
40; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
41; GFX11-NEXT:    s_load_b32 s6, s[6:7], 0x0
42; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
43; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
44; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
45; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
46; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
47; GFX11-NEXT:    v_dot2_f32_bf16 v0, s2, s3, v0
48; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
49; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
50; GFX11-NEXT:    s_endpgm
51    float addrspace(1)* %r,
52    <2 x i16> addrspace(1)* %a,
53    <2 x i16> addrspace(1)* %b,
54    float addrspace(1)* %c) {
55entry:
56  %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
57  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
58  %c.val = load float, float addrspace(1)* %c
59  %r.val = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a.val, <2 x i16> %b.val, float %c.val, i1 0)
60  store float %r.val, float addrspace(1)* %r
61  ret void
62}
63