1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #ifndef _IXGBE_OS_H_
6 #define _IXGBE_OS_H_
7
8 #include <string.h>
9 #include <stdint.h>
10 #include <stdio.h>
11 #include <stdarg.h>
12 #include <stdbool.h>
13 #include <rte_common.h>
14 #include <rte_debug.h>
15 #include <rte_cycles.h>
16 #include <rte_log.h>
17 #include <rte_byteorder.h>
18 #include <rte_io.h>
19 #include <rte_ip.h>
20
21 #include "../ixgbe_logs.h"
22 #include "../ixgbe_bypass_defines.h"
23
24 #ifndef IPPROTO_SCTP
25 #define IPPROTO_SCTP 132
26 #endif
27
28 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
29
30 #define DELAY(x) rte_delay_us_sleep(x)
31 #define usec_delay(x) DELAY(x)
32 #define msec_delay(x) DELAY(1000*(x))
33
34 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
35 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
36 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
37 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
38 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
39 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
40 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
41
42 #define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args)
43 #define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args)
44 #define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args)
45
46 #define FALSE 0
47 #define TRUE 1
48
49 #define false 0
50 #define true 1
51 #ifndef RTE_EXEC_ENV_WINDOWS
52 #define min(a,b) RTE_MIN(a,b)
53 #endif
54
55 #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)
56
57 /* Bunch of defines for shared code bogosity */
58 #ifndef UNREFERENCED_PARAMETER
59 #define UNREFERENCED_PARAMETER(_p)
60 #endif
61 #define UNREFERENCED_1PARAMETER(_p)
62 #define UNREFERENCED_2PARAMETER(_p, _q)
63 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
64 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
65 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
66
67 /* Shared code error reporting */
68 enum {
69 IXGBE_ERROR_SOFTWARE,
70 IXGBE_ERROR_POLLING,
71 IXGBE_ERROR_INVALID_STATE,
72 IXGBE_ERROR_UNSUPPORTED,
73 IXGBE_ERROR_ARGUMENT,
74 IXGBE_ERROR_CAUTION,
75 };
76
77 #define STATIC static
78 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
79 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
80 #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i)
81 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
82 #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)
83 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
84 #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
85 #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
86 #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i)
87
88 typedef uint8_t u8;
89 typedef int8_t s8;
90 typedef uint16_t u16;
91 typedef int16_t s16;
92 typedef uint32_t u32;
93 typedef int32_t s32;
94 typedef uint64_t u64;
95
96 #define mb() rte_mb()
97 #define wmb() rte_wmb()
98 #define rmb() rte_rmb()
99
100 #define IOMEM
101
102 #define prefetch(x) rte_prefetch0(x)
103
104 #define IXGBE_PCI_REG(reg) rte_read32(reg)
105
ixgbe_read_addr(volatile void * addr)106 static inline uint32_t ixgbe_read_addr(volatile void* addr)
107 {
108 return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
109 }
110
111 #define IXGBE_PCI_REG_WRITE(reg, value) \
112 rte_write32((rte_cpu_to_le_32(value)), reg)
113
114 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
115 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
116
117 #define IXGBE_PCI_REG_WC_WRITE(reg, value) \
118 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
119
120 #define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \
121 rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
122
123 #define IXGBE_PCI_REG_ADDR(hw, reg) \
124 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
125
126 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
127 IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
128
129 /* Not implemented !! */
130 #define IXGBE_READ_PCIE_WORD(hw, reg) 0
131 #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
132
133 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
134
135 #define IXGBE_READ_REG(hw, reg) \
136 ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
137
138 #define IXGBE_WRITE_REG(hw, reg, value) \
139 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
140
141 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \
142 IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
143
144 #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
145 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
146
147 #define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \
148 do { \
149 uint32_t cnt = poll_ms; \
150 IXGBE_WRITE_REG(hw, (reg), (val)); \
151 while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \
152 rte_delay_ms(1); \
153 } while (0)
154
155 #endif /* _IXGBE_OS_H_ */
156