1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IXGBE_DCB_H_ 6 #define _IXGBE_DCB_H_ 7 8 #include "ixgbe_type.h" 9 10 /* DCB defines */ 11 /* DCB credit calculation defines */ 12 #define IXGBE_DCB_CREDIT_QUANTUM 64 13 #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */ 14 #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ 15 #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL) 16 17 /* 513 for 32KB TSO packet */ 18 #define IXGBE_DCB_MIN_TSO_CREDIT \ 19 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) 20 21 /* DCB configuration defines */ 22 #define IXGBE_DCB_MAX_USER_PRIORITY 8 23 #define IXGBE_DCB_MAX_BW_GROUP 8 24 #define IXGBE_DCB_BW_PERCENT 100 25 26 #define IXGBE_DCB_TX_CONFIG 0 27 #define IXGBE_DCB_RX_CONFIG 1 28 29 /* DCB capability defines */ 30 #define IXGBE_DCB_PG_SUPPORT 0x00000001 31 #define IXGBE_DCB_PFC_SUPPORT 0x00000002 32 #define IXGBE_DCB_BCN_SUPPORT 0x00000004 33 #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 34 #define IXGBE_DCB_GSP_SUPPORT 0x00000010 35 36 struct ixgbe_dcb_support { 37 u32 capabilities; /* DCB capabilities */ 38 39 /* Each bit represents a number of TCs configurable in the hw. 40 * If 8 traffic classes can be configured, the value is 0x80. */ 41 u8 traffic_classes; 42 u8 pfc_traffic_classes; 43 }; 44 45 enum ixgbe_dcb_tsa { 46 ixgbe_dcb_tsa_ets = 0, 47 ixgbe_dcb_tsa_group_strict_cee, 48 ixgbe_dcb_tsa_strict 49 }; 50 51 /* Traffic class bandwidth allocation per direction */ 52 struct ixgbe_dcb_tc_path { 53 u8 bwg_id; /* Bandwidth Group (BWG) ID */ 54 u8 bwg_percent; /* % of BWG's bandwidth */ 55 u8 link_percent; /* % of link bandwidth */ 56 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 57 u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 58 u16 data_credits_max; /* Max credits for a configured packet buffer 59 * in 64B granularity.*/ 60 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ 61 }; 62 63 enum ixgbe_dcb_pfc { 64 ixgbe_dcb_pfc_disabled = 0, 65 ixgbe_dcb_pfc_enabled, 66 ixgbe_dcb_pfc_enabled_txonly, 67 ixgbe_dcb_pfc_enabled_rxonly 68 }; 69 70 /* Traffic class configuration */ 71 struct ixgbe_dcb_tc_config { 72 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ 73 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ 74 75 u16 desc_credits_max; /* For Tx Descriptor arbitration */ 76 u8 tc; /* Traffic class (TC) */ 77 }; 78 79 enum ixgbe_dcb_pba { 80 /* PBA[0-7] each use 64KB FIFO */ 81 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, 82 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 83 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED 84 }; 85 86 struct ixgbe_dcb_num_tcs { 87 u8 pg_tcs; 88 u8 pfc_tcs; 89 }; 90 91 struct ixgbe_dcb_config { 92 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 93 struct ixgbe_dcb_support support; 94 struct ixgbe_dcb_num_tcs num_tcs; 95 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ 96 bool pfc_mode_enable; 97 bool round_robin_enable; 98 99 enum ixgbe_dcb_pba rx_pba_cfg; 100 101 u32 dcb_cfg_version; /* Not used...OS-specific? */ 102 u32 link_speed; /* For bandwidth allocation validation purpose */ 103 bool vt_mode; 104 }; 105 106 /* DCB driver APIs */ 107 108 /* DCB rule checking */ 109 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); 110 111 /* DCB credits calculation */ 112 s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); 113 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, 114 struct ixgbe_dcb_config *, u32, u8); 115 116 /* DCB PFC */ 117 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); 118 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 119 120 /* DCB stats */ 121 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); 122 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 123 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 124 125 /* DCB config arbiters */ 126 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, 127 struct ixgbe_dcb_config *); 128 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, 129 struct ixgbe_dcb_config *); 130 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, 131 struct ixgbe_dcb_config *); 132 133 /* DCB unpack routines */ 134 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); 135 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); 136 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); 137 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); 138 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); 139 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); 140 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 141 142 /* DCB initialization */ 143 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); 144 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 145 #endif /* _IXGBE_DCB_H_ */ 146