1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2017 Kyle Evans <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <machine/bus.h>
40
41 #include <dev/fdt/simplebus.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <dev/extres/clk/clk_div.h>
47 #include <dev/extres/clk/clk_fixed.h>
48 #include <dev/extres/clk/clk_mux.h>
49
50 #include <arm/allwinner/clkng/aw_ccung.h>
51
52 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
53 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
54
55 /* Non-exported clocks */
56
57 #define CLK_PLL_C0CPUX 0
58 #define CLK_PLL_C1CPUX 1
59 #define CLK_PLL_AUDIO 2
60 #define CLK_PLL_VIDEO0 3
61 #define CLK_PLL_VE 4
62 #define CLK_PLL_DDR 5
63
64 #define CLK_PLL_GPU 7
65 #define CLK_PLL_HSIC 8
66 #define CLK_PLL_VIDEO1 10
67
68 #define CLK_AXI0 13
69 #define CLK_AXI1 14
70 #define CLK_AHB1 15
71 #define CLK_APB1 16
72 #define CLK_APB2 17
73 #define CLK_AHB2 18
74
75 #define CLK_CCI400 58
76
77 #define CLK_DRAM 82
78
79 #define CLK_MBUS 95
80
81 /* Non-exported fixed clocks */
82 #define CLK_OSC_12M 150
83
84 static struct aw_ccung_reset a83t_ccu_resets[] = {
85 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
86 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
87 CCU_RESET(RST_USB_HSIC, 0xcc, 2)
88
89 CCU_RESET(RST_DRAM, 0xf4, 31)
90 CCU_RESET(RST_MBUS, 0xfc, 31)
91
92 CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
93 CCU_RESET(RST_BUS_SS, 0x2c0, 5)
94 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
95 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
96 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
97 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
98 CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
99 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
100 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
101 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
102 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
103 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
104 CCU_RESET(RST_BUS_OTG, 0x2c0, 24)
105 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26)
106 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27)
107 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29)
108
109 CCU_RESET(RST_BUS_VE, 0x2c4, 0)
110 CCU_RESET(RST_BUS_TCON0, 0x2c4, 4)
111 CCU_RESET(RST_BUS_TCON1, 0x2c4, 5)
112 CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
113 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
114 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
115 CCU_RESET(RST_BUS_DE, 0x2c4, 12)
116 CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
117 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
118 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
119
120 CCU_RESET(RST_BUS_LVDS, 0x2c8, 0)
121
122 CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
123 CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
124 CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
125 CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
126 CCU_RESET(RST_BUS_TDM, 0x2d0, 15)
127
128 CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
129 CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
130 CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
131 CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
132 CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
133 CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
134 CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
135 CCU_RESET(RST_BUS_UART4, 0x2d8, 20)
136 };
137
138 static struct aw_ccung_gate a83t_ccu_gates[] = {
139 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
140 CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5)
141 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
142 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
143 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
144 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
145 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
146 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
147 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17)
148 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
149 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
150 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
151 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24)
152 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26)
153 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27)
154 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29)
155
156 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
157 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4)
158 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5)
159 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
160 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
161 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
162 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
163 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
164 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
165
166 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
167 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
168 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
169 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
170 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
171 CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15)
172
173 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
174 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
175 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
176 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
177 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
178 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
179 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
180 CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20)
181
182 CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
183 CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
184 CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
185 CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
186 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
187
188 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
189 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
190
191 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16)
192 CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31)
193
194 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
195
196 CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31)
197 };
198
199 static const char *osc12m_parents[] = {"osc24M"};
200 FIXED_CLK(osc12m_clk,
201 CLK_OSC_12M, /* id */
202 "osc12M", osc12m_parents, /* name, parents */
203 0, /* freq */
204 1, /* mult */
205 2, /* div */
206 0); /* flags */
207
208 /* CPU PLL are 24Mhz * N / P */
209 static const char *pll_c0cpux_parents[] = {"osc24M"};
210 static const char *pll_c1cpux_parents[] = {"osc24M"};
211 NKMP_CLK(pll_c0cpux_clk,
212 CLK_PLL_C0CPUX, /* id */
213 "pll_c0cpux", pll_c0cpux_parents, /* name, parents */
214 0x00, /* offset */
215 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
216 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
217 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */
218 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
219 0, 0, /* lock */
220 31, /* gate */
221 AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */
222 NKMP_CLK(pll_c1cpux_clk,
223 CLK_PLL_C1CPUX, /* id */
224 "pll_c1cpux", pll_c1cpux_parents, /* name, parents */
225 0x04, /* offset */
226 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
227 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
228 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */
229 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
230 0, 0, /* lock */
231 31, /* gate */
232 AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */
233
234 static const char *pll_audio_parents[] = {"osc24M"};
235 NKMP_CLK(pll_audio_clk,
236 CLK_PLL_AUDIO, /* id */
237 "pll_audio", pll_audio_parents, /* name, parents */
238 0x08, /* offset */
239 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
240 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
241 16, 1, 0, 0, /* m factor */
242 18, 1, 0, 0, /* p factor */
243 31, /* gate */
244 0, 0, /* lock */
245 AW_CLK_HAS_GATE); /* flags */
246
247 static const char *pll_video0_parents[] = {"osc24M"};
248 NKMP_CLK(pll_video0_clk,
249 CLK_PLL_VIDEO0, /* id */
250 "pll_video0", pll_video0_parents, /* name, parents */
251 0x10, /* offset */
252 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
253 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
254 16, 1, 0, 0, /* m factor */
255 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */
256 31, /* gate */
257 0, 0, /* lock */
258 AW_CLK_HAS_GATE); /* flags */
259
260 static const char *pll_ve_parents[] = {"osc24M"};
261 NKMP_CLK(pll_ve_clk,
262 CLK_PLL_VE, /* id */
263 "pll_ve", pll_ve_parents, /* name, parents */
264 0x18, /* offset */
265 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
266 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
267 16, 1, 0, 0, /* m factor */
268 18, 1, 0, 0, /* p factor */
269 31, /* gate */
270 0, 0, /* lock */
271 AW_CLK_HAS_GATE); /* flags */
272
273 static const char *pll_ddr_parents[] = {"osc24M"};
274 NKMP_CLK(pll_ddr_clk,
275 CLK_PLL_DDR, /* id */
276 "pll_ddr", pll_ddr_parents, /* name, parents */
277 0x20, /* offset */
278 8, 5, 0, 0, /* n factor */
279 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
280 16, 1, 0, 0, /* m factor */
281 18, 1, 0, 0, /* p factor */
282 31, /* gate */
283 0, 0, /* lock */
284 AW_CLK_HAS_GATE); /* flags */
285
286 static const char *pll_periph_parents[] = {"osc24M"};
287 NKMP_CLK(pll_periph_clk,
288 CLK_PLL_PERIPH, /* id */
289 "pll_periph", pll_periph_parents, /* name, parents */
290 0x28, /* offset */
291 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
292 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
293 16, 1, 1, 0, /* m factor */
294 18, 1, 1, 0, /* p factor */
295 31, /* gate */
296 0, 0, /* lock */
297 AW_CLK_HAS_GATE); /* flags */
298
299 static const char *pll_gpu_parents[] = {"osc24M"};
300 NKMP_CLK(pll_gpu_clk,
301 CLK_PLL_GPU, /* id */
302 "pll_gpu", pll_gpu_parents, /* name, parents */
303 0x38, /* offset */
304 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
305 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
306 16, 1, 1, 0, /* m factor */
307 18, 1, 1, 0, /* p factor */
308 31, /* gate */
309 0, 0, /* lock */
310 AW_CLK_HAS_GATE); /* flags */
311
312 static const char *pll_hsic_parents[] = {"osc24M"};
313 NKMP_CLK(pll_hsic_clk,
314 CLK_PLL_HSIC, /* id */
315 "pll_hsic", pll_hsic_parents, /* name, parents */
316 0x44, /* offset */
317 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
318 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
319 16, 1, 1, 0, /* m factor */
320 18, 1, 1, 0, /* p factor */
321 31, /* gate */
322 0, 0, /* lock */
323 AW_CLK_HAS_GATE); /* flags */
324
325 static const char *pll_de_parents[] = {"osc24M"};
326 NKMP_CLK(pll_de_clk,
327 CLK_PLL_DE, /* id */
328 "pll_de", pll_de_parents, /* name, parents */
329 0x48, /* offset */
330 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
331 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
332 16, 1, 1, 0, /* m factor */
333 18, 1, 1, 0, /* p factor */
334 31, /* gate */
335 0, 0, /* lock */
336 AW_CLK_HAS_GATE); /* flags */
337
338 static const char *pll_video1_parents[] = {"osc24M"};
339 NKMP_CLK(pll_video1_clk,
340 CLK_PLL_VIDEO1, /* id */
341 "pll_video1", pll_video1_parents, /* name, parents */
342 0x4c, /* offset */
343 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
344 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
345 16, 1, 1, 0, /* m factor */
346 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */
347 31, /* gate */
348 0, 0, /* lock */
349 AW_CLK_HAS_GATE); /* flags */
350
351 static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"};
352 MUX_CLK(c0cpux_clk,
353 CLK_C0CPUX, /* id */
354 "c0cpux", c0cpux_parents, /* name, parents */
355 0x50, 12, 1); /* offset, shift, width */
356
357 static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"};
358 MUX_CLK(c1cpux_clk,
359 CLK_C1CPUX, /* id */
360 "c1cpux", c1cpux_parents, /* name, parents */
361 0x50, 28, 1); /* offset, shift, width */
362
363 static const char *axi0_parents[] = {"c0cpux"};
364 DIV_CLK(axi0_clk,
365 CLK_AXI0, /* id */
366 "axi0", axi0_parents, /* name, parents */
367 0x50, /* offset */
368 0, 2, /* shift, width */
369 0, NULL); /* flags, div table */
370
371 static const char *axi1_parents[] = {"c1cpux"};
372 DIV_CLK(axi1_clk,
373 CLK_AXI1, /* id */
374 "axi1", axi1_parents, /* name, parents */
375 0x50, /* offset */
376 16, 2, /* shift, width */
377 0, NULL); /* flags, div table */
378
379 static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
380 PREDIV_CLK_WITH_MASK(ahb1_clk,
381 CLK_AHB1, /* id */
382 "ahb1", ahb1_parents, /* name, parents */
383 0x54, /* offset */
384 12, 2, /* mux */
385 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
386 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
387 (2 << 12), (2 << 12)); /* prediv condition */
388
389 static const char *apb1_parents[] = {"ahb1"};
390 DIV_CLK(apb1_clk,
391 CLK_APB1, /* id */
392 "apb1", apb1_parents, /* name, parents */
393 0x54, /* offset */
394 8, 2, /* shift, width */
395 0, NULL); /* flags, div table */
396
397 static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
398 NM_CLK(apb2_clk,
399 CLK_APB2, /* id */
400 "apb2", apb2_parents, /* name, parents */
401 0x58, /* offset */
402 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
403 0, 5, 0, 0, /* m factor */
404 24, 2, /* mux */
405 0, /* gate */
406 AW_CLK_HAS_MUX);
407
408 static const char *ahb2_parents[] = {"ahb1", "pll_periph"};
409 PREDIV_CLK(ahb2_clk,
410 CLK_AHB2, /* id */
411 "ahb2", ahb2_parents, /* name, parents */
412 0x5c,
413 0, 2, /* mux */
414 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div (fake) */
415 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */
416 0, 2, 1); /* prediv cond */
417
418 /* Actually has a divider, but we don't use it */
419 static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"};
420 MUX_CLK(cci400_clk,
421 CLK_CCI400, /* id */
422 "cci400", cci400_parents, /* name, parents */
423 0x78, 24, 2); /* offset, shift, width */
424
425 static const char *mod_parents[] = {"osc24M", "pll_periph"};
426
427 NM_CLK(nand_clk,
428 CLK_NAND, /* id */
429 "nand", mod_parents, /* name, parents */
430 0x80, /* offset */
431 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
432 0, 4, 0, 0, /* m factor */
433 24, 2, /* mux */
434 31, /* gate */
435 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
436
437 NM_CLK(mmc0_clk,
438 CLK_MMC0, /* id */
439 "mmc0", mod_parents, /* name, parents */
440 0x88, /* offset */
441 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
442 0, 4, 0, 0, /* m factor */
443 24, 2, /* mux */
444 31, /* gate */
445 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
446 AW_CLK_REPARENT);
447 NM_CLK(mmc1_clk,
448 CLK_MMC1, /* id */
449 "mmc1", mod_parents, /* name, parents */
450 0x8c, /* offset */
451 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
452 0, 4, 0, 0, /* m factor */
453 24, 2, /* mux */
454 31, /* gate */
455 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
456 AW_CLK_REPARENT);
457 NM_CLK(mmc2_clk,
458 CLK_MMC2, /* id */
459 "mmc2", mod_parents, /* name, parents */
460 0x90, /* offset */
461 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
462 0, 4, 0, 0, /* m factor */
463 24, 2, /* mux */
464 31, /* gate */
465 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
466 AW_CLK_REPARENT);
467
468 NM_CLK(ss_clk,
469 CLK_SS, /* id */
470 "ss", mod_parents, /* name, parents */
471 0x9c, /* offset */
472 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
473 0, 4, 0, 0, /* m factor */
474 24, 2, /* mux */
475 31, /* gate */
476 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
477
478 NM_CLK(spi0_clk,
479 CLK_SPI0, /* id */
480 "spi0", mod_parents, /* name, parents */
481 0xa0, /* offset */
482 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
483 0, 4, 0, 0, /* m factor */
484 24, 2, /* mux */
485 31, /* gate */
486 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
487 NM_CLK(spi1_clk,
488 CLK_SPI1, /* id */
489 "spi1", mod_parents, /* name, parents */
490 0xa4, /* offset */
491 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
492 0, 4, 0, 0, /* m factor */
493 24, 2, /* mux */
494 31, /* gate */
495 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
496
497 static const char *daudio_parents[] = {"pll_audio"};
498 NM_CLK(i2s0_clk,
499 CLK_I2S0, /* id */
500 "i2s0", daudio_parents, /* name, parents */
501 0xb0, /* offset */
502 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
503 0, 4, 0, 0, /* m factor */
504 0, 0, /* mux */
505 31, /* gate */
506 AW_CLK_HAS_GATE);
507 NM_CLK(i2s1_clk,
508 CLK_I2S1, /* id */
509 "i2s1", daudio_parents, /* name, parents */
510 0xb4, /* offset */
511 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
512 0, 4, 0, 0, /* m factor */
513 0, 0, /* mux */
514 31, /* gate */
515 AW_CLK_HAS_GATE);
516 NM_CLK(i2s2_clk,
517 CLK_I2S2, /* id */
518 "i2s2", daudio_parents, /* name, parents */
519 0xb8, /* offset */
520 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
521 0, 4, 0, 0, /* m factor */
522 0, 0, /* mux */
523 31, /* gate */
524 AW_CLK_HAS_GATE);
525
526 static const char *tdm_parents[] = {"pll_audio"};
527 NM_CLK(tdm_clk,
528 CLK_TDM, /* id */
529 "tdm", tdm_parents, /* name, parents */
530 0xbc, /* offset */
531 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
532 0, 4, 0, 0, /* m factor */
533 0, 0, /* mux */
534 31, /* gate */
535 AW_CLK_HAS_GATE);
536
537 static const char *spdif_parents[] = {"pll_audio"};
538 NM_CLK(spdif_clk,
539 CLK_SPDIF, /* id */
540 "spdif", spdif_parents, /* name, parents */
541 0xc0, /* offset */
542 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
543 0, 4, 0, 0, /* m factor */
544 0, 0, /* mux */
545 31, /* gate */
546 AW_CLK_HAS_GATE);
547
548 static const char *dram_parents[] = {"pll_ddr"};
549 NM_CLK(dram_clk,
550 CLK_DRAM, /* id */
551 "dram", dram_parents, /* name, parents */
552 0xf4, /* offset */
553 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
554 0, 4, 0, 0, /* m factor */
555 0, 0, /* mux */
556 0, /* gate */
557 0);
558
559 static const char *tcon0_parents[] = {"pll_video0"};
560 MUX_CLK(tcon0_clk,
561 CLK_TCON0, /* id */
562 "tcon0", tcon0_parents, /* name, parents */
563 0x118, 24, 2); /* offset, shift, width */
564
565 static const char *tcon1_parents[] = {"pll_video1"};
566 NM_CLK(tcon1_clk,
567 CLK_TCON1, /* id */
568 "tcon1", tcon1_parents, /* name, parents */
569 0x11c, /* offset */
570 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
571 0, 4, 0, 0, /* m factor */
572 0, 0, /* mux */
573 31, /* gate */
574 AW_CLK_HAS_GATE);
575
576 static const char *csi_mclk_parents[] = {"pll_de", "osc24M"};
577 NM_CLK(csi_mclk_clk,
578 CLK_CSI_MCLK, /* id */
579 "csi-mclk", csi_mclk_parents, /* name, parents */
580 0x134, /* offset */
581 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
582 0, 4, 0, 0, /* m factor */
583 8, 3, /* mux */
584 15, /* gate */
585 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
586
587 static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"};
588 NM_CLK(csi_sclk_clk,
589 CLK_CSI_SCLK, /* id */
590 "csi-sclk", csi_sclk_parents, /* name, parents */
591 0x134, /* offset */
592 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
593 16, 4, 0, 0, /* m factor */
594 24, 3, /* mux */
595 31, /* gate */
596 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
597
598 static const char *ve_parents[] = {"pll_ve"};
599 NM_CLK(ve_clk,
600 CLK_VE, /* id */
601 "ve", ve_parents, /* name, parents */
602 0x13c, /* offset */
603 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
604 16, 3, 0, 0, /* m factor */
605 0, 0, /* mux */
606 31, /* gate */
607 AW_CLK_HAS_GATE);
608
609 static const char *hdmi_parents[] = {"pll_video1"};
610 NM_CLK(hdmi_clk,
611 CLK_HDMI, /* id */
612 "hdmi", hdmi_parents, /* name, parents */
613 0x150, /* offset */
614 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
615 0, 4, 0, 0, /* m factor */
616 24, 2, /* mux */
617 31, /* gate */
618 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
619
620 static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"};
621 NM_CLK(mbus_clk,
622 CLK_MBUS, /* id */
623 "mbus", mbus_parents, /* name, parents */
624 0x15c, /* offset */
625 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
626 0, 3, 0, 0, /* m factor */
627 24, 2, /* mux */
628 31, /* gate */
629 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
630
631 static const char *mipi_dsi0_parents[] = {"pll_video0"};
632 NM_CLK(mipi_dsi0_clk,
633 CLK_MIPI_DSI0, /* id */
634 "mipi-dsi0", mipi_dsi0_parents, /* name, parents */
635 0x168, /* offset */
636 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
637 0, 4, 0, 0, /* m factor */
638 24, 4, /* mux */
639 31, /* gate */
640 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
641
642 static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"};
643 NM_CLK(mipi_dsi1_clk,
644 CLK_MIPI_DSI1, /* id */
645 "mipi-dsi1", mipi_dsi1_parents, /* name, parents */
646 0x16c, /* offset */
647 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
648 0, 4, 0, 0, /* m factor */
649 24, 4, /* mux */
650 31, /* gate */
651 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
652
653 static const char *gpu_core_parents[] = {"pll_gpu"};
654 NM_CLK(gpu_core_clk,
655 CLK_GPU_CORE, /* id */
656 "gpu-core", gpu_core_parents, /* name, parents */
657 0x1a0, /* offset */
658 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
659 0, 3, 0, 0, /* m factor */
660 0, 0, /* mux */
661 31, /* gate */
662 AW_CLK_HAS_GATE);
663
664 static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"};
665 NM_CLK(gpu_memory_clk,
666 CLK_GPU_MEMORY, /* id */
667 "gpu-memory", gpu_memory_parents, /* name, parents */
668 0x1a4, /* offset */
669 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
670 0, 3, 0, 0, /* m factor */
671 24, 1, /* mux */
672 31, /* gate */
673 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
674
675 static const char *gpu_hyd_parents[] = {"pll_gpu"};
676 NM_CLK(gpu_hyd_clk,
677 CLK_GPU_HYD, /* id */
678 "gpu-hyd", gpu_hyd_parents, /* name, parents */
679 0x1a0, /* offset */
680 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
681 0, 3, 0, 0, /* m factor */
682 0, 0, /* mux */
683 31, /* gate */
684 AW_CLK_HAS_GATE);
685
686 static struct aw_ccung_clk a83t_clks[] = {
687 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
688 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video0_clk},
689 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ve_clk},
690 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
691 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk},
692 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_gpu_clk},
693 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_hsic_clk},
694 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_de_clk},
695 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video1_clk},
696 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c0cpux_clk},
697 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c1cpux_clk},
698 { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
699 { .type = AW_CLK_NM, .clk.nm = &nand_clk},
700 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
701 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
702 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
703 { .type = AW_CLK_NM, .clk.nm = &ss_clk},
704 { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
705 { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
706 { .type = AW_CLK_NM, .clk.nm = &i2s0_clk},
707 { .type = AW_CLK_NM, .clk.nm = &i2s1_clk},
708 { .type = AW_CLK_NM, .clk.nm = &i2s2_clk},
709 { .type = AW_CLK_NM, .clk.nm = &tdm_clk},
710 { .type = AW_CLK_NM, .clk.nm = &spdif_clk},
711 { .type = AW_CLK_NM, .clk.nm = &dram_clk},
712 { .type = AW_CLK_NM, .clk.nm = &tcon1_clk},
713 { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk},
714 { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk},
715 { .type = AW_CLK_NM, .clk.nm = &ve_clk},
716 { .type = AW_CLK_NM, .clk.nm = &hdmi_clk},
717 { .type = AW_CLK_NM, .clk.nm = &mbus_clk},
718 { .type = AW_CLK_NM, .clk.nm = &mipi_dsi0_clk},
719 { .type = AW_CLK_NM, .clk.nm = &mipi_dsi1_clk},
720 { .type = AW_CLK_NM, .clk.nm = &gpu_core_clk},
721 { .type = AW_CLK_NM, .clk.nm = &gpu_memory_clk},
722 { .type = AW_CLK_NM, .clk.nm = &gpu_hyd_clk},
723 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk},
724 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk},
725 { .type = AW_CLK_MUX, .clk.mux = &c0cpux_clk},
726 { .type = AW_CLK_MUX, .clk.mux = &c1cpux_clk},
727 { .type = AW_CLK_MUX, .clk.mux = &cci400_clk},
728 { .type = AW_CLK_MUX, .clk.mux = &tcon0_clk},
729 { .type = AW_CLK_DIV, .clk.div = &axi0_clk},
730 { .type = AW_CLK_DIV, .clk.div = &axi1_clk},
731 { .type = AW_CLK_DIV, .clk.div = &apb1_clk},
732 { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk},
733 };
734
735 static struct aw_clk_init a83t_init_clks[] = {
736 {"ahb1", "pll_periph", 0, false},
737 {"ahb2", "ahb1", 0, false},
738 {"dram", "pll_ddr", 0, false},
739 };
740
741 static int
ccu_a83t_probe(device_t dev)742 ccu_a83t_probe(device_t dev)
743 {
744
745 if (!ofw_bus_status_okay(dev))
746 return (ENXIO);
747
748 if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-ccu"))
749 return (ENXIO);
750
751 device_set_desc(dev, "Allwinner A83T Clock Control Unit NG");
752 return (BUS_PROBE_DEFAULT);
753 }
754
755 static int
ccu_a83t_attach(device_t dev)756 ccu_a83t_attach(device_t dev)
757 {
758 struct aw_ccung_softc *sc;
759
760 sc = device_get_softc(dev);
761
762 sc->resets = a83t_ccu_resets;
763 sc->nresets = nitems(a83t_ccu_resets);
764 sc->gates = a83t_ccu_gates;
765 sc->ngates = nitems(a83t_ccu_gates);
766 sc->clks = a83t_clks;
767 sc->nclks = nitems(a83t_clks);
768 sc->clk_init = a83t_init_clks;
769 sc->n_clk_init = nitems(a83t_init_clks);
770
771 return (aw_ccung_attach(dev));
772 }
773
774 static device_method_t ccu_a83tng_methods[] = {
775 /* Device interface */
776 DEVMETHOD(device_probe, ccu_a83t_probe),
777 DEVMETHOD(device_attach, ccu_a83t_attach),
778
779 DEVMETHOD_END
780 };
781
782 static devclass_t ccu_a83tng_devclass;
783
784 DEFINE_CLASS_1(ccu_a83tng, ccu_a83tng_driver, ccu_a83tng_methods,
785 sizeof(struct aw_ccung_softc), aw_ccung_driver);
786
787 EARLY_DRIVER_MODULE(ccu_a83tng, simplebus, ccu_a83tng_driver,
788 ccu_a83tng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
789