1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Adrian Chadd <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_ddb.h"
33
34 #include <sys/param.h>
35 #include <sys/conf.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cons.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42
43 #include <vm/vm.h>
44 #include <vm/vm_page.h>
45
46 #include <net/ethernet.h>
47
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
55
56 #include <mips/atheros/ar71xxreg.h>
57 #include <mips/atheros/ar933xreg.h>
58
59 #include <mips/atheros/ar71xx_cpudef.h>
60 #include <mips/atheros/ar71xx_setup.h>
61
62 #include <mips/atheros/ar71xx_chip.h>
63 #include <mips/atheros/ar933x_chip.h>
64
65 static void
ar933x_chip_detect_mem_size(void)66 ar933x_chip_detect_mem_size(void)
67 {
68 }
69
70 static void
ar933x_chip_detect_sys_frequency(void)71 ar933x_chip_detect_sys_frequency(void)
72 {
73 uint32_t clock_ctrl;
74 uint32_t cpu_config;
75 uint32_t freq;
76 uint32_t t;
77
78 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
79 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
80 u_ar71xx_refclk = (40 * 1000 * 1000);
81 else
82 u_ar71xx_refclk = (25 * 1000 * 1000);
83
84 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
85 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
86 u_ar71xx_cpu_freq = u_ar71xx_refclk;
87 u_ar71xx_ahb_freq = u_ar71xx_refclk;
88 u_ar71xx_ddr_freq = u_ar71xx_refclk;
89 } else {
90 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
91
92 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
93 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
94 freq = u_ar71xx_refclk / t;
95
96 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
97 AR933X_PLL_CPU_CONFIG_NINT_MASK;
98 freq *= t;
99
100 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
101 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
102 if (t == 0)
103 t = 1;
104
105 freq >>= t;
106
107 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
108 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
109 u_ar71xx_cpu_freq = freq / t;
110
111 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
112 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
113 u_ar71xx_ddr_freq = freq / t;
114
115 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
116 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
117 u_ar71xx_ahb_freq = freq / t;
118 }
119
120 /*
121 * On the AR933x, the UART frequency is the reference clock,
122 * not the AHB bus clock.
123 */
124 u_ar71xx_uart_freq = u_ar71xx_refclk;
125
126 /*
127 * XXX TODO: check whether the mdio frequency is always the
128 * refclock frequency, or whether it's variable like on the
129 * AR934x.
130 */
131 u_ar71xx_mdio_freq = u_ar71xx_refclk;
132
133 /*
134 * XXX check what the watchdog frequency should be?
135 */
136 u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
137 }
138
139 static void
ar933x_chip_device_stop(uint32_t mask)140 ar933x_chip_device_stop(uint32_t mask)
141 {
142 uint32_t reg;
143
144 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
145 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
146 }
147
148 static void
ar933x_chip_device_start(uint32_t mask)149 ar933x_chip_device_start(uint32_t mask)
150 {
151 uint32_t reg;
152
153 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
154 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
155 }
156
157 static int
ar933x_chip_device_stopped(uint32_t mask)158 ar933x_chip_device_stopped(uint32_t mask)
159 {
160 uint32_t reg;
161
162 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
163 return ((reg & mask) == mask);
164 }
165
166 static void
ar933x_chip_set_mii_speed(uint32_t unit,uint32_t speed)167 ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
168 {
169
170 /* XXX TODO */
171 return;
172 }
173
174 /*
175 * XXX TODO !!
176 */
177 static void
ar933x_chip_set_pll_ge(int unit,int speed,uint32_t pll)178 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
179 {
180
181 switch (unit) {
182 case 0:
183 /* XXX TODO */
184 break;
185 case 1:
186 /* XXX TODO */
187 break;
188 default:
189 printf("%s: invalid PLL set for arge unit: %d\n",
190 __func__, unit);
191 return;
192 }
193 }
194
195 static void
ar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)196 ar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
197 {
198
199 switch (id) {
200 case AR71XX_CPU_DDR_FLUSH_GE0:
201 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
202 break;
203 case AR71XX_CPU_DDR_FLUSH_GE1:
204 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
205 break;
206 case AR71XX_CPU_DDR_FLUSH_USB:
207 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
208 break;
209 case AR71XX_CPU_DDR_FLUSH_WMAC:
210 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
211 break;
212 default:
213 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
214 break;
215 }
216 }
217
218 static uint32_t
ar933x_chip_get_eth_pll(unsigned int mac,int speed)219 ar933x_chip_get_eth_pll(unsigned int mac, int speed)
220 {
221 uint32_t pll;
222
223 switch (speed) {
224 case 10:
225 pll = AR933X_PLL_VAL_10;
226 break;
227 case 100:
228 pll = AR933X_PLL_VAL_100;
229 break;
230 case 1000:
231 pll = AR933X_PLL_VAL_1000;
232 break;
233 default:
234 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
235 pll = 0;
236 }
237 return (pll);
238 }
239
240 static void
ar933x_chip_init_usb_peripheral(void)241 ar933x_chip_init_usb_peripheral(void)
242 {
243 ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
244 DELAY(100);
245
246 ar71xx_device_start(AR933X_RESET_USB_HOST);
247 DELAY(100);
248
249 ar71xx_device_start(AR933X_RESET_USB_PHY);
250 DELAY(100);
251 }
252
253 static void
ar933x_configure_gmac(uint32_t gmac_cfg)254 ar933x_configure_gmac(uint32_t gmac_cfg)
255 {
256 uint32_t reg;
257
258 reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG);
259
260 /*
261 * The relevant bits here include:
262 *
263 * + AR933X_ETH_CFG_SW_PHY_SWAP
264 * + AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
265 *
266 * There are other things; look at what openwrt exposes so
267 * it can be correctly exposed.
268 *
269 * TODO: what about ethernet switch support? How's that work?
270 */
271 if (bootverbose)
272 printf("%s: GMAC config was 0x%08x\n", __func__, reg);
273 reg &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
274 reg |= gmac_cfg;
275 if (bootverbose)
276 printf("%s: GMAC setting is 0x%08x; register is now 0x%08x\n",
277 __func__,
278 gmac_cfg,
279 reg);
280 ATH_WRITE_REG(AR933X_GMAC_REG_ETH_CFG, reg);
281 }
282
283 static void
ar933x_chip_init_gmac(void)284 ar933x_chip_init_gmac(void)
285 {
286 int val;
287 uint32_t gmac_cfg = 0;
288
289 /*
290 * These two bits need a bit better explanation.
291 *
292 * The default configuration in the hardware is to map both
293 * ports to the internal switch.
294 *
295 * Here, GE0 == arge0, GE1 == arge1.
296 *
297 * The internal switch has:
298 * + 5 MAC ports, MAC0->MAC4.
299 * + 5 PHY ports, PHY0->PHY4,
300 * + MAC0 connects to GE1;
301 * + GE0 connects to PHY4;
302 * + The other mappings are MAC1->PHY0, MAC2->PHY1 .. MAC4->PHY3.
303 *
304 * The GE1 port is linked in via 1000MBit/full, supplying what is
305 * normally the 'WAN' switch ports.
306 *
307 * The switch is connected the MDIO bus on GE1. It looks like
308 * a normal AR7240 on-board switch.
309 *
310 * The GE0 port is connected via MII to PHY4, and can operate in
311 * 10/100mbit, full/half duplex. Ie, you can speak to PHY4 on
312 * the MDIO bus and everything will simply 'work'.
313 *
314 * So far so good. This looks just like an AR7240 SoC.
315 *
316 * However, some configurations will just expose one or two
317 * physical ports. In this case, some configuration bits can
318 * be set to tweak this.
319 *
320 * + CFG_SW_PHY_ADDR_SWAP swaps PHY port 0 with PHY port 4.
321 * Ie, GE0's PHY shows up as PHY 0. So if there's only
322 * one physical port, there's no need to involve the
323 * switch framework - it can just show up as a default,
324 * normal single PHY.
325 *
326 * + CFG_SW_PHY_SWAP swaps the internal switch connection
327 * between PHY0 and PHY4. Ie, PHY4 connects to MAc1,
328 * PHY0 connects to GE0.
329 */
330 if ((resource_int_value("ar933x_gmac", 0, "override_phy", &val) == 0)
331 && (val == 0))
332 return;
333 if ((resource_int_value("ar933x_gmac", 0, "swap_phy", &val) == 0)
334 && (val == 1))
335 gmac_cfg |= AR933X_ETH_CFG_SW_PHY_SWAP;
336 if ((resource_int_value("ar933x_gmac", 0, "swap_phy_addr", &val) == 0)
337 && (val == 1))
338 gmac_cfg |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
339 ar933x_configure_gmac(gmac_cfg);
340 }
341
342 struct ar71xx_cpu_def ar933x_chip_def = {
343 &ar933x_chip_detect_mem_size,
344 &ar933x_chip_detect_sys_frequency,
345 &ar933x_chip_device_stop,
346 &ar933x_chip_device_start,
347 &ar933x_chip_device_stopped,
348 &ar933x_chip_set_pll_ge,
349 &ar933x_chip_set_mii_speed,
350 &ar71xx_chip_set_mii_if,
351 &ar933x_chip_get_eth_pll,
352 &ar933x_chip_ddr_flush,
353 &ar933x_chip_init_usb_peripheral,
354 NULL,
355 NULL,
356 &ar933x_chip_init_gmac,
357 };
358