1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009, Oleksandr Tymoshenko <[email protected]>
5 * Copyright (c) 2011, Luiz Otavio O Souza.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include "opt_ar71xx.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38
39 #include <sys/bus.h>
40 #include <sys/interrupt.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/rman.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <vm/vm_extern.h>
49
50 #include <machine/bus.h>
51 #include <machine/cpu.h>
52 #include <machine/intr_machdep.h>
53
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56
57 #include <dev/pci/pcib_private.h>
58 #include "pcib_if.h"
59
60 #include <mips/atheros/ar71xxreg.h>
61 #include <mips/atheros/ar724xreg.h>
62 #include <mips/atheros/ar71xx_setup.h>
63 #include <mips/atheros/ar71xx_pci_bus_space.h>
64
65 #include <mips/atheros/ar71xx_cpudef.h>
66
67 #ifdef AR71XX_ATH_EEPROM
68 #include <mips/atheros/ar71xx_fixup.h>
69 #endif /* AR71XX_ATH_EEPROM */
70
71 #undef AR724X_PCI_DEBUG
72 #ifdef AR724X_PCI_DEBUG
73 #define dprintf printf
74 #else
75 #define dprintf(x, arg...)
76 #endif
77
78 struct ar71xx_pci_softc {
79 device_t sc_dev;
80
81 int sc_busno;
82 struct rman sc_mem_rman;
83 struct rman sc_irq_rman;
84
85 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
86 mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
87 struct resource *sc_irq;
88 void *sc_ih;
89 };
90
91 static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
92 driver_filter_t *, driver_intr_t *, void *, void **);
93 static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
94 void *);
95 static int ar724x_pci_intr(void *);
96
97 static void
ar724x_pci_write(uint32_t reg,uint32_t offset,uint32_t data,int bytes)98 ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
99 {
100 uint32_t val, mask, shift;
101
102 /* Register access is 32-bit aligned */
103 shift = (offset & 3) * 8;
104 if (bytes % 4)
105 mask = (1 << (bytes * 8)) - 1;
106 else
107 mask = 0xffffffff;
108
109 rmb();
110 val = ATH_READ_REG(reg + (offset & ~3));
111 val &= ~(mask << shift);
112 val |= ((data & mask) << shift);
113 ATH_WRITE_REG(reg + (offset & ~3), val);
114 wmb();
115
116 dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
117 reg, reg + (offset & ~3), offset, data, val, bytes);
118 }
119
120 static uint32_t
ar724x_pci_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)121 ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
122 u_int reg, int bytes)
123 {
124 uint32_t data, shift, mask;
125
126 /* Register access is 32-bit aligned */
127 shift = (reg & 3) * 8;
128
129 /* Create a mask based on the width, post-shift */
130 if (bytes == 2)
131 mask = 0xffff;
132 else if (bytes == 1)
133 mask = 0xff;
134 else
135 mask = 0xffffffff;
136
137 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
138 func, reg, bytes);
139
140 rmb();
141 if ((bus == 0) && (slot == 0) && (func == 0))
142 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
143 else
144 data = -1;
145
146 /* Get request bytes from 32-bit word */
147 data = (data >> shift) & mask;
148
149 dprintf("%s: read 0x%x\n", __func__, data);
150
151 return (data);
152 }
153
154 static void
ar724x_pci_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)155 ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
156 u_int reg, uint32_t data, int bytes)
157 {
158
159 dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
160 func, reg, bytes, data);
161
162 if ((bus != 0) || (slot != 0) || (func != 0))
163 return;
164
165 /*
166 * WAR for BAR issue on AR7240 - We are unable to access the PCI
167 * device space if we set the BAR with proper base address.
168 *
169 * However, we _do_ want to allow programming in the probe value
170 * (0xffffffff) so the PCI code can find out how big the memory
171 * map is for this device. Without it, it'll think the memory
172 * map is 32 bits wide, the PCI code will then end up thinking
173 * the register window is '0' and fail to allocate resources.
174 *
175 * Note: Test on AR7241/AR7242/AR9344! Those use a WAR value of
176 * 0x1000ffff.
177 */
178 if (reg == PCIR_BAR(0) && bytes == 4
179 && ar71xx_soc == AR71XX_SOC_AR7240
180 && data != 0xffffffff)
181 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, 0xffff, bytes);
182 else
183 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
184 }
185
186 static void
ar724x_pci_mask_irq(void * source)187 ar724x_pci_mask_irq(void *source)
188 {
189 uint32_t reg;
190 unsigned int irq = (unsigned int)source;
191
192 /* XXX - Only one interrupt ? Only one device ? */
193 if (irq != AR71XX_PCI_IRQ_START)
194 return;
195
196 /* Update the interrupt mask reg */
197 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
198 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
199 reg & ~AR724X_PCI_INTR_DEV0);
200
201 /* Clear any pending interrupt */
202 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
203 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
204 reg | AR724X_PCI_INTR_DEV0);
205 }
206
207 static void
ar724x_pci_unmask_irq(void * source)208 ar724x_pci_unmask_irq(void *source)
209 {
210 uint32_t reg;
211 unsigned int irq = (unsigned int)source;
212
213 /* XXX */
214 if (irq != AR71XX_PCI_IRQ_START)
215 return;
216
217 /* Update the interrupt mask reg */
218 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
219 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
220 reg | AR724X_PCI_INTR_DEV0);
221 }
222
223 static int
ar724x_pci_setup(device_t dev)224 ar724x_pci_setup(device_t dev)
225 {
226 uint32_t reg;
227
228 /* setup COMMAND register */
229 reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
230 PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
231
232 ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
233 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
234 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
235
236 reg = ATH_READ_REG(AR724X_PCI_RESET);
237 if (reg != 0x7) {
238 DELAY(100000);
239 ATH_WRITE_REG(AR724X_PCI_RESET, 0);
240 DELAY(100);
241 ATH_WRITE_REG(AR724X_PCI_RESET, 4);
242 DELAY(100000);
243 }
244
245 if (ar71xx_soc == AR71XX_SOC_AR7240)
246 reg = AR724X_PCI_APP_LTSSM_ENABLE;
247 else
248 reg = 0x1ffc1;
249 ATH_WRITE_REG(AR724X_PCI_APP, reg);
250 /* Flush write */
251 (void) ATH_READ_REG(AR724X_PCI_APP);
252
253 DELAY(1000);
254
255 reg = ATH_READ_REG(AR724X_PCI_RESET);
256 if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
257 device_printf(dev, "no PCIe controller found\n");
258 return (ENXIO);
259 }
260
261 if (ar71xx_soc == AR71XX_SOC_AR7241 ||
262 ar71xx_soc == AR71XX_SOC_AR7242) {
263 reg = ATH_READ_REG(AR724X_PCI_APP);
264 reg |= (1 << 16);
265 ATH_WRITE_REG(AR724X_PCI_APP, reg);
266 }
267
268 return (0);
269 }
270
271 #ifdef AR71XX_ATH_EEPROM
272 #define AR5416_EEPROM_MAGIC 0xa55a
273
274 /*
275 * XXX - This should not be here ! And this looks like Atheros (if_ath) only.
276 */
277 static void
ar724x_pci_fixup(device_t dev,long flash_addr,int len)278 ar724x_pci_fixup(device_t dev, long flash_addr, int len)
279 {
280 uint32_t bar0, reg, val;
281 uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
282
283 #if 0
284 if (cal_data[0] != AR5416_EEPROM_MAGIC) {
285 device_printf(dev, "%s: Invalid calibration data from 0x%x\n",
286 __func__, (uintptr_t) flash_addr);
287 return;
288 }
289 #endif
290
291 /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
292 bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
293
294 /* Write temporary BAR0 to map the NIC into a fixed location */
295 /* XXX AR7240: 0xffff; 7241/7242/9344: 0x1000ffff */
296 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
297 AR71XX_PCI_MEM_BASE, 4);
298
299 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
300 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
301 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
302
303 /* set pointer to first reg address */
304 cal_data += 3;
305 while (*cal_data != 0xffff) {
306 reg = *cal_data++;
307 val = *cal_data++;
308 val |= (*cal_data++) << 16;
309
310 if (bootverbose)
311 printf(" 0x%08x=0x%08x\n", reg, val);
312
313 /* Write eeprom fixup data to device memory */
314 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
315 DELAY(100);
316 }
317
318 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
319 val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
320 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
321
322 /* Write the saved bar(0) address */
323 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
324 }
325 #undef AR5416_EEPROM_MAGIC
326
327 /*
328 * XXX This is (mostly) duplicated with ar71xx_pci.c.
329 * It should at some point be fixed.
330 */
331 static void
ar724x_pci_slot_fixup(device_t dev)332 ar724x_pci_slot_fixup(device_t dev)
333 {
334 long int flash_addr;
335 char buf[64];
336 int size;
337
338 /*
339 * Check whether the given slot has a hint to poke.
340 */
341 if (bootverbose)
342 device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
343 __func__, device_get_nameunit(dev), 0, 0, 0);
344
345 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
346 0, 0, 0);
347
348 if (resource_long_value(device_get_name(dev), device_get_unit(dev),
349 buf, &flash_addr) == 0) {
350 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
351 0, 0, 0);
352 if (resource_int_value(device_get_name(dev),
353 device_get_unit(dev), buf, &size) != 0) {
354 device_printf(dev,
355 "%s: missing hint '%s', aborting EEPROM\n",
356 __func__, buf);
357 return;
358 }
359
360 device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
361 flash_addr, 0, 0, 0);
362 ar724x_pci_fixup(dev, flash_addr, size);
363 ar71xx_pci_slot_create_eeprom_firmware(dev, 0, 0, 0,
364 flash_addr, size);
365 }
366 }
367 #endif /* AR71XX_ATH_EEPROM */
368
369 static int
ar724x_pci_probe(device_t dev)370 ar724x_pci_probe(device_t dev)
371 {
372
373 return (BUS_PROBE_NOWILDCARD);
374 }
375
376 static int
ar724x_pci_attach(device_t dev)377 ar724x_pci_attach(device_t dev)
378 {
379 struct ar71xx_pci_softc *sc = device_get_softc(dev);
380 int rid = 0;
381
382 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
383 sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
384 if (rman_init(&sc->sc_mem_rman) != 0 ||
385 rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
386 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
387 panic("ar724x_pci_attach: failed to set up I/O rman");
388 }
389
390 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
391 sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
392 if (rman_init(&sc->sc_irq_rman) != 0 ||
393 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
394 AR71XX_PCI_IRQ_END) != 0)
395 panic("ar724x_pci_attach: failed to set up IRQ rman");
396
397 /* Disable interrupts */
398 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
399 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
400
401 /* Hook up our interrupt handler. */
402 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
403 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
404 device_printf(dev, "unable to allocate IRQ resource\n");
405 return (ENXIO);
406 }
407
408 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
409 ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
410 device_printf(dev,
411 "WARNING: unable to register interrupt handler\n");
412 return (ENXIO);
413 }
414
415 /* Reset PCIe core and PCIe PHY */
416 ar71xx_device_stop(AR724X_RESET_PCIE);
417 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
418 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
419 DELAY(100);
420
421 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
422 DELAY(100);
423 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
424 ar71xx_device_start(AR724X_RESET_PCIE);
425
426 if (ar724x_pci_setup(dev))
427 return (ENXIO);
428
429 #ifdef AR71XX_ATH_EEPROM
430 ar724x_pci_slot_fixup(dev);
431 #endif /* AR71XX_ATH_EEPROM */
432
433 /* Fixup internal PCI bridge */
434 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
435 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
436 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
437 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
438
439 device_add_child(dev, "pci", -1);
440 return (bus_generic_attach(dev));
441 }
442
443 static int
ar724x_pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)444 ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
445 {
446 struct ar71xx_pci_softc *sc = device_get_softc(dev);
447
448 switch (which) {
449 case PCIB_IVAR_DOMAIN:
450 *result = 0;
451 return (0);
452 case PCIB_IVAR_BUS:
453 *result = sc->sc_busno;
454 return (0);
455 }
456
457 return (ENOENT);
458 }
459
460 static int
ar724x_pci_write_ivar(device_t dev,device_t child,int which,uintptr_t result)461 ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
462 {
463 struct ar71xx_pci_softc * sc = device_get_softc(dev);
464
465 switch (which) {
466 case PCIB_IVAR_BUS:
467 sc->sc_busno = result;
468 return (0);
469 }
470
471 return (ENOENT);
472 }
473
474 static struct resource *
ar724x_pci_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)475 ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
476 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
477 {
478 struct ar71xx_pci_softc *sc = device_get_softc(bus);
479 struct resource *rv;
480 struct rman *rm;
481
482 switch (type) {
483 case SYS_RES_IRQ:
484 rm = &sc->sc_irq_rman;
485 break;
486 case SYS_RES_MEMORY:
487 rm = &sc->sc_mem_rman;
488 break;
489 default:
490 return (NULL);
491 }
492
493 rv = rman_reserve_resource(rm, start, end, count, flags, child);
494
495 if (rv == NULL)
496 return (NULL);
497
498 rman_set_rid(rv, *rid);
499
500 if (flags & RF_ACTIVE) {
501 if (bus_activate_resource(child, type, *rid, rv)) {
502 rman_release_resource(rv);
503 return (NULL);
504 }
505 }
506
507 return (rv);
508 }
509
510 static int
ar724x_pci_activate_resource(device_t bus,device_t child,int type,int rid,struct resource * r)511 ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
512 struct resource *r)
513 {
514 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
515 child, type, rid, r));
516
517 if (!res) {
518 switch(type) {
519 case SYS_RES_MEMORY:
520 case SYS_RES_IOPORT:
521
522 rman_set_bustag(r, ar71xx_bus_space_pcimem);
523 break;
524 }
525 }
526
527 return (res);
528 }
529
530 static int
ar724x_pci_setup_intr(device_t bus,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * handler,void * arg,void ** cookiep)531 ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
532 int flags, driver_filter_t *filt, driver_intr_t *handler,
533 void *arg, void **cookiep)
534 {
535 struct ar71xx_pci_softc *sc = device_get_softc(bus);
536 struct intr_event *event;
537 int irq, error;
538
539 irq = rman_get_start(ires);
540 if (irq > AR71XX_PCI_IRQ_END)
541 panic("%s: bad irq %d", __func__, irq);
542
543 event = sc->sc_eventstab[irq];
544 if (event == NULL) {
545 error = intr_event_create(&event, (void *)irq, 0, irq,
546 ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
547 "pci intr%d:", irq);
548
549 if (error == 0) {
550 sc->sc_eventstab[irq] = event;
551 sc->sc_intr_counter[irq] =
552 mips_intrcnt_create(event->ie_name);
553 }
554 else
555 return error;
556 }
557
558 intr_event_add_handler(event, device_get_nameunit(child), filt,
559 handler, arg, intr_priority(flags), flags, cookiep);
560 mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
561
562 ar724x_pci_unmask_irq((void*)irq);
563
564 return (0);
565 }
566
567 static int
ar724x_pci_teardown_intr(device_t dev,device_t child,struct resource * ires,void * cookie)568 ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
569 void *cookie)
570 {
571 struct ar71xx_pci_softc *sc = device_get_softc(dev);
572 int irq, result;
573
574 irq = rman_get_start(ires);
575 if (irq > AR71XX_PCI_IRQ_END)
576 panic("%s: bad irq %d", __func__, irq);
577
578 if (sc->sc_eventstab[irq] == NULL)
579 panic("Trying to teardown unoccupied IRQ");
580
581 ar724x_pci_mask_irq((void*)irq);
582
583 result = intr_event_remove_handler(cookie);
584 if (!result)
585 sc->sc_eventstab[irq] = NULL;
586
587 return (result);
588 }
589
590 static int
ar724x_pci_intr(void * arg)591 ar724x_pci_intr(void *arg)
592 {
593 struct ar71xx_pci_softc *sc = arg;
594 struct intr_event *event;
595 uint32_t reg, irq, mask;
596
597 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
598 mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
599 /*
600 * Handle only unmasked interrupts
601 */
602 reg &= mask;
603 if (reg & AR724X_PCI_INTR_DEV0) {
604 irq = AR71XX_PCI_IRQ_START;
605 event = sc->sc_eventstab[irq];
606 if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {
607 printf("Stray IRQ %d\n", irq);
608 return (FILTER_STRAY);
609 }
610
611 /* Flush pending memory transactions */
612 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
613
614 /* TODO: frame instead of NULL? */
615 intr_event_handle(event, NULL);
616 mips_intrcnt_inc(sc->sc_intr_counter[irq]);
617 }
618
619 return (FILTER_HANDLED);
620 }
621
622 static int
ar724x_pci_maxslots(device_t dev)623 ar724x_pci_maxslots(device_t dev)
624 {
625
626 return (PCI_SLOTMAX);
627 }
628
629 static int
ar724x_pci_route_interrupt(device_t pcib,device_t device,int pin)630 ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
631 {
632
633 return (pci_get_slot(device));
634 }
635
636 static device_method_t ar724x_pci_methods[] = {
637 /* Device interface */
638 DEVMETHOD(device_probe, ar724x_pci_probe),
639 DEVMETHOD(device_attach, ar724x_pci_attach),
640 DEVMETHOD(device_shutdown, bus_generic_shutdown),
641 DEVMETHOD(device_suspend, bus_generic_suspend),
642 DEVMETHOD(device_resume, bus_generic_resume),
643
644 /* Bus interface */
645 DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
646 DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
647 DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
648 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
649 DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
650 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
651 DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
652 DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
653
654 /* pcib interface */
655 DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
656 DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
657 DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
658 DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
659 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
660
661 DEVMETHOD_END
662 };
663
664 static driver_t ar724x_pci_driver = {
665 "pcib",
666 ar724x_pci_methods,
667 sizeof(struct ar71xx_pci_softc),
668 };
669
670 static devclass_t ar724x_pci_devclass;
671
672 DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
673