1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-bus"; 3 reg = <0x44c00000 0x800>, 4 <0x44c00800 0x800>, 5 <0x44c01000 0x400>, 6 <0x44c01400 0x400>; 7 reg-names = "ap", "la", "ia0", "ia1"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 13 14 segment@0 { /* 0x44c00000 */ 15 compatible = "simple-bus"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 19 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 20 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 21 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 22 }; 23 24 segment@100000 { /* 0x44d00000 */ 25 compatible = "simple-bus"; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 29 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 30 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 31 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 32 33 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 34 compatible = "ti,sysc-omap4", "ti,sysc"; 35 reg = <0x0 0x4>; 36 reg-names = "rev"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges = <0x0 0x0 0x4000>; 40 status = "disabled"; 41 }; 42 43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */ 44 compatible = "ti,sysc"; 45 status = "disabled"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x0 0x80000 0x2000>; 49 }; 50 }; 51 52 segment@200000 { /* 0x44e00000 */ 53 compatible = "simple-bus"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 57 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 58 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 59 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 60 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 61 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 62 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 63 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 64 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 70 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 71 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 72 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 73 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 74 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 75 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 76 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 77 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 78 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 79 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 80 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 81 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 86 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 87 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 88 89 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 90 compatible = "ti,sysc-omap4", "ti,sysc"; 91 reg = <0 0x4>; 92 reg-names = "rev"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0x0 0x0 0x2000>; 96 97 prcm: prcm@0 { 98 compatible = "ti,am3-prcm", "simple-bus"; 99 reg = <0 0x2000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0 0x2000>; 103 104 prcm_clocks: clocks { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 }; 108 109 prcm_clockdomains: clockdomains { 110 }; 111 }; 112 }; 113 114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 115 compatible = "ti,sysc"; 116 status = "disabled"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0x0 0x3000 0x1000>; 120 }; 121 122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 123 compatible = "ti,sysc"; 124 status = "disabled"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x0 0x5000 0x1000>; 128 }; 129 130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 131 compatible = "ti,sysc-omap2", "ti,sysc"; 132 reg = <0x7000 0x4>, 133 <0x7010 0x4>, 134 <0x7114 0x4>; 135 reg-names = "rev", "sysc", "syss"; 136 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 137 SYSC_OMAP2_SOFTRESET | 138 SYSC_OMAP2_AUTOIDLE)>; 139 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 140 <SYSC_IDLE_NO>, 141 <SYSC_IDLE_SMART>, 142 <SYSC_IDLE_SMART_WKUP>; 143 ti,syss-mask = <1>; 144 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 145 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 146 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 147 clock-names = "fck", "dbclk"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0x0 0x7000 0x1000>; 151 152 gpio0: gpio@0 { 153 compatible = "ti,omap4-gpio"; 154 gpio-ranges = <&am33xx_pinmux 0 82 8>, 155 <&am33xx_pinmux 8 52 4>, 156 <&am33xx_pinmux 12 94 4>, 157 <&am33xx_pinmux 16 71 2>, 158 <&am33xx_pinmux 18 135 1>, 159 <&am33xx_pinmux 19 108 2>, 160 <&am33xx_pinmux 21 73 1>, 161 <&am33xx_pinmux 22 8 2>, 162 <&am33xx_pinmux 26 10 2>, 163 <&am33xx_pinmux 28 74 1>, 164 <&am33xx_pinmux 29 81 1>, 165 <&am33xx_pinmux 30 28 2>; 166 gpio-controller; 167 #gpio-cells = <2>; 168 interrupt-controller; 169 #interrupt-cells = <2>; 170 reg = <0x0 0x1000>; 171 interrupts = <96>; 172 }; 173 }; 174 175 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 176 compatible = "ti,sysc-omap2", "ti,sysc"; 177 reg = <0x9050 0x4>, 178 <0x9054 0x4>, 179 <0x9058 0x4>; 180 reg-names = "rev", "sysc", "syss"; 181 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 182 SYSC_OMAP2_SOFTRESET | 183 SYSC_OMAP2_AUTOIDLE)>; 184 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 185 <SYSC_IDLE_NO>, 186 <SYSC_IDLE_SMART>, 187 <SYSC_IDLE_SMART_WKUP>; 188 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 189 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 190 clock-names = "fck"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0x0 0x9000 0x1000>; 194 195 uart0: serial@0 { 196 compatible = "ti,am3352-uart", "ti,omap3-uart"; 197 clock-frequency = <48000000>; 198 reg = <0x0 0x1000>; 199 interrupts = <72>; 200 status = "disabled"; 201 dmas = <&edma 26 0>, <&edma 27 0>; 202 dma-names = "tx", "rx"; 203 }; 204 }; 205 206 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 207 compatible = "ti,sysc-omap2", "ti,sysc"; 208 reg = <0xb000 0x8>, 209 <0xb010 0x8>, 210 <0xb090 0x8>; 211 reg-names = "rev", "sysc", "syss"; 212 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 213 SYSC_OMAP2_ENAWAKEUP | 214 SYSC_OMAP2_SOFTRESET | 215 SYSC_OMAP2_AUTOIDLE)>; 216 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 217 <SYSC_IDLE_NO>, 218 <SYSC_IDLE_SMART>, 219 <SYSC_IDLE_SMART_WKUP>; 220 ti,syss-mask = <1>; 221 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 222 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 223 clock-names = "fck"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0x0 0xb000 0x1000>; 227 228 i2c0: i2c@0 { 229 compatible = "ti,omap4-i2c"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 reg = <0x0 0x1000>; 233 interrupts = <70>; 234 status = "disabled"; 235 }; 236 }; 237 238 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 239 compatible = "ti,sysc-omap4", "ti,sysc"; 240 reg = <0xd000 0x4>, 241 <0xd010 0x4>; 242 reg-names = "rev", "sysc"; 243 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 244 <SYSC_IDLE_NO>, 245 <SYSC_IDLE_SMART>, 246 <SYSC_IDLE_SMART_WKUP>; 247 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 248 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 249 clock-names = "fck"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges = <0x00000000 0x0000d000 0x00001000>, 253 <0x00001000 0x0000e000 0x00001000>; 254 255 tscadc: tscadc@0 { 256 compatible = "ti,am3359-tscadc"; 257 reg = <0x0 0x1000>; 258 interrupts = <16>; 259 status = "disabled"; 260 dmas = <&edma 53 0>, <&edma 57 0>; 261 dma-names = "fifo0", "fifo1"; 262 263 tsc { 264 compatible = "ti,am3359-tsc"; 265 }; 266 am335x_adc: adc { 267 #io-channel-cells = <1>; 268 compatible = "ti,am3359-adc"; 269 }; 270 }; 271 }; 272 273 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 274 compatible = "ti,sysc-omap4", "ti,sysc"; 275 reg = <0x10000 0x4>; 276 reg-names = "rev"; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0x00000000 0x00010000 0x00010000>, 280 <0x00010000 0x00020000 0x00010000>; 281 282 scm: scm@0 { 283 compatible = "ti,am3-scm", "simple-bus"; 284 reg = <0x0 0x2000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 #pinctrl-cells = <1>; 288 ranges = <0 0 0x2000>; 289 290 am33xx_pinmux: pinmux@800 { 291 compatible = "pinctrl-single"; 292 reg = <0x800 0x238>; 293 #pinctrl-cells = <1>; 294 pinctrl-single,register-width = <32>; 295 pinctrl-single,function-mask = <0x7f>; 296 }; 297 298 scm_conf: scm_conf@0 { 299 compatible = "syscon", "simple-bus"; 300 reg = <0x0 0x800>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0 0 0x800>; 304 305 phy_gmii_sel: phy-gmii-sel { 306 compatible = "ti,am3352-phy-gmii-sel"; 307 reg = <0x650 0x4>; 308 #phy-cells = <2>; 309 }; 310 311 scm_clocks: clocks { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 }; 316 317 usb_ctrl_mod: control@620 { 318 compatible = "ti,am335x-usb-ctrl-module"; 319 reg = <0x620 0x10>, 320 <0x648 0x4>; 321 reg-names = "phy_ctrl", "wakeup"; 322 }; 323 324 wkup_m3_ipc: wkup_m3_ipc@1324 { 325 compatible = "ti,am3352-wkup-m3-ipc"; 326 reg = <0x1324 0x24>; 327 interrupts = <78>; 328 ti,rproc = <&wkup_m3>; 329 mboxes = <&mailbox &mbox_wkupm3>; 330 }; 331 332 edma_xbar: dma-router@f90 { 333 compatible = "ti,am335x-edma-crossbar"; 334 reg = <0xf90 0x40>; 335 #dma-cells = <3>; 336 dma-requests = <32>; 337 dma-masters = <&edma>; 338 }; 339 340 scm_clockdomains: clockdomains { 341 }; 342 }; 343 }; 344 345 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 346 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 347 reg = <0x31000 0x4>, 348 <0x31010 0x4>, 349 <0x31014 0x4>; 350 reg-names = "rev", "sysc", "syss"; 351 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 352 SYSC_OMAP2_SOFTRESET | 353 SYSC_OMAP2_AUTOIDLE)>; 354 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 355 <SYSC_IDLE_NO>, 356 <SYSC_IDLE_SMART>; 357 ti,syss-mask = <1>; 358 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 359 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 360 clock-names = "fck"; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges = <0x0 0x31000 0x1000>; 364 365 timer1: timer@0 { 366 compatible = "ti,am335x-timer-1ms"; 367 reg = <0x0 0x400>; 368 interrupts = <67>; 369 ti,timer-alwon; 370 clocks = <&timer1_fck>; 371 clock-names = "fck"; 372 }; 373 }; 374 375 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 376 compatible = "ti,sysc"; 377 status = "disabled"; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 ranges = <0x0 0x33000 0x1000>; 381 }; 382 383 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 384 compatible = "ti,sysc-omap2", "ti,sysc"; 385 reg = <0x35000 0x4>, 386 <0x35010 0x4>, 387 <0x35014 0x4>; 388 reg-names = "rev", "sysc", "syss"; 389 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 390 SYSC_OMAP2_SOFTRESET)>; 391 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 392 <SYSC_IDLE_NO>, 393 <SYSC_IDLE_SMART>, 394 <SYSC_IDLE_SMART_WKUP>; 395 ti,syss-mask = <1>; 396 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 397 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 398 clock-names = "fck"; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 ranges = <0x0 0x35000 0x1000>; 402 403 wdt2: wdt@0 { 404 compatible = "ti,omap3-wdt"; 405 reg = <0x0 0x1000>; 406 interrupts = <91>; 407 }; 408 }; 409 410 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 411 compatible = "ti,sysc"; 412 status = "disabled"; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 ranges = <0x0 0x37000 0x1000>; 416 }; 417 418 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 419 compatible = "ti,sysc"; 420 status = "disabled"; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges = <0x0 0x39000 0x1000>; 424 }; 425 426 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 427 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 428 ti,hwmods = "rtc"; 429 reg = <0x3e074 0x4>, 430 <0x3e078 0x4>; 431 reg-names = "rev", "sysc"; 432 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 433 <SYSC_IDLE_NO>, 434 <SYSC_IDLE_SMART>, 435 <SYSC_IDLE_SMART_WKUP>; 436 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 437 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 438 clock-names = "fck"; 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0x0 0x3e000 0x1000>; 442 443 rtc: rtc@0 { 444 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 445 reg = <0x0 0x1000>; 446 interrupts = <75 447 76>; 448 }; 449 }; 450 451 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 452 compatible = "ti,sysc"; 453 status = "disabled"; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0x0 0x40000 0x40000>; 457 }; 458 }; 459}; 460 461&l4_fw { /* 0x47c00000 */ 462 compatible = "ti,am33xx-l4-fw", "simple-bus"; 463 reg = <0x47c00000 0x800>, 464 <0x47c00800 0x800>, 465 <0x47c01000 0x400>; 466 reg-names = "ap", "la", "ia0"; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 470 471 segment@0 { /* 0x47c00000 */ 472 compatible = "simple-bus"; 473 #address-cells = <1>; 474 #size-cells = <1>; 475 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 476 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 477 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 478 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 479 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 480 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 481 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 482 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 483 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 484 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 485 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 486 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 487 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 488 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 489 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 490 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 491 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 492 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 493 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 494 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 495 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 496 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 497 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 498 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 499 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 500 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 501 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 502 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 503 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 504 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 505 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 506 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 507 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 508 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 509 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 510 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 511 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 512 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 513 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 514 515 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 516 compatible = "ti,sysc"; 517 status = "disabled"; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges = <0x0 0xc000 0x1000>; 521 }; 522 523 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 524 compatible = "ti,sysc"; 525 status = "disabled"; 526 #address-cells = <1>; 527 #size-cells = <1>; 528 ranges = <0x0 0xe000 0x1000>; 529 }; 530 531 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 532 compatible = "ti,sysc"; 533 status = "disabled"; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 ranges = <0x0 0x10000 0x1000>; 537 }; 538 539 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 540 compatible = "ti,sysc"; 541 status = "disabled"; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 ranges = <0x0 0x14000 0x1000>; 545 }; 546 547 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 548 compatible = "ti,sysc"; 549 status = "disabled"; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 ranges = <0x0 0x1a000 0x1000>; 553 }; 554 555 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 556 compatible = "ti,sysc"; 557 status = "disabled"; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 ranges = <0x0 0x24000 0x1000>; 561 }; 562 563 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 564 compatible = "ti,sysc"; 565 status = "disabled"; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 ranges = <0x0 0x26000 0x1000>; 569 }; 570 571 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 572 compatible = "ti,sysc"; 573 status = "disabled"; 574 #address-cells = <1>; 575 #size-cells = <1>; 576 ranges = <0x0 0x28000 0x1000>; 577 }; 578 579 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 580 compatible = "ti,sysc"; 581 status = "disabled"; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges = <0x0 0x30000 0x1000>; 585 }; 586 587 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 588 compatible = "ti,sysc"; 589 status = "disabled"; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges = <0x0 0x32000 0x1000>; 593 }; 594 595 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 596 compatible = "ti,sysc"; 597 status = "disabled"; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges = <0x0 0x38000 0x1000>; 601 }; 602 603 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 604 compatible = "ti,sysc"; 605 status = "disabled"; 606 #address-cells = <1>; 607 #size-cells = <1>; 608 ranges = <0x0 0x3a000 0x1000>; 609 }; 610 611 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 612 compatible = "ti,sysc"; 613 status = "disabled"; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 ranges = <0x0 0x3c000 0x1000>; 617 }; 618 619 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 620 compatible = "ti,sysc"; 621 status = "disabled"; 622 #address-cells = <1>; 623 #size-cells = <1>; 624 ranges = <0x0 0x3e000 0x1000>; 625 }; 626 627 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 628 compatible = "ti,sysc"; 629 status = "disabled"; 630 #address-cells = <1>; 631 #size-cells = <1>; 632 ranges = <0x0 0x40000 0x1000>; 633 }; 634 635 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 636 compatible = "ti,sysc"; 637 status = "disabled"; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges = <0x0 0x42000 0x1000>; 641 }; 642 643 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 644 compatible = "ti,sysc"; 645 status = "disabled"; 646 #address-cells = <1>; 647 #size-cells = <1>; 648 ranges = <0x0 0x44000 0x1000>; 649 }; 650 651 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 652 compatible = "ti,sysc"; 653 status = "disabled"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges = <0x0 0x46000 0x1000>; 657 }; 658 }; 659}; 660 661&l4_fast { /* 0x4a000000 */ 662 compatible = "ti,am33xx-l4-fast", "simple-bus"; 663 reg = <0x4a000000 0x800>, 664 <0x4a000800 0x800>, 665 <0x4a001000 0x400>; 666 reg-names = "ap", "la", "ia0"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 670 671 segment@0 { /* 0x4a000000 */ 672 compatible = "simple-bus"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 676 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 677 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 678 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 679 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 680 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 681 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 682 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 683 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 684 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 685 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 686 687 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 688 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 689 reg = <0x101200 0x4>, 690 <0x101208 0x4>, 691 <0x101204 0x4>; 692 reg-names = "rev", "sysc", "syss"; 693 ti,sysc-mask = <0>; 694 ti,sysc-midle = <SYSC_IDLE_FORCE>, 695 <SYSC_IDLE_NO>; 696 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 697 <SYSC_IDLE_NO>; 698 ti,syss-mask = <1>; 699 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 700 clock-names = "fck"; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges = <0x0 0x100000 0x8000>; 704 705 mac: ethernet@0 { 706 compatible = "ti,am335x-cpsw","ti,cpsw"; 707 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 708 clock-names = "fck", "cpts"; 709 cpdma_channels = <8>; 710 ale_entries = <1024>; 711 bd_ram_size = <0x2000>; 712 mac_control = <0x20>; 713 slaves = <2>; 714 active_slave = <0>; 715 cpts_clock_mult = <0x80000000>; 716 cpts_clock_shift = <29>; 717 reg = <0x0 0x800 718 0x1200 0x100>; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 /* 722 * c0_rx_thresh_pend 723 * c0_rx_pend 724 * c0_tx_pend 725 * c0_misc_pend 726 */ 727 interrupts = <40 41 42 43>; 728 ranges = <0 0 0x8000>; 729 syscon = <&scm_conf>; 730 status = "disabled"; 731 732 davinci_mdio: mdio@1000 { 733 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 734 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 735 clock-names = "fck"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 bus_freq = <1000000>; 739 reg = <0x1000 0x100>; 740 status = "disabled"; 741 }; 742 743 cpsw_emac0: slave@200 { 744 /* Filled in by U-Boot */ 745 mac-address = [ 00 00 00 00 00 00 ]; 746 phys = <&phy_gmii_sel 1 1>; 747 }; 748 749 cpsw_emac1: slave@300 { 750 /* Filled in by U-Boot */ 751 mac-address = [ 00 00 00 00 00 00 ]; 752 phys = <&phy_gmii_sel 2 1>; 753 }; 754 }; 755 }; 756 757 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 758 compatible = "ti,sysc"; 759 status = "disabled"; 760 #address-cells = <1>; 761 #size-cells = <1>; 762 ranges = <0x0 0x180000 0x20000>; 763 }; 764 765 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 766 compatible = "ti,sysc"; 767 status = "disabled"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges = <0x0 0x200000 0x80000>; 771 }; 772 773 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 774 compatible = "ti,sysc-pruss", "ti,sysc"; 775 reg = <0x326000 0x4>, 776 <0x326004 0x4>; 777 reg-names = "rev", "sysc"; 778 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 779 SYSC_PRUSS_SUB_MWAIT)>; 780 ti,sysc-midle = <SYSC_IDLE_FORCE>, 781 <SYSC_IDLE_NO>, 782 <SYSC_IDLE_SMART>; 783 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 784 <SYSC_IDLE_NO>, 785 <SYSC_IDLE_SMART>; 786 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 787 clock-names = "fck"; 788 resets = <&prm_per 1>; 789 reset-names = "rstctrl"; 790 #address-cells = <1>; 791 #size-cells = <1>; 792 ranges = <0x0 0x300000 0x80000>; 793 status = "disabled"; 794 }; 795 }; 796}; 797 798&l4_mpuss { /* 0x4b140000 */ 799 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 800 reg = <0x4b144400 0x100>, 801 <0x4b144800 0x400>; 802 reg-names = "la", "ap"; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 806 807 segment@0 { /* 0x4b140000 */ 808 compatible = "simple-bus"; 809 #address-cells = <1>; 810 #size-cells = <1>; 811 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 812 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 813 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 814 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 815 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 816 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 817 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 818 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 819 820 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 821 compatible = "ti,sysc"; 822 status = "disabled"; 823 #address-cells = <1>; 824 #size-cells = <1>; 825 ranges = <0x00000000 0x00000000 0x00001000>, 826 <0x00001000 0x00001000 0x00001000>, 827 <0x00002000 0x00002000 0x00001000>; 828 }; 829 830 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 831 compatible = "ti,sysc"; 832 status = "disabled"; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 ranges = <0x0 0x3000 0x1000>; 836 }; 837 }; 838}; 839 840&l4_per { /* 0x48000000 */ 841 compatible = "ti,am33xx-l4-per", "simple-bus"; 842 reg = <0x48000000 0x800>, 843 <0x48000800 0x800>, 844 <0x48001000 0x400>, 845 <0x48001400 0x400>, 846 <0x48001800 0x400>, 847 <0x48001c00 0x400>; 848 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 849 #address-cells = <1>; 850 #size-cells = <1>; 851 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 852 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 853 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 854 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 855 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 856 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 857 858 segment@0 { /* 0x48000000 */ 859 compatible = "simple-bus"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 863 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 864 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 865 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 866 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 867 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 868 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 869 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 870 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 871 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 872 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 873 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 874 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 875 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 876 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 877 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 878 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 879 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 880 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 881 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 882 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 883 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 884 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 885 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 886 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 887 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 888 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 889 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 890 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 891 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 892 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 893 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 894 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 895 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 896 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 897 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 898 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 899 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 900 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 901 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 902 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 903 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 904 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 905 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 906 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 907 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 908 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 909 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 910 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 911 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 912 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 913 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 914 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 915 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 916 917 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 918 compatible = "ti,sysc"; 919 status = "disabled"; 920 #address-cells = <1>; 921 #size-cells = <1>; 922 ranges = <0x0 0x8000 0x1000>; 923 }; 924 925 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 926 compatible = "ti,sysc"; 927 status = "disabled"; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges = <0x0 0x14000 0x1000>; 931 }; 932 933 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 934 compatible = "ti,sysc"; 935 status = "disabled"; 936 #address-cells = <1>; 937 #size-cells = <1>; 938 ranges = <0x0 0x16000 0x1000>; 939 }; 940 941 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 942 compatible = "ti,sysc-omap2", "ti,sysc"; 943 reg = <0x22050 0x4>, 944 <0x22054 0x4>, 945 <0x22058 0x4>; 946 reg-names = "rev", "sysc", "syss"; 947 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 948 SYSC_OMAP2_SOFTRESET | 949 SYSC_OMAP2_AUTOIDLE)>; 950 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 951 <SYSC_IDLE_NO>, 952 <SYSC_IDLE_SMART>, 953 <SYSC_IDLE_SMART_WKUP>; 954 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 955 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 956 clock-names = "fck"; 957 #address-cells = <1>; 958 #size-cells = <1>; 959 ranges = <0x0 0x22000 0x1000>; 960 961 uart1: serial@0 { 962 compatible = "ti,am3352-uart", "ti,omap3-uart"; 963 clock-frequency = <48000000>; 964 reg = <0x0 0x1000>; 965 interrupts = <73>; 966 status = "disabled"; 967 dmas = <&edma 28 0>, <&edma 29 0>; 968 dma-names = "tx", "rx"; 969 }; 970 }; 971 972 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 973 compatible = "ti,sysc-omap2", "ti,sysc"; 974 reg = <0x24050 0x4>, 975 <0x24054 0x4>, 976 <0x24058 0x4>; 977 reg-names = "rev", "sysc", "syss"; 978 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 979 SYSC_OMAP2_SOFTRESET | 980 SYSC_OMAP2_AUTOIDLE)>; 981 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 982 <SYSC_IDLE_NO>, 983 <SYSC_IDLE_SMART>, 984 <SYSC_IDLE_SMART_WKUP>; 985 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 986 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 987 clock-names = "fck"; 988 #address-cells = <1>; 989 #size-cells = <1>; 990 ranges = <0x0 0x24000 0x1000>; 991 992 uart2: serial@0 { 993 compatible = "ti,am3352-uart", "ti,omap3-uart"; 994 clock-frequency = <48000000>; 995 reg = <0x0 0x1000>; 996 interrupts = <74>; 997 status = "disabled"; 998 dmas = <&edma 30 0>, <&edma 31 0>; 999 dma-names = "tx", "rx"; 1000 }; 1001 }; 1002 1003 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 1004 compatible = "ti,sysc-omap2", "ti,sysc"; 1005 reg = <0x2a000 0x8>, 1006 <0x2a010 0x8>, 1007 <0x2a090 0x8>; 1008 reg-names = "rev", "sysc", "syss"; 1009 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1010 SYSC_OMAP2_ENAWAKEUP | 1011 SYSC_OMAP2_SOFTRESET | 1012 SYSC_OMAP2_AUTOIDLE)>; 1013 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1014 <SYSC_IDLE_NO>, 1015 <SYSC_IDLE_SMART>, 1016 <SYSC_IDLE_SMART_WKUP>; 1017 ti,syss-mask = <1>; 1018 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1019 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 1020 clock-names = "fck"; 1021 #address-cells = <1>; 1022 #size-cells = <1>; 1023 ranges = <0x0 0x2a000 0x1000>; 1024 1025 i2c1: i2c@0 { 1026 compatible = "ti,omap4-i2c"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 reg = <0x0 0x1000>; 1030 interrupts = <71>; 1031 status = "disabled"; 1032 }; 1033 }; 1034 1035 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1036 compatible = "ti,sysc-omap2", "ti,sysc"; 1037 reg = <0x30000 0x4>, 1038 <0x30110 0x4>, 1039 <0x30114 0x4>; 1040 reg-names = "rev", "sysc", "syss"; 1041 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1042 SYSC_OMAP2_SOFTRESET | 1043 SYSC_OMAP2_AUTOIDLE)>; 1044 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1045 <SYSC_IDLE_NO>, 1046 <SYSC_IDLE_SMART>; 1047 ti,syss-mask = <1>; 1048 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1049 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1050 clock-names = "fck"; 1051 #address-cells = <1>; 1052 #size-cells = <1>; 1053 ranges = <0x0 0x30000 0x1000>; 1054 1055 spi0: spi@0 { 1056 compatible = "ti,omap4-mcspi"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 reg = <0x0 0x400>; 1060 interrupts = <65>; 1061 ti,spi-num-cs = <2>; 1062 dmas = <&edma 16 0 1063 &edma 17 0 1064 &edma 18 0 1065 &edma 19 0>; 1066 dma-names = "tx0", "rx0", "tx1", "rx1"; 1067 status = "disabled"; 1068 }; 1069 }; 1070 1071 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1072 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1073 reg = <0x38000 0x4>, 1074 <0x38004 0x4>; 1075 reg-names = "rev", "sysc"; 1076 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1077 <SYSC_IDLE_NO>, 1078 <SYSC_IDLE_SMART>; 1079 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1080 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1081 clock-names = "fck"; 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 ranges = <0x0 0x38000 0x2000>, 1085 <0x46000000 0x46000000 0x400000>; 1086 1087 mcasp0: mcasp@0 { 1088 compatible = "ti,am33xx-mcasp-audio"; 1089 reg = <0x0 0x2000>, 1090 <0x46000000 0x400000>; 1091 reg-names = "mpu", "dat"; 1092 interrupts = <80>, <81>; 1093 interrupt-names = "tx", "rx"; 1094 status = "disabled"; 1095 dmas = <&edma 8 2>, 1096 <&edma 9 2>; 1097 dma-names = "tx", "rx"; 1098 }; 1099 }; 1100 1101 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1102 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1103 reg = <0x3c000 0x4>, 1104 <0x3c004 0x4>; 1105 reg-names = "rev", "sysc"; 1106 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1107 <SYSC_IDLE_NO>, 1108 <SYSC_IDLE_SMART>; 1109 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1110 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1111 clock-names = "fck"; 1112 #address-cells = <1>; 1113 #size-cells = <1>; 1114 ranges = <0x0 0x3c000 0x2000>, 1115 <0x46400000 0x46400000 0x400000>; 1116 1117 mcasp1: mcasp@0 { 1118 compatible = "ti,am33xx-mcasp-audio"; 1119 reg = <0x0 0x2000>, 1120 <0x46400000 0x400000>; 1121 reg-names = "mpu", "dat"; 1122 interrupts = <82>, <83>; 1123 interrupt-names = "tx", "rx"; 1124 status = "disabled"; 1125 dmas = <&edma 10 2>, 1126 <&edma 11 2>; 1127 dma-names = "tx", "rx"; 1128 }; 1129 }; 1130 1131 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1132 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1133 reg = <0x40000 0x4>, 1134 <0x40010 0x4>, 1135 <0x40014 0x4>; 1136 reg-names = "rev", "sysc", "syss"; 1137 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1138 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1139 <SYSC_IDLE_NO>, 1140 <SYSC_IDLE_SMART>, 1141 <SYSC_IDLE_SMART_WKUP>; 1142 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1143 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1144 clock-names = "fck"; 1145 #address-cells = <1>; 1146 #size-cells = <1>; 1147 ranges = <0x0 0x40000 0x1000>; 1148 1149 timer2: timer@0 { 1150 compatible = "ti,am335x-timer"; 1151 reg = <0x0 0x400>; 1152 interrupts = <68>; 1153 clocks = <&timer2_fck>; 1154 clock-names = "fck"; 1155 }; 1156 }; 1157 1158 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1159 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1160 reg = <0x42000 0x4>, 1161 <0x42010 0x4>, 1162 <0x42014 0x4>; 1163 reg-names = "rev", "sysc", "syss"; 1164 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1165 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1166 <SYSC_IDLE_NO>, 1167 <SYSC_IDLE_SMART>, 1168 <SYSC_IDLE_SMART_WKUP>; 1169 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1170 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1171 clock-names = "fck"; 1172 #address-cells = <1>; 1173 #size-cells = <1>; 1174 ranges = <0x0 0x42000 0x1000>; 1175 1176 timer3: timer@0 { 1177 compatible = "ti,am335x-timer"; 1178 reg = <0x0 0x400>; 1179 interrupts = <69>; 1180 clocks = <&timer3_fck>; 1181 clock-names = "fck"; 1182 }; 1183 }; 1184 1185 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1186 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1187 reg = <0x44000 0x4>, 1188 <0x44010 0x4>, 1189 <0x44014 0x4>; 1190 reg-names = "rev", "sysc", "syss"; 1191 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1192 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1193 <SYSC_IDLE_NO>, 1194 <SYSC_IDLE_SMART>, 1195 <SYSC_IDLE_SMART_WKUP>; 1196 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1197 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1198 clock-names = "fck"; 1199 #address-cells = <1>; 1200 #size-cells = <1>; 1201 ranges = <0x0 0x44000 0x1000>; 1202 1203 timer4: timer@0 { 1204 compatible = "ti,am335x-timer"; 1205 reg = <0x0 0x400>; 1206 interrupts = <92>; 1207 ti,timer-pwm; 1208 clocks = <&timer4_fck>; 1209 clock-names = "fck"; 1210 }; 1211 }; 1212 1213 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1214 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1215 reg = <0x46000 0x4>, 1216 <0x46010 0x4>, 1217 <0x46014 0x4>; 1218 reg-names = "rev", "sysc", "syss"; 1219 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1220 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1221 <SYSC_IDLE_NO>, 1222 <SYSC_IDLE_SMART>, 1223 <SYSC_IDLE_SMART_WKUP>; 1224 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1225 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1226 clock-names = "fck"; 1227 #address-cells = <1>; 1228 #size-cells = <1>; 1229 ranges = <0x0 0x46000 0x1000>; 1230 1231 timer5: timer@0 { 1232 compatible = "ti,am335x-timer"; 1233 reg = <0x0 0x400>; 1234 interrupts = <93>; 1235 ti,timer-pwm; 1236 clocks = <&timer5_fck>; 1237 clock-names = "fck"; 1238 }; 1239 }; 1240 1241 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1242 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1243 reg = <0x48000 0x4>, 1244 <0x48010 0x4>, 1245 <0x48014 0x4>; 1246 reg-names = "rev", "sysc", "syss"; 1247 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1248 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1249 <SYSC_IDLE_NO>, 1250 <SYSC_IDLE_SMART>, 1251 <SYSC_IDLE_SMART_WKUP>; 1252 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1253 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1254 clock-names = "fck"; 1255 #address-cells = <1>; 1256 #size-cells = <1>; 1257 ranges = <0x0 0x48000 0x1000>; 1258 1259 timer6: timer@0 { 1260 compatible = "ti,am335x-timer"; 1261 reg = <0x0 0x400>; 1262 interrupts = <94>; 1263 ti,timer-pwm; 1264 clocks = <&timer6_fck>; 1265 clock-names = "fck"; 1266 }; 1267 }; 1268 1269 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1270 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1271 reg = <0x4a000 0x4>, 1272 <0x4a010 0x4>, 1273 <0x4a014 0x4>; 1274 reg-names = "rev", "sysc", "syss"; 1275 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1276 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1277 <SYSC_IDLE_NO>, 1278 <SYSC_IDLE_SMART>, 1279 <SYSC_IDLE_SMART_WKUP>; 1280 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1281 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1282 clock-names = "fck"; 1283 #address-cells = <1>; 1284 #size-cells = <1>; 1285 ranges = <0x0 0x4a000 0x1000>; 1286 1287 timer7: timer@0 { 1288 compatible = "ti,am335x-timer"; 1289 reg = <0x0 0x400>; 1290 interrupts = <95>; 1291 ti,timer-pwm; 1292 clocks = <&timer7_fck>; 1293 clock-names = "fck"; 1294 }; 1295 }; 1296 1297 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1298 compatible = "ti,sysc-omap2", "ti,sysc"; 1299 reg = <0x4c000 0x4>, 1300 <0x4c010 0x4>, 1301 <0x4c114 0x4>; 1302 reg-names = "rev", "sysc", "syss"; 1303 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1304 SYSC_OMAP2_SOFTRESET | 1305 SYSC_OMAP2_AUTOIDLE)>; 1306 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1307 <SYSC_IDLE_NO>, 1308 <SYSC_IDLE_SMART>, 1309 <SYSC_IDLE_SMART_WKUP>; 1310 ti,syss-mask = <1>; 1311 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1312 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1313 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1314 clock-names = "fck", "dbclk"; 1315 #address-cells = <1>; 1316 #size-cells = <1>; 1317 ranges = <0x0 0x4c000 0x1000>; 1318 1319 gpio1: gpio@0 { 1320 compatible = "ti,omap4-gpio"; 1321 gpio-ranges = <&am33xx_pinmux 0 0 8>, 1322 <&am33xx_pinmux 8 90 4>, 1323 <&am33xx_pinmux 12 12 16>, 1324 <&am33xx_pinmux 28 30 4>; 1325 gpio-controller; 1326 #gpio-cells = <2>; 1327 interrupt-controller; 1328 #interrupt-cells = <2>; 1329 reg = <0x0 0x1000>; 1330 interrupts = <98>; 1331 }; 1332 }; 1333 1334 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1335 compatible = "ti,sysc"; 1336 status = "disabled"; 1337 #address-cells = <1>; 1338 #size-cells = <1>; 1339 ranges = <0x0 0x50000 0x2000>; 1340 }; 1341 1342 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1343 compatible = "ti,sysc-omap2", "ti,sysc"; 1344 reg = <0x602fc 0x4>, 1345 <0x60110 0x4>, 1346 <0x60114 0x4>; 1347 reg-names = "rev", "sysc", "syss"; 1348 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1349 SYSC_OMAP2_ENAWAKEUP | 1350 SYSC_OMAP2_SOFTRESET | 1351 SYSC_OMAP2_AUTOIDLE)>; 1352 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1353 <SYSC_IDLE_NO>, 1354 <SYSC_IDLE_SMART>; 1355 ti,syss-mask = <1>; 1356 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1357 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1358 clock-names = "fck"; 1359 #address-cells = <1>; 1360 #size-cells = <1>; 1361 ranges = <0x0 0x60000 0x1000>; 1362 1363 mmc1: mmc@0 { 1364 compatible = "ti,am335-sdhci"; 1365 ti,needs-special-reset; 1366 dmas = <&edma_xbar 24 0 0 1367 &edma_xbar 25 0 0>; 1368 dma-names = "tx", "rx"; 1369 interrupts = <64>; 1370 reg = <0x0 0x1000>; 1371 status = "disabled"; 1372 }; 1373 }; 1374 1375 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1376 compatible = "ti,sysc-omap2", "ti,sysc"; 1377 reg = <0x80000 0x4>, 1378 <0x80010 0x4>, 1379 <0x80014 0x4>; 1380 reg-names = "rev", "sysc", "syss"; 1381 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1382 SYSC_OMAP2_SOFTRESET | 1383 SYSC_OMAP2_AUTOIDLE)>; 1384 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1385 <SYSC_IDLE_NO>, 1386 <SYSC_IDLE_SMART>; 1387 ti,syss-mask = <1>; 1388 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1389 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1390 clock-names = "fck"; 1391 #address-cells = <1>; 1392 #size-cells = <1>; 1393 ranges = <0x0 0x80000 0x10000>; 1394 1395 elm: elm@0 { 1396 compatible = "ti,am3352-elm"; 1397 reg = <0x0 0x2000>; 1398 interrupts = <4>; 1399 status = "disabled"; 1400 }; 1401 }; 1402 1403 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1404 compatible = "ti,sysc"; 1405 status = "disabled"; 1406 #address-cells = <1>; 1407 #size-cells = <1>; 1408 ranges = <0x0 0xa0000 0x10000>; 1409 }; 1410 1411 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1412 compatible = "ti,sysc-omap4", "ti,sysc"; 1413 reg = <0xc8000 0x4>, 1414 <0xc8010 0x4>; 1415 reg-names = "rev", "sysc"; 1416 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1417 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1418 <SYSC_IDLE_NO>, 1419 <SYSC_IDLE_SMART>; 1420 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1421 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1422 clock-names = "fck"; 1423 #address-cells = <1>; 1424 #size-cells = <1>; 1425 ranges = <0x0 0xc8000 0x1000>; 1426 1427 mailbox: mailbox@0 { 1428 compatible = "ti,omap4-mailbox"; 1429 reg = <0x0 0x200>; 1430 interrupts = <77>; 1431 #mbox-cells = <1>; 1432 ti,mbox-num-users = <4>; 1433 ti,mbox-num-fifos = <8>; 1434 mbox_wkupm3: wkup_m3 { 1435 ti,mbox-send-noirq; 1436 ti,mbox-tx = <0 0 0>; 1437 ti,mbox-rx = <0 0 3>; 1438 }; 1439 }; 1440 }; 1441 1442 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1443 compatible = "ti,sysc-omap2", "ti,sysc"; 1444 reg = <0xca000 0x4>, 1445 <0xca010 0x4>, 1446 <0xca014 0x4>; 1447 reg-names = "rev", "sysc", "syss"; 1448 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1449 SYSC_OMAP2_ENAWAKEUP | 1450 SYSC_OMAP2_SOFTRESET | 1451 SYSC_OMAP2_AUTOIDLE)>; 1452 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1453 <SYSC_IDLE_NO>, 1454 <SYSC_IDLE_SMART>; 1455 ti,syss-mask = <1>; 1456 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1457 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1458 clock-names = "fck"; 1459 #address-cells = <1>; 1460 #size-cells = <1>; 1461 ranges = <0x0 0xca000 0x1000>; 1462 1463 hwspinlock: spinlock@0 { 1464 compatible = "ti,omap4-hwspinlock"; 1465 reg = <0x0 0x1000>; 1466 #hwlock-cells = <1>; 1467 }; 1468 }; 1469 1470 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1471 compatible = "ti,sysc"; 1472 status = "disabled"; 1473 #address-cells = <1>; 1474 #size-cells = <1>; 1475 ranges = <0x0 0xcc000 0x1000>; 1476 }; 1477 }; 1478 1479 segment@100000 { /* 0x48100000 */ 1480 compatible = "simple-bus"; 1481 #address-cells = <1>; 1482 #size-cells = <1>; 1483 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1484 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1485 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1486 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1487 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1488 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1489 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1490 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1491 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1492 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1493 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1494 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1495 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1496 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1497 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1498 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1499 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1500 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1501 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1502 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1503 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1504 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1505 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1506 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1507 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1508 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1509 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1510 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1511 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1512 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1513 1514 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1515 compatible = "ti,sysc"; 1516 status = "disabled"; 1517 #address-cells = <1>; 1518 #size-cells = <1>; 1519 ranges = <0x0 0x8c000 0x1000>; 1520 }; 1521 1522 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1523 compatible = "ti,sysc"; 1524 status = "disabled"; 1525 #address-cells = <1>; 1526 #size-cells = <1>; 1527 ranges = <0x0 0x8e000 0x1000>; 1528 }; 1529 1530 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1531 compatible = "ti,sysc-omap2", "ti,sysc"; 1532 reg = <0x9c000 0x8>, 1533 <0x9c010 0x8>, 1534 <0x9c090 0x8>; 1535 reg-names = "rev", "sysc", "syss"; 1536 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1537 SYSC_OMAP2_ENAWAKEUP | 1538 SYSC_OMAP2_SOFTRESET | 1539 SYSC_OMAP2_AUTOIDLE)>; 1540 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1541 <SYSC_IDLE_NO>, 1542 <SYSC_IDLE_SMART>, 1543 <SYSC_IDLE_SMART_WKUP>; 1544 ti,syss-mask = <1>; 1545 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1546 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1547 clock-names = "fck"; 1548 #address-cells = <1>; 1549 #size-cells = <1>; 1550 ranges = <0x0 0x9c000 0x1000>; 1551 1552 i2c2: i2c@0 { 1553 compatible = "ti,omap4-i2c"; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 reg = <0x0 0x1000>; 1557 interrupts = <30>; 1558 status = "disabled"; 1559 }; 1560 }; 1561 1562 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1563 compatible = "ti,sysc-omap2", "ti,sysc"; 1564 reg = <0xa0000 0x4>, 1565 <0xa0110 0x4>, 1566 <0xa0114 0x4>; 1567 reg-names = "rev", "sysc", "syss"; 1568 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1569 SYSC_OMAP2_SOFTRESET | 1570 SYSC_OMAP2_AUTOIDLE)>; 1571 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1572 <SYSC_IDLE_NO>, 1573 <SYSC_IDLE_SMART>; 1574 ti,syss-mask = <1>; 1575 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1576 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1577 clock-names = "fck"; 1578 #address-cells = <1>; 1579 #size-cells = <1>; 1580 ranges = <0x0 0xa0000 0x1000>; 1581 1582 spi1: spi@0 { 1583 compatible = "ti,omap4-mcspi"; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 reg = <0x0 0x400>; 1587 interrupts = <125>; 1588 ti,spi-num-cs = <2>; 1589 dmas = <&edma 42 0 1590 &edma 43 0 1591 &edma 44 0 1592 &edma 45 0>; 1593 dma-names = "tx0", "rx0", "tx1", "rx1"; 1594 status = "disabled"; 1595 }; 1596 }; 1597 1598 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1599 compatible = "ti,sysc"; 1600 status = "disabled"; 1601 #address-cells = <1>; 1602 #size-cells = <1>; 1603 ranges = <0x0 0xa2000 0x1000>; 1604 }; 1605 1606 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1607 compatible = "ti,sysc"; 1608 status = "disabled"; 1609 #address-cells = <1>; 1610 #size-cells = <1>; 1611 ranges = <0x0 0xa4000 0x1000>; 1612 }; 1613 1614 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1615 compatible = "ti,sysc-omap2", "ti,sysc"; 1616 reg = <0xa6050 0x4>, 1617 <0xa6054 0x4>, 1618 <0xa6058 0x4>; 1619 reg-names = "rev", "sysc", "syss"; 1620 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1621 SYSC_OMAP2_SOFTRESET | 1622 SYSC_OMAP2_AUTOIDLE)>; 1623 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1624 <SYSC_IDLE_NO>, 1625 <SYSC_IDLE_SMART>, 1626 <SYSC_IDLE_SMART_WKUP>; 1627 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1628 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1629 clock-names = "fck"; 1630 #address-cells = <1>; 1631 #size-cells = <1>; 1632 ranges = <0x0 0xa6000 0x1000>; 1633 1634 uart3: serial@0 { 1635 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1636 clock-frequency = <48000000>; 1637 reg = <0x0 0x1000>; 1638 interrupts = <44>; 1639 status = "disabled"; 1640 }; 1641 }; 1642 1643 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1644 compatible = "ti,sysc-omap2", "ti,sysc"; 1645 reg = <0xa8050 0x4>, 1646 <0xa8054 0x4>, 1647 <0xa8058 0x4>; 1648 reg-names = "rev", "sysc", "syss"; 1649 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1650 SYSC_OMAP2_SOFTRESET | 1651 SYSC_OMAP2_AUTOIDLE)>; 1652 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1653 <SYSC_IDLE_NO>, 1654 <SYSC_IDLE_SMART>, 1655 <SYSC_IDLE_SMART_WKUP>; 1656 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1657 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1658 clock-names = "fck"; 1659 #address-cells = <1>; 1660 #size-cells = <1>; 1661 ranges = <0x0 0xa8000 0x1000>; 1662 1663 uart4: serial@0 { 1664 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1665 clock-frequency = <48000000>; 1666 reg = <0x0 0x1000>; 1667 interrupts = <45>; 1668 status = "disabled"; 1669 }; 1670 }; 1671 1672 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1673 compatible = "ti,sysc-omap2", "ti,sysc"; 1674 reg = <0xaa050 0x4>, 1675 <0xaa054 0x4>, 1676 <0xaa058 0x4>; 1677 reg-names = "rev", "sysc", "syss"; 1678 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1679 SYSC_OMAP2_SOFTRESET | 1680 SYSC_OMAP2_AUTOIDLE)>; 1681 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1682 <SYSC_IDLE_NO>, 1683 <SYSC_IDLE_SMART>, 1684 <SYSC_IDLE_SMART_WKUP>; 1685 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1686 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1687 clock-names = "fck"; 1688 #address-cells = <1>; 1689 #size-cells = <1>; 1690 ranges = <0x0 0xaa000 0x1000>; 1691 1692 uart5: serial@0 { 1693 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1694 clock-frequency = <48000000>; 1695 reg = <0x0 0x1000>; 1696 interrupts = <46>; 1697 status = "disabled"; 1698 }; 1699 }; 1700 1701 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1702 compatible = "ti,sysc-omap2", "ti,sysc"; 1703 reg = <0xac000 0x4>, 1704 <0xac010 0x4>, 1705 <0xac114 0x4>; 1706 reg-names = "rev", "sysc", "syss"; 1707 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1708 SYSC_OMAP2_SOFTRESET | 1709 SYSC_OMAP2_AUTOIDLE)>; 1710 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1711 <SYSC_IDLE_NO>, 1712 <SYSC_IDLE_SMART>, 1713 <SYSC_IDLE_SMART_WKUP>; 1714 ti,syss-mask = <1>; 1715 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1716 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1717 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1718 clock-names = "fck", "dbclk"; 1719 #address-cells = <1>; 1720 #size-cells = <1>; 1721 ranges = <0x0 0xac000 0x1000>; 1722 1723 gpio2: gpio@0 { 1724 compatible = "ti,omap4-gpio"; 1725 gpio-ranges = <&am33xx_pinmux 0 34 18>, 1726 <&am33xx_pinmux 18 77 4>, 1727 <&am33xx_pinmux 22 56 10>; 1728 gpio-controller; 1729 #gpio-cells = <2>; 1730 interrupt-controller; 1731 #interrupt-cells = <2>; 1732 reg = <0x0 0x1000>; 1733 interrupts = <32>; 1734 }; 1735 }; 1736 1737 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1738 compatible = "ti,sysc-omap2", "ti,sysc"; 1739 reg = <0xae000 0x4>, 1740 <0xae010 0x4>, 1741 <0xae114 0x4>; 1742 reg-names = "rev", "sysc", "syss"; 1743 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1744 SYSC_OMAP2_SOFTRESET | 1745 SYSC_OMAP2_AUTOIDLE)>; 1746 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1747 <SYSC_IDLE_NO>, 1748 <SYSC_IDLE_SMART>, 1749 <SYSC_IDLE_SMART_WKUP>; 1750 ti,syss-mask = <1>; 1751 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1752 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1753 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1754 clock-names = "fck", "dbclk"; 1755 #address-cells = <1>; 1756 #size-cells = <1>; 1757 ranges = <0x0 0xae000 0x1000>; 1758 1759 gpio3: gpio@0 { 1760 compatible = "ti,omap4-gpio"; 1761 gpio-ranges = <&am33xx_pinmux 0 66 5>, 1762 <&am33xx_pinmux 5 98 2>, 1763 <&am33xx_pinmux 7 75 2>, 1764 <&am33xx_pinmux 13 141 1>, 1765 <&am33xx_pinmux 14 100 8>; 1766 gpio-controller; 1767 #gpio-cells = <2>; 1768 interrupt-controller; 1769 #interrupt-cells = <2>; 1770 reg = <0x0 0x1000>; 1771 interrupts = <62>; 1772 }; 1773 }; 1774 1775 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1776 compatible = "ti,sysc"; 1777 status = "disabled"; 1778 #address-cells = <1>; 1779 #size-cells = <1>; 1780 ranges = <0x0 0xb0000 0x10000>; 1781 }; 1782 1783 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1784 compatible = "ti,sysc-omap4", "ti,sysc"; 1785 reg = <0xcc020 0x4>; 1786 reg-names = "rev"; 1787 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1788 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1789 <&dcan0_fck>; 1790 clock-names = "fck", "osc"; 1791 #address-cells = <1>; 1792 #size-cells = <1>; 1793 ranges = <0x0 0xcc000 0x2000>; 1794 1795 dcan0: can@0 { 1796 compatible = "ti,am3352-d_can"; 1797 reg = <0x0 0x2000>; 1798 clocks = <&dcan0_fck>; 1799 clock-names = "fck"; 1800 syscon-raminit = <&scm_conf 0x644 0>; 1801 interrupts = <52>; 1802 status = "disabled"; 1803 }; 1804 }; 1805 1806 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1807 compatible = "ti,sysc-omap4", "ti,sysc"; 1808 reg = <0xd0020 0x4>; 1809 reg-names = "rev"; 1810 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1811 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1812 <&dcan1_fck>; 1813 clock-names = "fck", "osc"; 1814 #address-cells = <1>; 1815 #size-cells = <1>; 1816 ranges = <0x0 0xd0000 0x2000>; 1817 1818 dcan1: can@0 { 1819 compatible = "ti,am3352-d_can"; 1820 reg = <0x0 0x2000>; 1821 clocks = <&dcan1_fck>; 1822 clock-names = "fck"; 1823 syscon-raminit = <&scm_conf 0x644 1>; 1824 interrupts = <55>; 1825 status = "disabled"; 1826 }; 1827 }; 1828 1829 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1830 compatible = "ti,sysc-omap2", "ti,sysc"; 1831 reg = <0xd82fc 0x4>, 1832 <0xd8110 0x4>, 1833 <0xd8114 0x4>; 1834 reg-names = "rev", "sysc", "syss"; 1835 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1836 SYSC_OMAP2_ENAWAKEUP | 1837 SYSC_OMAP2_SOFTRESET | 1838 SYSC_OMAP2_AUTOIDLE)>; 1839 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1840 <SYSC_IDLE_NO>, 1841 <SYSC_IDLE_SMART>; 1842 ti,syss-mask = <1>; 1843 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1844 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1845 clock-names = "fck"; 1846 #address-cells = <1>; 1847 #size-cells = <1>; 1848 ranges = <0x0 0xd8000 0x1000>; 1849 1850 mmc2: mmc@0 { 1851 compatible = "ti,am335-sdhci"; 1852 ti,needs-special-reset; 1853 dmas = <&edma 2 0 1854 &edma 3 0>; 1855 dma-names = "tx", "rx"; 1856 interrupts = <28>; 1857 reg = <0x0 0x1000>; 1858 status = "disabled"; 1859 }; 1860 }; 1861 }; 1862 1863 segment@200000 { /* 0x48200000 */ 1864 compatible = "simple-bus"; 1865 #address-cells = <1>; 1866 #size-cells = <1>; 1867 }; 1868 1869 segment@300000 { /* 0x48300000 */ 1870 compatible = "simple-bus"; 1871 #address-cells = <1>; 1872 #size-cells = <1>; 1873 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 1874 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 1875 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 1876 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 1877 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 1878 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 1879 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 1880 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 1881 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 1882 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 1883 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 1884 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 1885 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 1886 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 1887 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 1888 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 1889 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 1890 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 1891 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 1892 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 1893 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 1894 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 1895 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 1896 1897 target-module@0 { /* 0x48300000, ap 66 48.0 */ 1898 compatible = "ti,sysc-omap4", "ti,sysc"; 1899 reg = <0x0 0x4>, 1900 <0x4 0x4>; 1901 reg-names = "rev", "sysc"; 1902 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1903 <SYSC_IDLE_NO>, 1904 <SYSC_IDLE_SMART>, 1905 <SYSC_IDLE_SMART_WKUP>; 1906 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1907 <SYSC_IDLE_NO>, 1908 <SYSC_IDLE_SMART>, 1909 <SYSC_IDLE_SMART_WKUP>; 1910 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1911 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 1912 clock-names = "fck"; 1913 #address-cells = <1>; 1914 #size-cells = <1>; 1915 ranges = <0x0 0x0 0x1000>; 1916 1917 epwmss0: epwmss@0 { 1918 compatible = "ti,am33xx-pwmss"; 1919 reg = <0x0 0x10>; 1920 #address-cells = <1>; 1921 #size-cells = <1>; 1922 status = "disabled"; 1923 ranges = <0 0 0x1000>; 1924 1925 ecap0: ecap@100 { 1926 compatible = "ti,am3352-ecap", 1927 "ti,am33xx-ecap"; 1928 #pwm-cells = <3>; 1929 reg = <0x100 0x80>; 1930 clocks = <&l4ls_gclk>; 1931 clock-names = "fck"; 1932 interrupts = <31>; 1933 interrupt-names = "ecap0"; 1934 status = "disabled"; 1935 }; 1936 1937 ehrpwm0: pwm@200 { 1938 compatible = "ti,am3352-ehrpwm", 1939 "ti,am33xx-ehrpwm"; 1940 #pwm-cells = <3>; 1941 reg = <0x200 0x80>; 1942 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 1943 clock-names = "tbclk", "fck"; 1944 status = "disabled"; 1945 }; 1946 }; 1947 }; 1948 1949 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 1950 compatible = "ti,sysc-omap4", "ti,sysc"; 1951 reg = <0x2000 0x4>, 1952 <0x2004 0x4>; 1953 reg-names = "rev", "sysc"; 1954 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1955 <SYSC_IDLE_NO>, 1956 <SYSC_IDLE_SMART>, 1957 <SYSC_IDLE_SMART_WKUP>; 1958 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1959 <SYSC_IDLE_NO>, 1960 <SYSC_IDLE_SMART>, 1961 <SYSC_IDLE_SMART_WKUP>; 1962 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1963 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 1964 clock-names = "fck"; 1965 #address-cells = <1>; 1966 #size-cells = <1>; 1967 ranges = <0x0 0x2000 0x1000>; 1968 1969 epwmss1: epwmss@0 { 1970 compatible = "ti,am33xx-pwmss"; 1971 reg = <0x0 0x10>; 1972 #address-cells = <1>; 1973 #size-cells = <1>; 1974 status = "disabled"; 1975 ranges = <0 0 0x1000>; 1976 1977 ecap1: ecap@100 { 1978 compatible = "ti,am3352-ecap", 1979 "ti,am33xx-ecap"; 1980 #pwm-cells = <3>; 1981 reg = <0x100 0x80>; 1982 clocks = <&l4ls_gclk>; 1983 clock-names = "fck"; 1984 interrupts = <47>; 1985 interrupt-names = "ecap1"; 1986 status = "disabled"; 1987 }; 1988 1989 ehrpwm1: pwm@200 { 1990 compatible = "ti,am3352-ehrpwm", 1991 "ti,am33xx-ehrpwm"; 1992 #pwm-cells = <3>; 1993 reg = <0x200 0x80>; 1994 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 1995 clock-names = "tbclk", "fck"; 1996 status = "disabled"; 1997 }; 1998 }; 1999 }; 2000 2001 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 2002 compatible = "ti,sysc-omap4", "ti,sysc"; 2003 reg = <0x4000 0x4>, 2004 <0x4004 0x4>; 2005 reg-names = "rev", "sysc"; 2006 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2007 <SYSC_IDLE_NO>, 2008 <SYSC_IDLE_SMART>, 2009 <SYSC_IDLE_SMART_WKUP>; 2010 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2011 <SYSC_IDLE_NO>, 2012 <SYSC_IDLE_SMART>, 2013 <SYSC_IDLE_SMART_WKUP>; 2014 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2015 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 2016 clock-names = "fck"; 2017 #address-cells = <1>; 2018 #size-cells = <1>; 2019 ranges = <0x0 0x4000 0x1000>; 2020 2021 epwmss2: epwmss@0 { 2022 compatible = "ti,am33xx-pwmss"; 2023 reg = <0x0 0x10>; 2024 #address-cells = <1>; 2025 #size-cells = <1>; 2026 status = "disabled"; 2027 ranges = <0 0 0x1000>; 2028 2029 ecap2: ecap@100 { 2030 compatible = "ti,am3352-ecap", 2031 "ti,am33xx-ecap"; 2032 #pwm-cells = <3>; 2033 reg = <0x100 0x80>; 2034 clocks = <&l4ls_gclk>; 2035 clock-names = "fck"; 2036 interrupts = <61>; 2037 interrupt-names = "ecap2"; 2038 status = "disabled"; 2039 }; 2040 2041 ehrpwm2: pwm@200 { 2042 compatible = "ti,am3352-ehrpwm", 2043 "ti,am33xx-ehrpwm"; 2044 #pwm-cells = <3>; 2045 reg = <0x200 0x80>; 2046 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2047 clock-names = "tbclk", "fck"; 2048 status = "disabled"; 2049 }; 2050 }; 2051 }; 2052 2053 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2054 compatible = "ti,sysc-omap4", "ti,sysc"; 2055 reg = <0xe000 0x4>, 2056 <0xe054 0x4>; 2057 reg-names = "rev", "sysc"; 2058 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2059 <SYSC_IDLE_NO>, 2060 <SYSC_IDLE_SMART>; 2061 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2062 <SYSC_IDLE_NO>, 2063 <SYSC_IDLE_SMART>; 2064 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2065 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2066 clock-names = "fck"; 2067 #address-cells = <1>; 2068 #size-cells = <1>; 2069 ranges = <0x0 0xe000 0x1000>; 2070 2071 lcdc: lcdc@0 { 2072 compatible = "ti,am33xx-tilcdc"; 2073 reg = <0x0 0x1000>; 2074 interrupts = <36>; 2075 status = "disabled"; 2076 }; 2077 }; 2078 2079 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2080 compatible = "ti,sysc-omap2", "ti,sysc"; 2081 reg = <0x11fe0 0x4>, 2082 <0x11fe4 0x4>; 2083 reg-names = "rev", "sysc"; 2084 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2085 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2086 <SYSC_IDLE_NO>; 2087 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2088 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2089 clock-names = "fck"; 2090 #address-cells = <1>; 2091 #size-cells = <1>; 2092 ranges = <0x0 0x10000 0x2000>; 2093 2094 rng: rng@0 { 2095 compatible = "ti,omap4-rng"; 2096 reg = <0x0 0x2000>; 2097 interrupts = <111>; 2098 }; 2099 }; 2100 2101 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2102 compatible = "ti,sysc"; 2103 status = "disabled"; 2104 #address-cells = <1>; 2105 #size-cells = <1>; 2106 ranges = <0x0 0x13000 0x1000>; 2107 }; 2108 2109 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2110 compatible = "ti,sysc"; 2111 status = "disabled"; 2112 #address-cells = <1>; 2113 #size-cells = <1>; 2114 ranges = <0x00000000 0x00015000 0x00001000>, 2115 <0x00001000 0x00016000 0x00001000>; 2116 }; 2117 2118 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2119 compatible = "ti,sysc"; 2120 status = "disabled"; 2121 #address-cells = <1>; 2122 #size-cells = <1>; 2123 ranges = <0x0 0x18000 0x4000>; 2124 }; 2125 2126 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2127 compatible = "ti,sysc"; 2128 status = "disabled"; 2129 #address-cells = <1>; 2130 #size-cells = <1>; 2131 ranges = <0x0 0x20000 0x1000>; 2132 }; 2133 2134 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2135 compatible = "ti,sysc"; 2136 status = "disabled"; 2137 #address-cells = <1>; 2138 #size-cells = <1>; 2139 ranges = <0x0 0x22000 0x1000>; 2140 }; 2141 2142 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2143 compatible = "ti,sysc"; 2144 status = "disabled"; 2145 #address-cells = <1>; 2146 #size-cells = <1>; 2147 ranges = <0x0 0x24000 0x1000>; 2148 }; 2149 }; 2150}; 2151 2152