1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56//===----------------------------------------------------------------------===// 57// FPStack pattern fragments 58//===----------------------------------------------------------------------===// 59 60def fpimm0 : FPImmLeaf<fAny, [{ 61 return Imm.isExactlyValue(+0.0); 62}]>; 63 64def fpimmneg0 : FPImmLeaf<fAny, [{ 65 return Imm.isExactlyValue(-0.0); 66}]>; 67 68def fpimm1 : FPImmLeaf<fAny, [{ 69 return Imm.isExactlyValue(+1.0); 70}]>; 71 72def fpimmneg1 : FPImmLeaf<fAny, [{ 73 return Imm.isExactlyValue(-1.0); 74}]>; 75 76// Some 'special' instructions - expanded after instruction selection. 77let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96} 97 98// All FP Stack operations are represented with four instructions here. The 99// first three instructions, generated by the instruction selector, use "RFP32" 100// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101// 64-bit or 80-bit floating point values. These sizes apply to the values, 102// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103// copied to each other without losing information. These instructions are all 104// pseudo instructions and use the "_Fp" suffix. 105// In some cases there are additional variants with a mixture of different 106// register sizes. 107// The second instruction is defined with FPI, which is the actual instruction 108// emitted by the assembler. These use "RST" registers, although frequently 109// the actual register(s) used are implicit. These are always 80 bits. 110// The FP stackifier pass converts one to the other after register allocation 111// occurs. 112// 113// Note that the FpI instruction should have instruction selection info (e.g. 114// a pattern) and the FPI instruction should have emission info (e.g. opcode 115// encoding and asm printing info). 116 117// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 118// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 119// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 120// f80 instructions cannot use SSE and use neither of these. 121class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 122 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 123class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 124 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 125 126// Factoring for arithmetic. 127multiclass FPBinary_rr<SDNode OpNode> { 128// Register op register -> register 129// These are separated out because they have no reversed form. 130def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 132def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 134def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 136} 137// The FopST0 series are not included here because of the irregularities 138// in where the 'r' goes in assembly output. 139// These instructions cannot address 80-bit memory. 140multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 141 bit Forward = 1> { 142let mayLoad = 1, hasSideEffects = 1 in { 143// ST(0) = ST(0) + [mem] 144def _Fp32m : FpIf32<(outs RFP32:$dst), 145 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 146 [!if(Forward, 147 (set RFP32:$dst, 148 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 149 (set RFP32:$dst, 150 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 151def _Fp64m : FpIf64<(outs RFP64:$dst), 152 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 153 [!if(Forward, 154 (set RFP64:$dst, 155 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 156 (set RFP64:$dst, 157 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 158def _Fp64m32: FpIf64<(outs RFP64:$dst), 159 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 160 [!if(Forward, 161 (set RFP64:$dst, 162 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 163 (set RFP64:$dst, 164 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 165def _Fp80m32: FpI_<(outs RFP80:$dst), 166 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 167 [!if(Forward, 168 (set RFP80:$dst, 169 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 170 (set RFP80:$dst, 171 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 172def _Fp80m64: FpI_<(outs RFP80:$dst), 173 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 174 [!if(Forward, 175 (set RFP80:$dst, 176 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 177 (set RFP80:$dst, 178 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 179def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 180 !strconcat("f", asmstring, "{s}\t$src")>; 181def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 182 !strconcat("f", asmstring, "{l}\t$src")>; 183// ST(0) = ST(0) + [memint] 184def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 185 OneArgFPRW, 186 [!if(Forward, 187 (set RFP32:$dst, 188 (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), 189 (set RFP32:$dst, 190 (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; 191def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 192 OneArgFPRW, 193 [!if(Forward, 194 (set RFP32:$dst, 195 (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), 196 (set RFP32:$dst, 197 (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; 198def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 199 OneArgFPRW, 200 [!if(Forward, 201 (set RFP64:$dst, 202 (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), 203 (set RFP64:$dst, 204 (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; 205def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 206 OneArgFPRW, 207 [!if(Forward, 208 (set RFP64:$dst, 209 (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), 210 (set RFP64:$dst, 211 (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; 212def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 213 OneArgFPRW, 214 [!if(Forward, 215 (set RFP80:$dst, 216 (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), 217 (set RFP80:$dst, 218 (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; 219def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 220 OneArgFPRW, 221 [!if(Forward, 222 (set RFP80:$dst, 223 (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), 224 (set RFP80:$dst, 225 (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; 226def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 227 !strconcat("fi", asmstring, "{s}\t$src")>; 228def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 229 !strconcat("fi", asmstring, "{l}\t$src")>; 230} // mayLoad = 1, hasSideEffects = 1 231} 232 233let Defs = [FPSW], Uses = [FPCW] in { 234// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 235// resources. 236let hasNoSchedulingInfo = 1 in { 237defm ADD : FPBinary_rr<fadd>; 238defm SUB : FPBinary_rr<fsub>; 239defm MUL : FPBinary_rr<fmul>; 240defm DIV : FPBinary_rr<fdiv>; 241} 242 243// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 244let SchedRW = [WriteFAddLd] in { 245defm ADD : FPBinary<fadd, MRM0m, "add">; 246defm SUB : FPBinary<fsub, MRM4m, "sub">; 247defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>; 248} 249 250let SchedRW = [WriteFMulLd] in { 251defm MUL : FPBinary<fmul, MRM1m, "mul">; 252} 253 254let SchedRW = [WriteFDivLd] in { 255defm DIV : FPBinary<fdiv, MRM6m, "div">; 256defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; 257} 258} // Defs = [FPSW] 259 260class FPST0rInst<Format fp, string asm> 261 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 262class FPrST0Inst<Format fp, string asm> 263 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 264class FPrST0PInst<Format fp, string asm> 265 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 266 267// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 268// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 269// we have to put some 'r's in and take them out of weird places. 270let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in { 271def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 272def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 273def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 274def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 275def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 276def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 277def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 278def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 279def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 280} // SchedRW 281let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in { 282def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 283def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 284} // SchedRW 285let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in { 286def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 287def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 288def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 289} // SchedRW 290let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in { 291def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 292def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 293def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 294def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 295def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 296def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 297} // SchedRW 298 299// Unary operations. 300multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 301def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 302 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 303def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 304 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 305def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 306 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 307def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 308} 309 310let Defs = [FPSW], Uses = [FPCW] in { 311 312let SchedRW = [WriteFSign] in { 313defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 314defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 315} 316 317let SchedRW = [WriteFSqrt80] in 318defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 319 320let SchedRW = [WriteMicrocoded] in { 321defm SIN : FPUnary<fsin, MRM_FE, "fsin">; 322defm COS : FPUnary<fcos, MRM_FF, "fcos">; 323} 324 325let SchedRW = [WriteFCom] in { 326let hasSideEffects = 0 in { 327def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 328def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 329def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 330} // hasSideEffects 331 332def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 333} // SchedRW 334} // Defs = [FPSW] 335 336// Versions of FP instructions that take a single memory operand. Added for the 337// disassembler; remove as they are included with patterns elsewhere. 338let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in { 339def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 340def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 341 342def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 343def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 344 345def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 346def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 347 348def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 349def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 350} // SchedRW 351 352let SchedRW = [WriteMicrocoded] in { 353def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 354def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 355 356def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 357def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 358def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 359 360def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 361def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 362} // SchedRW 363 364// Floating point cmovs. 365class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 366 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 367class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 368 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 369 370multiclass FPCMov<PatLeaf cc> { 371 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 372 CondMovFP, 373 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 374 cc, EFLAGS))]>; 375 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 376 CondMovFP, 377 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 378 cc, EFLAGS))]>; 379 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 380 CondMovFP, 381 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 382 cc, EFLAGS))]>, 383 Requires<[HasCMov]>; 384} 385 386let Defs = [FPSW] in { 387let SchedRW = [WriteFCMOV] in { 388let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 389defm CMOVB : FPCMov<X86_COND_B>; 390defm CMOVBE : FPCMov<X86_COND_BE>; 391defm CMOVE : FPCMov<X86_COND_E>; 392defm CMOVP : FPCMov<X86_COND_P>; 393defm CMOVNB : FPCMov<X86_COND_AE>; 394defm CMOVNBE: FPCMov<X86_COND_A>; 395defm CMOVNE : FPCMov<X86_COND_NE>; 396defm CMOVNP : FPCMov<X86_COND_NP>; 397} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 398 399let Predicates = [HasCMov] in { 400// These are not factored because there's no clean way to pass DA/DB. 401def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 402 "fcmovb\t{$op, %st|st, $op}">; 403def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 404 "fcmovbe\t{$op, %st|st, $op}">; 405def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 406 "fcmove\t{$op, %st|st, $op}">; 407def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 408 "fcmovu\t{$op, %st|st, $op}">; 409def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 410 "fcmovnb\t{$op, %st|st, $op}">; 411def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 412 "fcmovnbe\t{$op, %st|st, $op}">; 413def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 414 "fcmovne\t{$op, %st|st, $op}">; 415def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 416 "fcmovnu\t{$op, %st|st, $op}">; 417} // Predicates = [HasCMov] 418} // SchedRW 419 420// Floating point loads & stores. 421let SchedRW = [WriteLoad] in { 422let canFoldAsLoad = 1 in { 423def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 424 [(set RFP32:$dst, (loadf32 addr:$src))]>; 425let isReMaterializable = 1 in 426 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 427 [(set RFP64:$dst, (loadf64 addr:$src))]>; 428def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 429 [(set RFP80:$dst, (loadf80 addr:$src))]>; 430} // canFoldAsLoad 431def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 432 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 433def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 434 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 435def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 436 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 437def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 438 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 439def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 440 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 441def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 442 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 443def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 444 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 445def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 446 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 447def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 448 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 449def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 450 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 451def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 452 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 453def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 454 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 455} // SchedRW 456 457let SchedRW = [WriteStore], Uses = [FPCW] in { 458def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 459 [(store RFP32:$src, addr:$op)]>; 460def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 461 [(truncstoref32 RFP64:$src, addr:$op)]>; 462def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 463 [(store RFP64:$src, addr:$op)]>; 464def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 465 [(truncstoref32 RFP80:$src, addr:$op)]>; 466def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 467 [(truncstoref64 RFP80:$src, addr:$op)]>; 468// FST does not support 80-bit memory target; FSTP must be used. 469 470let mayStore = 1, hasSideEffects = 0 in { 471def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 472def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 473def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 474def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 475def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 476} // mayStore 477 478def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 479 [(store RFP80:$src, addr:$op)]>; 480 481let mayStore = 1, hasSideEffects = 0 in { 482def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 483def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 484def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 485def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 486def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 487def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 488def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 489def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 490def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 491} // mayStore 492} // SchedRW, Uses = [FPCW] 493 494let mayLoad = 1, SchedRW = [WriteLoad] in { 495def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 496def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 497def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 498def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 499def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 500def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 501} 502let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 503def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 504def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 505def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 506def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 507def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 508def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 509def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 510def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 511def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 512def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 513} 514 515// FISTTP requires SSE3 even though it's a FPStack op. 516let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 517def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 518 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 519def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 520 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 521def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 522 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 523def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 524 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 525def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 526 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 527def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 528 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 529def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 530 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 531def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 532 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 533def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 534 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 535} // Predicates = [HasSSE3] 536 537let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 538def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 539def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 540def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 541} 542 543// FP Stack manipulation instructions. 544let SchedRW = [WriteMove] in { 545def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 546def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 547def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 548def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 549} 550 551// Floating point constant loads. 552let isReMaterializable = 1, SchedRW = [WriteZero] in { 553def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 554 [(set RFP32:$dst, fpimm0)]>; 555def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 556 [(set RFP32:$dst, fpimm1)]>; 557def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 558 [(set RFP64:$dst, fpimm0)]>; 559def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 560 [(set RFP64:$dst, fpimm1)]>; 561def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 562 [(set RFP80:$dst, fpimm0)]>; 563def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 564 [(set RFP80:$dst, fpimm1)]>; 565} 566 567let SchedRW = [WriteFLD0] in 568def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 569 570let SchedRW = [WriteFLD1] in 571def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 572 573let SchedRW = [WriteFLDC] in { 574def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 575def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 576def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 577def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 578def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 579} // SchedRW 580 581// Floating point compares. 582let SchedRW = [WriteFCom], Uses = [FPCW] in { 583def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 584 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 585def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 586 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 587def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 588 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 589} // SchedRW 590} // Defs = [FPSW] 591 592let SchedRW = [WriteFCom] in { 593// CC = ST(0) cmp ST(i) 594let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 595def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 596 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>, 597 Requires<[FPStackf32, HasCMov]>; 598def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 599 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>, 600 Requires<[FPStackf64, HasCMov]>; 601def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 602 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>, 603 Requires<[HasCMov]>; 604} 605 606let Defs = [FPSW], Uses = [ST0, FPCW] in { 607def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 608 (outs), (ins RSTi:$reg), "fucom\t$reg">; 609def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 610 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 611def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 612 (outs), (ins), "fucompp">; 613} 614 615let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 616def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 617 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 618def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 619 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 620 621def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 622 "fcomi\t{$reg, %st|st, $reg}">; 623def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 624 "fcompi\t{$reg, %st|st, $reg}">; 625} 626} // SchedRW 627 628// Floating point flag ops. 629let SchedRW = [WriteALU] in { 630let Defs = [AX], Uses = [FPSW] in 631def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 632 (outs), (ins), "fnstsw\t{%ax|ax}", 633 [(set AX, (X86fp_stsw FPSW))]>; 634let Defs = [FPSW], Uses = [FPCW] in 635def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 636 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 637 [(X86fp_cwd_get16 addr:$dst)]>; 638} // SchedRW 639let Defs = [FPSW,FPCW], mayLoad = 1 in 640def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 641 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 642 Sched<[WriteLoad]>; 643 644// FPU control instructions 645let SchedRW = [WriteMicrocoded] in { 646let Defs = [FPSW] in { 647def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 648def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 649def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 650 651// Clear exceptions 652def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 653} // Defs = [FPSW] 654} // SchedRW 655 656// Operand-less floating-point instructions for the disassembler. 657def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 658 659let SchedRW = [WriteMicrocoded] in { 660let Defs = [FPSW] in { 661def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 662def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 663def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 664def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 665def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 666def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 667def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 668def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 669def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 670def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 671def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 672def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 673def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 674def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 675def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 676def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 677} // Defs = [FPSW] 678 679def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 680 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, 681 Requires<[HasFXSR]>; 682def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 683 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 684 TB, Requires<[HasFXSR, In64BitMode]>; 685def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 686 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 687 TB, Requires<[HasFXSR]>; 688def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 689 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 690 TB, Requires<[HasFXSR, In64BitMode]>; 691} // SchedRW 692 693//===----------------------------------------------------------------------===// 694// Non-Instruction Patterns 695//===----------------------------------------------------------------------===// 696 697// Required for RET of f32 / f64 / f80 values. 698def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 699def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 700def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 701 702// Required for CALL which return f32 / f64 / f80 values. 703def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 704def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 705 RFP64:$src)>; 706def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 707def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 708 RFP80:$src)>; 709def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 710 RFP80:$src)>; 711def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 712 RFP80:$src)>; 713 714// Floating point constant -0.0 and -1.0 715def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 716def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 717def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 718def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 719def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 720def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 721 722// Used to conv. i64 to f64 since there isn't a SSE version. 723def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 724 725// FP extensions map onto simple pseudo-value conversions if they are to/from 726// the FP stack. 727def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 728 Requires<[FPStackf32]>; 729def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 730 Requires<[FPStackf32]>; 731def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 732 Requires<[FPStackf64]>; 733 734// FP truncations map onto simple pseudo-value conversions if they are to/from 735// the FP stack. We have validated that only value-preserving truncations make 736// it through isel. 737def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 738 Requires<[FPStackf32]>; 739def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 740 Requires<[FPStackf32]>; 741def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 742 Requires<[FPStackf64]>; 743