1 //===-- X86DisassemblerDecoder.cpp - Disassembler decoder -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler.
11 // It contains the implementation of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include <cstdarg> /* for va_*() */
17 #include <cstdio> /* for vsnprintf() */
18 #include <cstdlib> /* for exit() */
19 #include <cstring> /* for memset() */
20
21 #include "X86DisassemblerDecoder.h"
22
23 using namespace llvm::X86Disassembler;
24
25 /// Specifies whether a ModR/M byte is needed and (if so) which
26 /// instruction each possible value of the ModR/M byte corresponds to. Once
27 /// this information is known, we have narrowed down to a single instruction.
28 struct ModRMDecision {
29 uint8_t modrm_type;
30 uint16_t instructionIDs;
31 };
32
33 /// Specifies which set of ModR/M->instruction tables to look at
34 /// given a particular opcode.
35 struct OpcodeDecision {
36 ModRMDecision modRMDecisions[256];
37 };
38
39 /// Specifies which opcode->instruction tables to look at given
40 /// a particular context (set of attributes). Since there are many possible
41 /// contexts, the decoder first uses CONTEXTS_SYM to determine which context
42 /// applies given a specific set of attributes. Hence there are only IC_max
43 /// entries in this table, rather than 2^(ATTR_max).
44 struct ContextDecision {
45 OpcodeDecision opcodeDecisions[IC_max];
46 };
47
48 #include "X86GenDisassemblerTables.inc"
49
50 #ifndef NDEBUG
51 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
52 #else
53 #define debug(s) do { } while (0)
54 #endif
55
56 /*
57 * contextForAttrs - Client for the instruction context table. Takes a set of
58 * attributes and returns the appropriate decode context.
59 *
60 * @param attrMask - Attributes, from the enumeration attributeBits.
61 * @return - The InstructionContext to use when looking up an
62 * an instruction with these attributes.
63 */
contextForAttrs(uint16_t attrMask)64 static InstructionContext contextForAttrs(uint16_t attrMask) {
65 return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
66 }
67
68 /*
69 * modRMRequired - Reads the appropriate instruction table to determine whether
70 * the ModR/M byte is required to decode a particular instruction.
71 *
72 * @param type - The opcode type (i.e., how many bytes it has).
73 * @param insnContext - The context for the instruction, as returned by
74 * contextForAttrs.
75 * @param opcode - The last byte of the instruction's opcode, not counting
76 * ModR/M extensions and escapes.
77 * @return - true if the ModR/M byte is required, false otherwise.
78 */
modRMRequired(OpcodeType type,InstructionContext insnContext,uint16_t opcode)79 static int modRMRequired(OpcodeType type,
80 InstructionContext insnContext,
81 uint16_t opcode) {
82 const struct ContextDecision* decision = nullptr;
83
84 switch (type) {
85 case ONEBYTE:
86 decision = &ONEBYTE_SYM;
87 break;
88 case TWOBYTE:
89 decision = &TWOBYTE_SYM;
90 break;
91 case THREEBYTE_38:
92 decision = &THREEBYTE38_SYM;
93 break;
94 case THREEBYTE_3A:
95 decision = &THREEBYTE3A_SYM;
96 break;
97 case XOP8_MAP:
98 decision = &XOP8_MAP_SYM;
99 break;
100 case XOP9_MAP:
101 decision = &XOP9_MAP_SYM;
102 break;
103 case XOPA_MAP:
104 decision = &XOPA_MAP_SYM;
105 break;
106 case THREEDNOW_MAP:
107 decision = &THREEDNOW_MAP_SYM;
108 break;
109 }
110
111 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
112 modrm_type != MODRM_ONEENTRY;
113 }
114
115 /*
116 * decode - Reads the appropriate instruction table to obtain the unique ID of
117 * an instruction.
118 *
119 * @param type - See modRMRequired().
120 * @param insnContext - See modRMRequired().
121 * @param opcode - See modRMRequired().
122 * @param modRM - The ModR/M byte if required, or any value if not.
123 * @return - The UID of the instruction, or 0 on failure.
124 */
decode(OpcodeType type,InstructionContext insnContext,uint8_t opcode,uint8_t modRM)125 static InstrUID decode(OpcodeType type,
126 InstructionContext insnContext,
127 uint8_t opcode,
128 uint8_t modRM) {
129 const struct ModRMDecision* dec = nullptr;
130
131 switch (type) {
132 case ONEBYTE:
133 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
134 break;
135 case TWOBYTE:
136 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
137 break;
138 case THREEBYTE_38:
139 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
140 break;
141 case THREEBYTE_3A:
142 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143 break;
144 case XOP8_MAP:
145 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
146 break;
147 case XOP9_MAP:
148 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
149 break;
150 case XOPA_MAP:
151 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152 break;
153 case THREEDNOW_MAP:
154 dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155 break;
156 }
157
158 switch (dec->modrm_type) {
159 default:
160 debug("Corrupt table! Unknown modrm_type");
161 return 0;
162 case MODRM_ONEENTRY:
163 return modRMTable[dec->instructionIDs];
164 case MODRM_SPLITRM:
165 if (modFromModRM(modRM) == 0x3)
166 return modRMTable[dec->instructionIDs+1];
167 return modRMTable[dec->instructionIDs];
168 case MODRM_SPLITREG:
169 if (modFromModRM(modRM) == 0x3)
170 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
171 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
172 case MODRM_SPLITMISC:
173 if (modFromModRM(modRM) == 0x3)
174 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
175 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
176 case MODRM_FULL:
177 return modRMTable[dec->instructionIDs+modRM];
178 }
179 }
180
181 /*
182 * specifierForUID - Given a UID, returns the name and operand specification for
183 * that instruction.
184 *
185 * @param uid - The unique ID for the instruction. This should be returned by
186 * decode(); specifierForUID will not check bounds.
187 * @return - A pointer to the specification for that instruction.
188 */
specifierForUID(InstrUID uid)189 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
190 return &INSTRUCTIONS_SYM[uid];
191 }
192
193 /*
194 * consumeByte - Uses the reader function provided by the user to consume one
195 * byte from the instruction's memory and advance the cursor.
196 *
197 * @param insn - The instruction with the reader function to use. The cursor
198 * for this instruction is advanced.
199 * @param byte - A pointer to a pre-allocated memory buffer to be populated
200 * with the data read.
201 * @return - 0 if the read was successful; nonzero otherwise.
202 */
consumeByte(struct InternalInstruction * insn,uint8_t * byte)203 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
204 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
205
206 if (!ret)
207 ++(insn->readerCursor);
208
209 return ret;
210 }
211
212 /*
213 * lookAtByte - Like consumeByte, but does not advance the cursor.
214 *
215 * @param insn - See consumeByte().
216 * @param byte - See consumeByte().
217 * @return - See consumeByte().
218 */
lookAtByte(struct InternalInstruction * insn,uint8_t * byte)219 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
220 return insn->reader(insn->readerArg, byte, insn->readerCursor);
221 }
222
unconsumeByte(struct InternalInstruction * insn)223 static void unconsumeByte(struct InternalInstruction* insn) {
224 insn->readerCursor--;
225 }
226
227 #define CONSUME_FUNC(name, type) \
228 static int name(struct InternalInstruction* insn, type* ptr) { \
229 type combined = 0; \
230 unsigned offset; \
231 for (offset = 0; offset < sizeof(type); ++offset) { \
232 uint8_t byte; \
233 int ret = insn->reader(insn->readerArg, \
234 &byte, \
235 insn->readerCursor + offset); \
236 if (ret) \
237 return ret; \
238 combined = combined | ((uint64_t)byte << (offset * 8)); \
239 } \
240 *ptr = combined; \
241 insn->readerCursor += sizeof(type); \
242 return 0; \
243 }
244
245 /*
246 * consume* - Use the reader function provided by the user to consume data
247 * values of various sizes from the instruction's memory and advance the
248 * cursor appropriately. These readers perform endian conversion.
249 *
250 * @param insn - See consumeByte().
251 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
252 * be populated with the data read.
253 * @return - See consumeByte().
254 */
CONSUME_FUNC(consumeInt8,int8_t)255 CONSUME_FUNC(consumeInt8, int8_t)
256 CONSUME_FUNC(consumeInt16, int16_t)
257 CONSUME_FUNC(consumeInt32, int32_t)
258 CONSUME_FUNC(consumeUInt16, uint16_t)
259 CONSUME_FUNC(consumeUInt32, uint32_t)
260 CONSUME_FUNC(consumeUInt64, uint64_t)
261
262 /*
263 * dbgprintf - Uses the logging function provided by the user to log a single
264 * message, typically without a carriage-return.
265 *
266 * @param insn - The instruction containing the logging function.
267 * @param format - See printf().
268 * @param ... - See printf().
269 */
270 static void dbgprintf(struct InternalInstruction* insn,
271 const char* format,
272 ...) {
273 char buffer[256];
274 va_list ap;
275
276 if (!insn->dlog)
277 return;
278
279 va_start(ap, format);
280 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
281 va_end(ap);
282
283 insn->dlog(insn->dlogArg, buffer);
284 }
285
isREX(struct InternalInstruction * insn,uint8_t prefix)286 static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
287 if (insn->mode == MODE_64BIT)
288 return prefix >= 0x40 && prefix <= 0x4f;
289 return false;
290 }
291
292 /*
293 * setPrefixPresent - Marks that a particular prefix is present as mandatory
294 *
295 * @param insn - The instruction to be marked as having the prefix.
296 * @param prefix - The prefix that is present.
297 */
setPrefixPresent(struct InternalInstruction * insn,uint8_t prefix)298 static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) {
299 uint8_t nextByte;
300 switch (prefix) {
301 case 0xf0:
302 insn->hasLockPrefix = true;
303 break;
304 case 0xf2:
305 case 0xf3:
306 if (lookAtByte(insn, &nextByte))
307 break;
308 // TODO:
309 // 1. There could be several 0x66
310 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
311 // it's not mandatory prefix
312 // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
313 // 0x0f exactly after it to be mandatory prefix
314 if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
315 // The last of 0xf2 /0xf3 is mandatory prefix
316 insn->mandatoryPrefix = prefix;
317 insn->repeatPrefix = prefix;
318 break;
319 case 0x66:
320 if (lookAtByte(insn, &nextByte))
321 break;
322 // 0x66 can't overwrite existing mandatory prefix and should be ignored
323 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
324 insn->mandatoryPrefix = prefix;
325 break;
326 }
327 }
328
329 /*
330 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
331 * instruction as having them. Also sets the instruction's default operand,
332 * address, and other relevant data sizes to report operands correctly.
333 *
334 * @param insn - The instruction whose prefixes are to be read.
335 * @return - 0 if the instruction could be read until the end of the prefix
336 * bytes, and no prefixes conflicted; nonzero otherwise.
337 */
readPrefixes(struct InternalInstruction * insn)338 static int readPrefixes(struct InternalInstruction* insn) {
339 bool isPrefix = true;
340 uint8_t byte = 0;
341 uint8_t nextByte;
342
343 dbgprintf(insn, "readPrefixes()");
344
345 while (isPrefix) {
346 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
347 if (consumeByte(insn, &byte))
348 break;
349
350 /*
351 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
352 * break and let it be disassembled as a normal "instruction".
353 */
354 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
355 break;
356
357 if ((byte == 0xf2 || byte == 0xf3) && !lookAtByte(insn, &nextByte)) {
358 /*
359 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
360 * met:
361 * - it is followed by a LOCK (0xf0) prefix
362 * - it is followed by an xchg instruction
363 * then it should be disassembled as a xacquire/xrelease not repne/rep.
364 */
365 if (((nextByte == 0xf0) ||
366 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
367 insn->xAcquireRelease = true;
368 if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
369 break;
370 }
371 /*
372 * Also if the byte is 0xf3, and the following condition is met:
373 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
374 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
375 * then it should be disassembled as an xrelease not rep.
376 */
377 if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
378 nextByte == 0xc6 || nextByte == 0xc7)) {
379 insn->xAcquireRelease = true;
380 if (nextByte != 0x90) // PAUSE instruction support
381 break;
382 }
383 if (isREX(insn, nextByte)) {
384 uint8_t nnextByte;
385 // Go to REX prefix after the current one
386 if (consumeByte(insn, &nnextByte))
387 return -1;
388 // We should be able to read next byte after REX prefix
389 if (lookAtByte(insn, &nnextByte))
390 return -1;
391 unconsumeByte(insn);
392 }
393 }
394
395 switch (byte) {
396 case 0xf0: /* LOCK */
397 case 0xf2: /* REPNE/REPNZ */
398 case 0xf3: /* REP or REPE/REPZ */
399 setPrefixPresent(insn, byte);
400 break;
401 case 0x2e: /* CS segment override -OR- Branch not taken */
402 case 0x36: /* SS segment override -OR- Branch taken */
403 case 0x3e: /* DS segment override */
404 case 0x26: /* ES segment override */
405 case 0x64: /* FS segment override */
406 case 0x65: /* GS segment override */
407 switch (byte) {
408 case 0x2e:
409 insn->segmentOverride = SEG_OVERRIDE_CS;
410 break;
411 case 0x36:
412 insn->segmentOverride = SEG_OVERRIDE_SS;
413 break;
414 case 0x3e:
415 insn->segmentOverride = SEG_OVERRIDE_DS;
416 break;
417 case 0x26:
418 insn->segmentOverride = SEG_OVERRIDE_ES;
419 break;
420 case 0x64:
421 insn->segmentOverride = SEG_OVERRIDE_FS;
422 break;
423 case 0x65:
424 insn->segmentOverride = SEG_OVERRIDE_GS;
425 break;
426 default:
427 debug("Unhandled override");
428 return -1;
429 }
430 setPrefixPresent(insn, byte);
431 break;
432 case 0x66: /* Operand-size override */
433 insn->hasOpSize = true;
434 setPrefixPresent(insn, byte);
435 break;
436 case 0x67: /* Address-size override */
437 insn->hasAdSize = true;
438 setPrefixPresent(insn, byte);
439 break;
440 default: /* Not a prefix byte */
441 isPrefix = false;
442 break;
443 }
444
445 if (isPrefix)
446 dbgprintf(insn, "Found prefix 0x%hhx", byte);
447 }
448
449 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
450
451 if (byte == 0x62) {
452 uint8_t byte1, byte2;
453
454 if (consumeByte(insn, &byte1)) {
455 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
456 return -1;
457 }
458
459 if (lookAtByte(insn, &byte2)) {
460 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
461 return -1;
462 }
463
464 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
465 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
466 insn->vectorExtensionType = TYPE_EVEX;
467 } else {
468 unconsumeByte(insn); /* unconsume byte1 */
469 unconsumeByte(insn); /* unconsume byte */
470 }
471
472 if (insn->vectorExtensionType == TYPE_EVEX) {
473 insn->vectorExtensionPrefix[0] = byte;
474 insn->vectorExtensionPrefix[1] = byte1;
475 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
476 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
477 return -1;
478 }
479 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
480 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
481 return -1;
482 }
483
484 /* We simulate the REX prefix for simplicity's sake */
485 if (insn->mode == MODE_64BIT) {
486 insn->rexPrefix = 0x40
487 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
488 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
489 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
490 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
491 }
492
493 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
494 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
495 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
496 }
497 } else if (byte == 0xc4) {
498 uint8_t byte1;
499
500 if (lookAtByte(insn, &byte1)) {
501 dbgprintf(insn, "Couldn't read second byte of VEX");
502 return -1;
503 }
504
505 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
506 insn->vectorExtensionType = TYPE_VEX_3B;
507 else
508 unconsumeByte(insn);
509
510 if (insn->vectorExtensionType == TYPE_VEX_3B) {
511 insn->vectorExtensionPrefix[0] = byte;
512 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
513 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
514
515 /* We simulate the REX prefix for simplicity's sake */
516
517 if (insn->mode == MODE_64BIT)
518 insn->rexPrefix = 0x40
519 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
520 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
521 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
522 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
523
524 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
525 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
526 insn->vectorExtensionPrefix[2]);
527 }
528 } else if (byte == 0xc5) {
529 uint8_t byte1;
530
531 if (lookAtByte(insn, &byte1)) {
532 dbgprintf(insn, "Couldn't read second byte of VEX");
533 return -1;
534 }
535
536 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
537 insn->vectorExtensionType = TYPE_VEX_2B;
538 else
539 unconsumeByte(insn);
540
541 if (insn->vectorExtensionType == TYPE_VEX_2B) {
542 insn->vectorExtensionPrefix[0] = byte;
543 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
544
545 if (insn->mode == MODE_64BIT)
546 insn->rexPrefix = 0x40
547 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
548
549 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
550 default:
551 break;
552 case VEX_PREFIX_66:
553 insn->hasOpSize = true;
554 break;
555 }
556
557 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
558 insn->vectorExtensionPrefix[0],
559 insn->vectorExtensionPrefix[1]);
560 }
561 } else if (byte == 0x8f) {
562 uint8_t byte1;
563
564 if (lookAtByte(insn, &byte1)) {
565 dbgprintf(insn, "Couldn't read second byte of XOP");
566 return -1;
567 }
568
569 if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */
570 insn->vectorExtensionType = TYPE_XOP;
571 else
572 unconsumeByte(insn);
573
574 if (insn->vectorExtensionType == TYPE_XOP) {
575 insn->vectorExtensionPrefix[0] = byte;
576 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
577 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
578
579 /* We simulate the REX prefix for simplicity's sake */
580
581 if (insn->mode == MODE_64BIT)
582 insn->rexPrefix = 0x40
583 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
584 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
585 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
586 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
587
588 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
589 default:
590 break;
591 case VEX_PREFIX_66:
592 insn->hasOpSize = true;
593 break;
594 }
595
596 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
597 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
598 insn->vectorExtensionPrefix[2]);
599 }
600 } else if (isREX(insn, byte)) {
601 if (lookAtByte(insn, &nextByte))
602 return -1;
603 insn->rexPrefix = byte;
604 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
605 } else
606 unconsumeByte(insn);
607
608 if (insn->mode == MODE_16BIT) {
609 insn->registerSize = (insn->hasOpSize ? 4 : 2);
610 insn->addressSize = (insn->hasAdSize ? 4 : 2);
611 insn->displacementSize = (insn->hasAdSize ? 4 : 2);
612 insn->immediateSize = (insn->hasOpSize ? 4 : 2);
613 } else if (insn->mode == MODE_32BIT) {
614 insn->registerSize = (insn->hasOpSize ? 2 : 4);
615 insn->addressSize = (insn->hasAdSize ? 2 : 4);
616 insn->displacementSize = (insn->hasAdSize ? 2 : 4);
617 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
618 } else if (insn->mode == MODE_64BIT) {
619 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
620 insn->registerSize = 8;
621 insn->addressSize = (insn->hasAdSize ? 4 : 8);
622 insn->displacementSize = 4;
623 insn->immediateSize = 4;
624 } else {
625 insn->registerSize = (insn->hasOpSize ? 2 : 4);
626 insn->addressSize = (insn->hasAdSize ? 4 : 8);
627 insn->displacementSize = (insn->hasOpSize ? 2 : 4);
628 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
629 }
630 }
631
632 return 0;
633 }
634
635 static int readModRM(struct InternalInstruction* insn);
636
637 /*
638 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
639 * extended or escape opcodes).
640 *
641 * @param insn - The instruction whose opcode is to be read.
642 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
643 */
readOpcode(struct InternalInstruction * insn)644 static int readOpcode(struct InternalInstruction* insn) {
645 /* Determine the length of the primary opcode */
646
647 uint8_t current;
648
649 dbgprintf(insn, "readOpcode()");
650
651 insn->opcodeType = ONEBYTE;
652
653 if (insn->vectorExtensionType == TYPE_EVEX) {
654 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
655 default:
656 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
657 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
658 return -1;
659 case VEX_LOB_0F:
660 insn->opcodeType = TWOBYTE;
661 return consumeByte(insn, &insn->opcode);
662 case VEX_LOB_0F38:
663 insn->opcodeType = THREEBYTE_38;
664 return consumeByte(insn, &insn->opcode);
665 case VEX_LOB_0F3A:
666 insn->opcodeType = THREEBYTE_3A;
667 return consumeByte(insn, &insn->opcode);
668 }
669 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
670 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
671 default:
672 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
673 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
674 return -1;
675 case VEX_LOB_0F:
676 insn->opcodeType = TWOBYTE;
677 return consumeByte(insn, &insn->opcode);
678 case VEX_LOB_0F38:
679 insn->opcodeType = THREEBYTE_38;
680 return consumeByte(insn, &insn->opcode);
681 case VEX_LOB_0F3A:
682 insn->opcodeType = THREEBYTE_3A;
683 return consumeByte(insn, &insn->opcode);
684 }
685 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
686 insn->opcodeType = TWOBYTE;
687 return consumeByte(insn, &insn->opcode);
688 } else if (insn->vectorExtensionType == TYPE_XOP) {
689 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
690 default:
691 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
692 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
693 return -1;
694 case XOP_MAP_SELECT_8:
695 insn->opcodeType = XOP8_MAP;
696 return consumeByte(insn, &insn->opcode);
697 case XOP_MAP_SELECT_9:
698 insn->opcodeType = XOP9_MAP;
699 return consumeByte(insn, &insn->opcode);
700 case XOP_MAP_SELECT_A:
701 insn->opcodeType = XOPA_MAP;
702 return consumeByte(insn, &insn->opcode);
703 }
704 }
705
706 if (consumeByte(insn, ¤t))
707 return -1;
708
709 if (current == 0x0f) {
710 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
711
712 if (consumeByte(insn, ¤t))
713 return -1;
714
715 if (current == 0x38) {
716 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
717
718 if (consumeByte(insn, ¤t))
719 return -1;
720
721 insn->opcodeType = THREEBYTE_38;
722 } else if (current == 0x3a) {
723 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
724
725 if (consumeByte(insn, ¤t))
726 return -1;
727
728 insn->opcodeType = THREEBYTE_3A;
729 } else if (current == 0x0f) {
730 dbgprintf(insn, "Found a 3dnow escape prefix (0x%hhx)", current);
731
732 // Consume operands before the opcode to comply with the 3DNow encoding
733 if (readModRM(insn))
734 return -1;
735
736 if (consumeByte(insn, ¤t))
737 return -1;
738
739 insn->opcodeType = THREEDNOW_MAP;
740 } else {
741 dbgprintf(insn, "Didn't find a three-byte escape prefix");
742
743 insn->opcodeType = TWOBYTE;
744 }
745 } else if (insn->mandatoryPrefix)
746 // The opcode with mandatory prefix must start with opcode escape.
747 // If not it's legacy repeat prefix
748 insn->mandatoryPrefix = 0;
749
750 /*
751 * At this point we have consumed the full opcode.
752 * Anything we consume from here on must be unconsumed.
753 */
754
755 insn->opcode = current;
756
757 return 0;
758 }
759
760 /*
761 * getIDWithAttrMask - Determines the ID of an instruction, consuming
762 * the ModR/M byte as appropriate for extended and escape opcodes,
763 * and using a supplied attribute mask.
764 *
765 * @param instructionID - A pointer whose target is filled in with the ID of the
766 * instruction.
767 * @param insn - The instruction whose ID is to be determined.
768 * @param attrMask - The attribute mask to search.
769 * @return - 0 if the ModR/M could be read when needed or was not
770 * needed; nonzero otherwise.
771 */
getIDWithAttrMask(uint16_t * instructionID,struct InternalInstruction * insn,uint16_t attrMask)772 static int getIDWithAttrMask(uint16_t* instructionID,
773 struct InternalInstruction* insn,
774 uint16_t attrMask) {
775 bool hasModRMExtension;
776
777 InstructionContext instructionClass = contextForAttrs(attrMask);
778
779 hasModRMExtension = modRMRequired(insn->opcodeType,
780 instructionClass,
781 insn->opcode);
782
783 if (hasModRMExtension) {
784 if (readModRM(insn))
785 return -1;
786
787 *instructionID = decode(insn->opcodeType,
788 instructionClass,
789 insn->opcode,
790 insn->modRM);
791 } else {
792 *instructionID = decode(insn->opcodeType,
793 instructionClass,
794 insn->opcode,
795 0);
796 }
797
798 return 0;
799 }
800
801 /*
802 * is16BitEquivalent - Determines whether two instruction names refer to
803 * equivalent instructions but one is 16-bit whereas the other is not.
804 *
805 * @param orig - The instruction that is not 16-bit
806 * @param equiv - The instruction that is 16-bit
807 */
is16BitEquivalent(const char * orig,const char * equiv)808 static bool is16BitEquivalent(const char *orig, const char *equiv) {
809 off_t i;
810
811 for (i = 0;; i++) {
812 if (orig[i] == '\0' && equiv[i] == '\0')
813 return true;
814 if (orig[i] == '\0' || equiv[i] == '\0')
815 return false;
816 if (orig[i] != equiv[i]) {
817 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
818 continue;
819 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
820 continue;
821 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
822 continue;
823 return false;
824 }
825 }
826 }
827
828 /*
829 * is64Bit - Determines whether this instruction is a 64-bit instruction.
830 *
831 * @param name - The instruction that is not 16-bit
832 */
is64Bit(const char * name)833 static bool is64Bit(const char *name) {
834 off_t i;
835
836 for (i = 0;; ++i) {
837 if (name[i] == '\0')
838 return false;
839 if (name[i] == '6' && name[i+1] == '4')
840 return true;
841 }
842 }
843
844 /*
845 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
846 * appropriate for extended and escape opcodes. Determines the attributes and
847 * context for the instruction before doing so.
848 *
849 * @param insn - The instruction whose ID is to be determined.
850 * @return - 0 if the ModR/M could be read when needed or was not needed;
851 * nonzero otherwise.
852 */
getID(struct InternalInstruction * insn,const void * miiArg)853 static int getID(struct InternalInstruction* insn, const void *miiArg) {
854 uint16_t attrMask;
855 uint16_t instructionID;
856
857 dbgprintf(insn, "getID()");
858
859 attrMask = ATTR_NONE;
860
861 if (insn->mode == MODE_64BIT)
862 attrMask |= ATTR_64BIT;
863
864 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
865 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
866
867 if (insn->vectorExtensionType == TYPE_EVEX) {
868 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
869 case VEX_PREFIX_66:
870 attrMask |= ATTR_OPSIZE;
871 break;
872 case VEX_PREFIX_F3:
873 attrMask |= ATTR_XS;
874 break;
875 case VEX_PREFIX_F2:
876 attrMask |= ATTR_XD;
877 break;
878 }
879
880 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
881 attrMask |= ATTR_EVEXKZ;
882 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
883 attrMask |= ATTR_EVEXB;
884 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
885 attrMask |= ATTR_EVEXK;
886 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
887 attrMask |= ATTR_EVEXL;
888 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
889 attrMask |= ATTR_EVEXL2;
890 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
891 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
892 case VEX_PREFIX_66:
893 attrMask |= ATTR_OPSIZE;
894 break;
895 case VEX_PREFIX_F3:
896 attrMask |= ATTR_XS;
897 break;
898 case VEX_PREFIX_F2:
899 attrMask |= ATTR_XD;
900 break;
901 }
902
903 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
904 attrMask |= ATTR_VEXL;
905 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
906 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
907 case VEX_PREFIX_66:
908 attrMask |= ATTR_OPSIZE;
909 break;
910 case VEX_PREFIX_F3:
911 attrMask |= ATTR_XS;
912 break;
913 case VEX_PREFIX_F2:
914 attrMask |= ATTR_XD;
915 break;
916 }
917
918 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
919 attrMask |= ATTR_VEXL;
920 } else if (insn->vectorExtensionType == TYPE_XOP) {
921 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
922 case VEX_PREFIX_66:
923 attrMask |= ATTR_OPSIZE;
924 break;
925 case VEX_PREFIX_F3:
926 attrMask |= ATTR_XS;
927 break;
928 case VEX_PREFIX_F2:
929 attrMask |= ATTR_XD;
930 break;
931 }
932
933 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
934 attrMask |= ATTR_VEXL;
935 } else {
936 return -1;
937 }
938 } else if (!insn->mandatoryPrefix) {
939 // If we don't have mandatory prefix we should use legacy prefixes here
940 if (insn->hasOpSize && (insn->mode != MODE_16BIT))
941 attrMask |= ATTR_OPSIZE;
942 if (insn->hasAdSize)
943 attrMask |= ATTR_ADSIZE;
944 if (insn->opcodeType == ONEBYTE) {
945 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
946 // Special support for PAUSE
947 attrMask |= ATTR_XS;
948 } else {
949 if (insn->repeatPrefix == 0xf2)
950 attrMask |= ATTR_XD;
951 else if (insn->repeatPrefix == 0xf3)
952 attrMask |= ATTR_XS;
953 }
954 } else {
955 switch (insn->mandatoryPrefix) {
956 case 0xf2:
957 attrMask |= ATTR_XD;
958 break;
959 case 0xf3:
960 attrMask |= ATTR_XS;
961 break;
962 case 0x66:
963 if (insn->mode != MODE_16BIT)
964 attrMask |= ATTR_OPSIZE;
965 break;
966 case 0x67:
967 attrMask |= ATTR_ADSIZE;
968 break;
969 }
970
971 }
972
973 if (insn->rexPrefix & 0x08) {
974 attrMask |= ATTR_REXW;
975 attrMask &= ~ATTR_ADSIZE;
976 }
977
978 /*
979 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
980 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
981 */
982 if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE &&
983 insn->opcode == 0xE3)
984 attrMask ^= ATTR_ADSIZE;
985
986 // If we're in 16-bit mode and this is one of the relative jumps and opsize
987 // prefix isn't present, we need to force the opsize attribute since the
988 // prefix is inverted relative to 32-bit mode.
989 if (insn->mode == MODE_16BIT && !insn->hasOpSize &&
990 insn->opcodeType == ONEBYTE &&
991 (insn->opcode == 0xE8 || insn->opcode == 0xE9))
992 attrMask |= ATTR_OPSIZE;
993
994 if (insn->mode == MODE_16BIT && !insn->hasOpSize &&
995 insn->opcodeType == TWOBYTE &&
996 insn->opcode >= 0x80 && insn->opcode <= 0x8F)
997 attrMask |= ATTR_OPSIZE;
998
999 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1000 return -1;
1001
1002 /* The following clauses compensate for limitations of the tables. */
1003
1004 if (insn->mode != MODE_64BIT &&
1005 insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
1006 /*
1007 * The tables can't distinquish between cases where the W-bit is used to
1008 * select register size and cases where its a required part of the opcode.
1009 */
1010 if ((insn->vectorExtensionType == TYPE_EVEX &&
1011 wFromEVEX3of4(insn->vectorExtensionPrefix[2])) ||
1012 (insn->vectorExtensionType == TYPE_VEX_3B &&
1013 wFromVEX3of3(insn->vectorExtensionPrefix[2])) ||
1014 (insn->vectorExtensionType == TYPE_XOP &&
1015 wFromXOP3of3(insn->vectorExtensionPrefix[2]))) {
1016
1017 uint16_t instructionIDWithREXW;
1018 if (getIDWithAttrMask(&instructionIDWithREXW,
1019 insn, attrMask | ATTR_REXW)) {
1020 insn->instructionID = instructionID;
1021 insn->spec = specifierForUID(instructionID);
1022 return 0;
1023 }
1024
1025 auto SpecName = GetInstrName(instructionIDWithREXW, miiArg);
1026 // If not a 64-bit instruction. Switch the opcode.
1027 if (!is64Bit(SpecName.data())) {
1028 insn->instructionID = instructionIDWithREXW;
1029 insn->spec = specifierForUID(instructionIDWithREXW);
1030 return 0;
1031 }
1032 }
1033 }
1034
1035 /*
1036 * Absolute moves, umonitor, and movdir64b need special handling.
1037 * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1038 * inverted w.r.t.
1039 * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1040 * any position.
1041 */
1042 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1043 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1044 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
1045 /* Make sure we observed the prefixes in any position. */
1046 if (insn->hasAdSize)
1047 attrMask |= ATTR_ADSIZE;
1048 if (insn->hasOpSize)
1049 attrMask |= ATTR_OPSIZE;
1050
1051 /* In 16-bit, invert the attributes. */
1052 if (insn->mode == MODE_16BIT) {
1053 attrMask ^= ATTR_ADSIZE;
1054
1055 /* The OpSize attribute is only valid with the absolute moves. */
1056 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1057 attrMask ^= ATTR_OPSIZE;
1058 }
1059
1060 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1061 return -1;
1062
1063 insn->instructionID = instructionID;
1064 insn->spec = specifierForUID(instructionID);
1065 return 0;
1066 }
1067
1068 if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1069 !(attrMask & ATTR_OPSIZE)) {
1070 /*
1071 * The instruction tables make no distinction between instructions that
1072 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1073 * particular spot (i.e., many MMX operations). In general we're
1074 * conservative, but in the specific case where OpSize is present but not
1075 * in the right place we check if there's a 16-bit operation.
1076 */
1077
1078 const struct InstructionSpecifier *spec;
1079 uint16_t instructionIDWithOpsize;
1080 llvm::StringRef specName, specWithOpSizeName;
1081
1082 spec = specifierForUID(instructionID);
1083
1084 if (getIDWithAttrMask(&instructionIDWithOpsize,
1085 insn,
1086 attrMask | ATTR_OPSIZE)) {
1087 /*
1088 * ModRM required with OpSize but not present; give up and return version
1089 * without OpSize set
1090 */
1091
1092 insn->instructionID = instructionID;
1093 insn->spec = spec;
1094 return 0;
1095 }
1096
1097 specName = GetInstrName(instructionID, miiArg);
1098 specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1099
1100 if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1101 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1102 insn->instructionID = instructionIDWithOpsize;
1103 insn->spec = specifierForUID(instructionIDWithOpsize);
1104 } else {
1105 insn->instructionID = instructionID;
1106 insn->spec = spec;
1107 }
1108 return 0;
1109 }
1110
1111 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1112 insn->rexPrefix & 0x01) {
1113 /*
1114 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1115 * it should decode as XCHG %r8, %eax.
1116 */
1117
1118 const struct InstructionSpecifier *spec;
1119 uint16_t instructionIDWithNewOpcode;
1120 const struct InstructionSpecifier *specWithNewOpcode;
1121
1122 spec = specifierForUID(instructionID);
1123
1124 /* Borrow opcode from one of the other XCHGar opcodes */
1125 insn->opcode = 0x91;
1126
1127 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1128 insn,
1129 attrMask)) {
1130 insn->opcode = 0x90;
1131
1132 insn->instructionID = instructionID;
1133 insn->spec = spec;
1134 return 0;
1135 }
1136
1137 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1138
1139 /* Change back */
1140 insn->opcode = 0x90;
1141
1142 insn->instructionID = instructionIDWithNewOpcode;
1143 insn->spec = specWithNewOpcode;
1144
1145 return 0;
1146 }
1147
1148 insn->instructionID = instructionID;
1149 insn->spec = specifierForUID(insn->instructionID);
1150
1151 return 0;
1152 }
1153
1154 /*
1155 * readSIB - Consumes the SIB byte to determine addressing information for an
1156 * instruction.
1157 *
1158 * @param insn - The instruction whose SIB byte is to be read.
1159 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1160 */
readSIB(struct InternalInstruction * insn)1161 static int readSIB(struct InternalInstruction* insn) {
1162 SIBBase sibBaseBase = SIB_BASE_NONE;
1163 uint8_t index, base;
1164
1165 dbgprintf(insn, "readSIB()");
1166
1167 if (insn->consumedSIB)
1168 return 0;
1169
1170 insn->consumedSIB = true;
1171
1172 switch (insn->addressSize) {
1173 case 2:
1174 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1175 return -1;
1176 case 4:
1177 insn->sibIndexBase = SIB_INDEX_EAX;
1178 sibBaseBase = SIB_BASE_EAX;
1179 break;
1180 case 8:
1181 insn->sibIndexBase = SIB_INDEX_RAX;
1182 sibBaseBase = SIB_BASE_RAX;
1183 break;
1184 }
1185
1186 if (consumeByte(insn, &insn->sib))
1187 return -1;
1188
1189 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1190
1191 if (index == 0x4) {
1192 insn->sibIndex = SIB_INDEX_NONE;
1193 } else {
1194 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
1195 }
1196
1197 insn->sibScale = 1 << scaleFromSIB(insn->sib);
1198
1199 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1200
1201 switch (base) {
1202 case 0x5:
1203 case 0xd:
1204 switch (modFromModRM(insn->modRM)) {
1205 case 0x0:
1206 insn->eaDisplacement = EA_DISP_32;
1207 insn->sibBase = SIB_BASE_NONE;
1208 break;
1209 case 0x1:
1210 insn->eaDisplacement = EA_DISP_8;
1211 insn->sibBase = (SIBBase)(sibBaseBase + base);
1212 break;
1213 case 0x2:
1214 insn->eaDisplacement = EA_DISP_32;
1215 insn->sibBase = (SIBBase)(sibBaseBase + base);
1216 break;
1217 case 0x3:
1218 debug("Cannot have Mod = 0b11 and a SIB byte");
1219 return -1;
1220 }
1221 break;
1222 default:
1223 insn->sibBase = (SIBBase)(sibBaseBase + base);
1224 break;
1225 }
1226
1227 return 0;
1228 }
1229
1230 /*
1231 * readDisplacement - Consumes the displacement of an instruction.
1232 *
1233 * @param insn - The instruction whose displacement is to be read.
1234 * @return - 0 if the displacement byte was successfully read; nonzero
1235 * otherwise.
1236 */
readDisplacement(struct InternalInstruction * insn)1237 static int readDisplacement(struct InternalInstruction* insn) {
1238 int8_t d8;
1239 int16_t d16;
1240 int32_t d32;
1241
1242 dbgprintf(insn, "readDisplacement()");
1243
1244 if (insn->consumedDisplacement)
1245 return 0;
1246
1247 insn->consumedDisplacement = true;
1248 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1249
1250 switch (insn->eaDisplacement) {
1251 case EA_DISP_NONE:
1252 insn->consumedDisplacement = false;
1253 break;
1254 case EA_DISP_8:
1255 if (consumeInt8(insn, &d8))
1256 return -1;
1257 insn->displacement = d8;
1258 break;
1259 case EA_DISP_16:
1260 if (consumeInt16(insn, &d16))
1261 return -1;
1262 insn->displacement = d16;
1263 break;
1264 case EA_DISP_32:
1265 if (consumeInt32(insn, &d32))
1266 return -1;
1267 insn->displacement = d32;
1268 break;
1269 }
1270
1271 insn->consumedDisplacement = true;
1272 return 0;
1273 }
1274
1275 /*
1276 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1277 * displacement) for an instruction and interprets it.
1278 *
1279 * @param insn - The instruction whose addressing information is to be read.
1280 * @return - 0 if the information was successfully read; nonzero otherwise.
1281 */
readModRM(struct InternalInstruction * insn)1282 static int readModRM(struct InternalInstruction* insn) {
1283 uint8_t mod, rm, reg, evexrm;
1284
1285 dbgprintf(insn, "readModRM()");
1286
1287 if (insn->consumedModRM)
1288 return 0;
1289
1290 if (consumeByte(insn, &insn->modRM))
1291 return -1;
1292 insn->consumedModRM = true;
1293
1294 mod = modFromModRM(insn->modRM);
1295 rm = rmFromModRM(insn->modRM);
1296 reg = regFromModRM(insn->modRM);
1297
1298 /*
1299 * This goes by insn->registerSize to pick the correct register, which messes
1300 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1301 * fixupReg().
1302 */
1303 switch (insn->registerSize) {
1304 case 2:
1305 insn->regBase = MODRM_REG_AX;
1306 insn->eaRegBase = EA_REG_AX;
1307 break;
1308 case 4:
1309 insn->regBase = MODRM_REG_EAX;
1310 insn->eaRegBase = EA_REG_EAX;
1311 break;
1312 case 8:
1313 insn->regBase = MODRM_REG_RAX;
1314 insn->eaRegBase = EA_REG_RAX;
1315 break;
1316 }
1317
1318 reg |= rFromREX(insn->rexPrefix) << 3;
1319 rm |= bFromREX(insn->rexPrefix) << 3;
1320
1321 evexrm = 0;
1322 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) {
1323 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1324 evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1325 }
1326
1327 insn->reg = (Reg)(insn->regBase + reg);
1328
1329 switch (insn->addressSize) {
1330 case 2: {
1331 EABase eaBaseBase = EA_BASE_BX_SI;
1332
1333 switch (mod) {
1334 case 0x0:
1335 if (rm == 0x6) {
1336 insn->eaBase = EA_BASE_NONE;
1337 insn->eaDisplacement = EA_DISP_16;
1338 if (readDisplacement(insn))
1339 return -1;
1340 } else {
1341 insn->eaBase = (EABase)(eaBaseBase + rm);
1342 insn->eaDisplacement = EA_DISP_NONE;
1343 }
1344 break;
1345 case 0x1:
1346 insn->eaBase = (EABase)(eaBaseBase + rm);
1347 insn->eaDisplacement = EA_DISP_8;
1348 insn->displacementSize = 1;
1349 if (readDisplacement(insn))
1350 return -1;
1351 break;
1352 case 0x2:
1353 insn->eaBase = (EABase)(eaBaseBase + rm);
1354 insn->eaDisplacement = EA_DISP_16;
1355 if (readDisplacement(insn))
1356 return -1;
1357 break;
1358 case 0x3:
1359 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1360 if (readDisplacement(insn))
1361 return -1;
1362 break;
1363 }
1364 break;
1365 }
1366 case 4:
1367 case 8: {
1368 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1369
1370 switch (mod) {
1371 case 0x0:
1372 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1373 // In determining whether RIP-relative mode is used (rm=5),
1374 // or whether a SIB byte is present (rm=4),
1375 // the extension bits (REX.b and EVEX.x) are ignored.
1376 switch (rm & 7) {
1377 case 0x4: // SIB byte is present
1378 insn->eaBase = (insn->addressSize == 4 ?
1379 EA_BASE_sib : EA_BASE_sib64);
1380 if (readSIB(insn) || readDisplacement(insn))
1381 return -1;
1382 break;
1383 case 0x5: // RIP-relative
1384 insn->eaBase = EA_BASE_NONE;
1385 insn->eaDisplacement = EA_DISP_32;
1386 if (readDisplacement(insn))
1387 return -1;
1388 break;
1389 default:
1390 insn->eaBase = (EABase)(eaBaseBase + rm);
1391 break;
1392 }
1393 break;
1394 case 0x1:
1395 insn->displacementSize = 1;
1396 LLVM_FALLTHROUGH;
1397 case 0x2:
1398 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1399 switch (rm & 7) {
1400 case 0x4: // SIB byte is present
1401 insn->eaBase = EA_BASE_sib;
1402 if (readSIB(insn) || readDisplacement(insn))
1403 return -1;
1404 break;
1405 default:
1406 insn->eaBase = (EABase)(eaBaseBase + rm);
1407 if (readDisplacement(insn))
1408 return -1;
1409 break;
1410 }
1411 break;
1412 case 0x3:
1413 insn->eaDisplacement = EA_DISP_NONE;
1414 insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm);
1415 break;
1416 }
1417 break;
1418 }
1419 } /* switch (insn->addressSize) */
1420
1421 return 0;
1422 }
1423
1424 #define GENERIC_FIXUP_FUNC(name, base, prefix, mask) \
1425 static uint16_t name(struct InternalInstruction *insn, \
1426 OperandType type, \
1427 uint8_t index, \
1428 uint8_t *valid) { \
1429 *valid = 1; \
1430 switch (type) { \
1431 default: \
1432 debug("Unhandled register type"); \
1433 *valid = 0; \
1434 return 0; \
1435 case TYPE_Rv: \
1436 return base + index; \
1437 case TYPE_R8: \
1438 index &= mask; \
1439 if (index > 0xf) \
1440 *valid = 0; \
1441 if (insn->rexPrefix && \
1442 index >= 4 && index <= 7) { \
1443 return prefix##_SPL + (index - 4); \
1444 } else { \
1445 return prefix##_AL + index; \
1446 } \
1447 case TYPE_R16: \
1448 index &= mask; \
1449 if (index > 0xf) \
1450 *valid = 0; \
1451 return prefix##_AX + index; \
1452 case TYPE_R32: \
1453 index &= mask; \
1454 if (index > 0xf) \
1455 *valid = 0; \
1456 return prefix##_EAX + index; \
1457 case TYPE_R64: \
1458 index &= mask; \
1459 if (index > 0xf) \
1460 *valid = 0; \
1461 return prefix##_RAX + index; \
1462 case TYPE_ZMM: \
1463 return prefix##_ZMM0 + index; \
1464 case TYPE_YMM: \
1465 return prefix##_YMM0 + index; \
1466 case TYPE_XMM: \
1467 return prefix##_XMM0 + index; \
1468 case TYPE_VK: \
1469 index &= 0xf; \
1470 if (index > 7) \
1471 *valid = 0; \
1472 return prefix##_K0 + index; \
1473 case TYPE_MM64: \
1474 return prefix##_MM0 + (index & 0x7); \
1475 case TYPE_SEGMENTREG: \
1476 if ((index & 7) > 5) \
1477 *valid = 0; \
1478 return prefix##_ES + (index & 7); \
1479 case TYPE_DEBUGREG: \
1480 return prefix##_DR0 + index; \
1481 case TYPE_CONTROLREG: \
1482 return prefix##_CR0 + index; \
1483 case TYPE_BNDR: \
1484 if (index > 3) \
1485 *valid = 0; \
1486 return prefix##_BND0 + index; \
1487 case TYPE_MVSIBX: \
1488 return prefix##_XMM0 + index; \
1489 case TYPE_MVSIBY: \
1490 return prefix##_YMM0 + index; \
1491 case TYPE_MVSIBZ: \
1492 return prefix##_ZMM0 + index; \
1493 } \
1494 }
1495
1496 /*
1497 * fixup*Value - Consults an operand type to determine the meaning of the
1498 * reg or R/M field. If the operand is an XMM operand, for example, an
1499 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1500 * misinterpret it as.
1501 *
1502 * @param insn - The instruction containing the operand.
1503 * @param type - The operand type.
1504 * @param index - The existing value of the field as reported by readModRM().
1505 * @param valid - The address of a uint8_t. The target is set to 1 if the
1506 * field is valid for the register class; 0 if not.
1507 * @return - The proper value.
1508 */
1509 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG, 0x1f)
1510 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG, 0xf)
1511
1512 /*
1513 * fixupReg - Consults an operand specifier to determine which of the
1514 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1515 *
1516 * @param insn - See fixup*Value().
1517 * @param op - The operand specifier.
1518 * @return - 0 if fixup was successful; -1 if the register returned was
1519 * invalid for its class.
1520 */
fixupReg(struct InternalInstruction * insn,const struct OperandSpecifier * op)1521 static int fixupReg(struct InternalInstruction *insn,
1522 const struct OperandSpecifier *op) {
1523 uint8_t valid;
1524
1525 dbgprintf(insn, "fixupReg()");
1526
1527 switch ((OperandEncoding)op->encoding) {
1528 default:
1529 debug("Expected a REG or R/M encoding in fixupReg");
1530 return -1;
1531 case ENCODING_VVVV:
1532 insn->vvvv = (Reg)fixupRegValue(insn,
1533 (OperandType)op->type,
1534 insn->vvvv,
1535 &valid);
1536 if (!valid)
1537 return -1;
1538 break;
1539 case ENCODING_REG:
1540 insn->reg = (Reg)fixupRegValue(insn,
1541 (OperandType)op->type,
1542 insn->reg - insn->regBase,
1543 &valid);
1544 if (!valid)
1545 return -1;
1546 break;
1547 CASE_ENCODING_RM:
1548 if (insn->eaBase >= insn->eaRegBase) {
1549 insn->eaBase = (EABase)fixupRMValue(insn,
1550 (OperandType)op->type,
1551 insn->eaBase - insn->eaRegBase,
1552 &valid);
1553 if (!valid)
1554 return -1;
1555 }
1556 break;
1557 }
1558
1559 return 0;
1560 }
1561
1562 /*
1563 * readOpcodeRegister - Reads an operand from the opcode field of an
1564 * instruction and interprets it appropriately given the operand width.
1565 * Handles AddRegFrm instructions.
1566 *
1567 * @param insn - the instruction whose opcode field is to be read.
1568 * @param size - The width (in bytes) of the register being specified.
1569 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1570 * RAX.
1571 * @return - 0 on success; nonzero otherwise.
1572 */
readOpcodeRegister(struct InternalInstruction * insn,uint8_t size)1573 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1574 dbgprintf(insn, "readOpcodeRegister()");
1575
1576 if (size == 0)
1577 size = insn->registerSize;
1578
1579 switch (size) {
1580 case 1:
1581 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1582 | (insn->opcode & 7)));
1583 if (insn->rexPrefix &&
1584 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1585 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1586 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1587 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1588 }
1589
1590 break;
1591 case 2:
1592 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1593 + ((bFromREX(insn->rexPrefix) << 3)
1594 | (insn->opcode & 7)));
1595 break;
1596 case 4:
1597 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1598 + ((bFromREX(insn->rexPrefix) << 3)
1599 | (insn->opcode & 7)));
1600 break;
1601 case 8:
1602 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1603 + ((bFromREX(insn->rexPrefix) << 3)
1604 | (insn->opcode & 7)));
1605 break;
1606 }
1607
1608 return 0;
1609 }
1610
1611 /*
1612 * readImmediate - Consumes an immediate operand from an instruction, given the
1613 * desired operand size.
1614 *
1615 * @param insn - The instruction whose operand is to be read.
1616 * @param size - The width (in bytes) of the operand.
1617 * @return - 0 if the immediate was successfully consumed; nonzero
1618 * otherwise.
1619 */
readImmediate(struct InternalInstruction * insn,uint8_t size)1620 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1621 uint8_t imm8;
1622 uint16_t imm16;
1623 uint32_t imm32;
1624 uint64_t imm64;
1625
1626 dbgprintf(insn, "readImmediate()");
1627
1628 if (insn->numImmediatesConsumed == 2) {
1629 debug("Already consumed two immediates");
1630 return -1;
1631 }
1632
1633 if (size == 0)
1634 size = insn->immediateSize;
1635 else
1636 insn->immediateSize = size;
1637 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1638
1639 switch (size) {
1640 case 1:
1641 if (consumeByte(insn, &imm8))
1642 return -1;
1643 insn->immediates[insn->numImmediatesConsumed] = imm8;
1644 break;
1645 case 2:
1646 if (consumeUInt16(insn, &imm16))
1647 return -1;
1648 insn->immediates[insn->numImmediatesConsumed] = imm16;
1649 break;
1650 case 4:
1651 if (consumeUInt32(insn, &imm32))
1652 return -1;
1653 insn->immediates[insn->numImmediatesConsumed] = imm32;
1654 break;
1655 case 8:
1656 if (consumeUInt64(insn, &imm64))
1657 return -1;
1658 insn->immediates[insn->numImmediatesConsumed] = imm64;
1659 break;
1660 }
1661
1662 insn->numImmediatesConsumed++;
1663
1664 return 0;
1665 }
1666
1667 /*
1668 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1669 *
1670 * @param insn - The instruction whose operand is to be read.
1671 * @return - 0 if the vvvv was successfully consumed; nonzero
1672 * otherwise.
1673 */
readVVVV(struct InternalInstruction * insn)1674 static int readVVVV(struct InternalInstruction* insn) {
1675 dbgprintf(insn, "readVVVV()");
1676
1677 int vvvv;
1678 if (insn->vectorExtensionType == TYPE_EVEX)
1679 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1680 vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]));
1681 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1682 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1683 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1684 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1685 else if (insn->vectorExtensionType == TYPE_XOP)
1686 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1687 else
1688 return -1;
1689
1690 if (insn->mode != MODE_64BIT)
1691 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1692
1693 insn->vvvv = static_cast<Reg>(vvvv);
1694 return 0;
1695 }
1696
1697 /*
1698 * readMaskRegister - Reads an mask register from the opcode field of an
1699 * instruction.
1700 *
1701 * @param insn - The instruction whose opcode field is to be read.
1702 * @return - 0 on success; nonzero otherwise.
1703 */
readMaskRegister(struct InternalInstruction * insn)1704 static int readMaskRegister(struct InternalInstruction* insn) {
1705 dbgprintf(insn, "readMaskRegister()");
1706
1707 if (insn->vectorExtensionType != TYPE_EVEX)
1708 return -1;
1709
1710 insn->writemask =
1711 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1712 return 0;
1713 }
1714
1715 /*
1716 * readOperands - Consults the specifier for an instruction and consumes all
1717 * operands for that instruction, interpreting them as it goes.
1718 *
1719 * @param insn - The instruction whose operands are to be read and interpreted.
1720 * @return - 0 if all operands could be read; nonzero otherwise.
1721 */
readOperands(struct InternalInstruction * insn)1722 static int readOperands(struct InternalInstruction* insn) {
1723 int hasVVVV, needVVVV;
1724 int sawRegImm = 0;
1725
1726 dbgprintf(insn, "readOperands()");
1727
1728 /* If non-zero vvvv specified, need to make sure one of the operands
1729 uses it. */
1730 hasVVVV = !readVVVV(insn);
1731 needVVVV = hasVVVV && (insn->vvvv != 0);
1732
1733 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1734 switch (Op.encoding) {
1735 case ENCODING_NONE:
1736 case ENCODING_SI:
1737 case ENCODING_DI:
1738 break;
1739 CASE_ENCODING_VSIB:
1740 // VSIB can use the V2 bit so check only the other bits.
1741 if (needVVVV)
1742 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1743 if (readModRM(insn))
1744 return -1;
1745
1746 // Reject if SIB wasn't used.
1747 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1748 return -1;
1749
1750 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1751 if (insn->sibIndex == SIB_INDEX_NONE)
1752 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4);
1753
1754 // If EVEX.v2 is set this is one of the 16-31 registers.
1755 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
1756 v2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
1757 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1758
1759 // Adjust the index register to the correct size.
1760 switch ((OperandType)Op.type) {
1761 default:
1762 debug("Unhandled VSIB index type");
1763 return -1;
1764 case TYPE_MVSIBX:
1765 insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 +
1766 (insn->sibIndex - insn->sibIndexBase));
1767 break;
1768 case TYPE_MVSIBY:
1769 insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 +
1770 (insn->sibIndex - insn->sibIndexBase));
1771 break;
1772 case TYPE_MVSIBZ:
1773 insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 +
1774 (insn->sibIndex - insn->sibIndexBase));
1775 break;
1776 }
1777
1778 // Apply the AVX512 compressed displacement scaling factor.
1779 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1780 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1781 break;
1782 case ENCODING_REG:
1783 CASE_ENCODING_RM:
1784 if (readModRM(insn))
1785 return -1;
1786 if (fixupReg(insn, &Op))
1787 return -1;
1788 // Apply the AVX512 compressed displacement scaling factor.
1789 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1790 insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1791 break;
1792 case ENCODING_IB:
1793 if (sawRegImm) {
1794 /* Saw a register immediate so don't read again and instead split the
1795 previous immediate. FIXME: This is a hack. */
1796 insn->immediates[insn->numImmediatesConsumed] =
1797 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1798 ++insn->numImmediatesConsumed;
1799 break;
1800 }
1801 if (readImmediate(insn, 1))
1802 return -1;
1803 if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1804 sawRegImm = 1;
1805 break;
1806 case ENCODING_IW:
1807 if (readImmediate(insn, 2))
1808 return -1;
1809 break;
1810 case ENCODING_ID:
1811 if (readImmediate(insn, 4))
1812 return -1;
1813 break;
1814 case ENCODING_IO:
1815 if (readImmediate(insn, 8))
1816 return -1;
1817 break;
1818 case ENCODING_Iv:
1819 if (readImmediate(insn, insn->immediateSize))
1820 return -1;
1821 break;
1822 case ENCODING_Ia:
1823 if (readImmediate(insn, insn->addressSize))
1824 return -1;
1825 break;
1826 case ENCODING_IRC:
1827 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1828 lFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1829 break;
1830 case ENCODING_RB:
1831 if (readOpcodeRegister(insn, 1))
1832 return -1;
1833 break;
1834 case ENCODING_RW:
1835 if (readOpcodeRegister(insn, 2))
1836 return -1;
1837 break;
1838 case ENCODING_RD:
1839 if (readOpcodeRegister(insn, 4))
1840 return -1;
1841 break;
1842 case ENCODING_RO:
1843 if (readOpcodeRegister(insn, 8))
1844 return -1;
1845 break;
1846 case ENCODING_Rv:
1847 if (readOpcodeRegister(insn, 0))
1848 return -1;
1849 break;
1850 case ENCODING_FP:
1851 break;
1852 case ENCODING_VVVV:
1853 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1854 if (!hasVVVV)
1855 return -1;
1856 if (insn->mode != MODE_64BIT)
1857 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1858 if (fixupReg(insn, &Op))
1859 return -1;
1860 break;
1861 case ENCODING_WRITEMASK:
1862 if (readMaskRegister(insn))
1863 return -1;
1864 break;
1865 case ENCODING_DUP:
1866 break;
1867 default:
1868 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1869 return -1;
1870 }
1871 }
1872
1873 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1874 if (needVVVV) return -1;
1875
1876 return 0;
1877 }
1878
1879 /*
1880 * decodeInstruction - Reads and interprets a full instruction provided by the
1881 * user.
1882 *
1883 * @param insn - A pointer to the instruction to be populated. Must be
1884 * pre-allocated.
1885 * @param reader - The function to be used to read the instruction's bytes.
1886 * @param readerArg - A generic argument to be passed to the reader to store
1887 * any internal state.
1888 * @param logger - If non-NULL, the function to be used to write log messages
1889 * and warnings.
1890 * @param loggerArg - A generic argument to be passed to the logger to store
1891 * any internal state.
1892 * @param startLoc - The address (in the reader's address space) of the first
1893 * byte in the instruction.
1894 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1895 * decode the instruction in.
1896 * @return - 0 if the instruction's memory could be read; nonzero if
1897 * not.
1898 */
decodeInstruction(struct InternalInstruction * insn,byteReader_t reader,const void * readerArg,dlog_t logger,void * loggerArg,const void * miiArg,uint64_t startLoc,DisassemblerMode mode)1899 int llvm::X86Disassembler::decodeInstruction(
1900 struct InternalInstruction *insn, byteReader_t reader,
1901 const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1902 uint64_t startLoc, DisassemblerMode mode) {
1903 memset(insn, 0, sizeof(struct InternalInstruction));
1904
1905 insn->reader = reader;
1906 insn->readerArg = readerArg;
1907 insn->dlog = logger;
1908 insn->dlogArg = loggerArg;
1909 insn->startLocation = startLoc;
1910 insn->readerCursor = startLoc;
1911 insn->mode = mode;
1912 insn->numImmediatesConsumed = 0;
1913
1914 if (readPrefixes(insn) ||
1915 readOpcode(insn) ||
1916 getID(insn, miiArg) ||
1917 insn->instructionID == 0 ||
1918 readOperands(insn))
1919 return -1;
1920
1921 insn->operands = x86OperandSets[insn->spec->operands];
1922
1923 insn->length = insn->readerCursor - insn->startLocation;
1924
1925 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1926 startLoc, insn->readerCursor, insn->length);
1927
1928 if (insn->length > 15)
1929 dbgprintf(insn, "Instruction exceeds 15-byte limit");
1930
1931 return 0;
1932 }
1933