1 //===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands the pseudo instruction pseudolisimm32
10 // into target instructions. This pass should be run during the post-regalloc
11 // passes, before post RA scheduling.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "MCTargetDesc/RISCVMatInt.h"
16 #include "RISCV.h"
17 #include "RISCVInstrInfo.h"
18 #include "RISCVTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21
22 using namespace llvm;
23
24 #define RISCV_POST_RA_EXPAND_PSEUDO_NAME \
25 "RISC-V post-regalloc pseudo instruction expansion pass"
26
27 namespace {
28
29 class RISCVPostRAExpandPseudo : public MachineFunctionPass {
30 public:
31 const RISCVInstrInfo *TII;
32 static char ID;
33
RISCVPostRAExpandPseudo()34 RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {
35 initializeRISCVPostRAExpandPseudoPass(*PassRegistry::getPassRegistry());
36 }
37
38 bool runOnMachineFunction(MachineFunction &MF) override;
39
getPassName() const40 StringRef getPassName() const override {
41 return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
42 }
43
44 private:
45 bool expandMBB(MachineBasicBlock &MBB);
46 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
47 MachineBasicBlock::iterator &NextMBBI);
48 bool expandMovImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
49 };
50
51 char RISCVPostRAExpandPseudo::ID = 0;
52
runOnMachineFunction(MachineFunction & MF)53 bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
54 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
55 bool Modified = false;
56 for (auto &MBB : MF)
57 Modified |= expandMBB(MBB);
58 return Modified;
59 }
60
expandMBB(MachineBasicBlock & MBB)61 bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
62 bool Modified = false;
63
64 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
65 while (MBBI != E) {
66 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
67 Modified |= expandMI(MBB, MBBI, NMBBI);
68 MBBI = NMBBI;
69 }
70
71 return Modified;
72 }
73
expandMI(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,MachineBasicBlock::iterator & NextMBBI)74 bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator MBBI,
76 MachineBasicBlock::iterator &NextMBBI) {
77 switch (MBBI->getOpcode()) {
78 case RISCV::PseudoMovImm:
79 return expandMovImm(MBB, MBBI);
80 default:
81 return false;
82 }
83 }
84
expandMovImm(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI)85 bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI) {
87 DebugLoc DL = MBBI->getDebugLoc();
88
89 int64_t Val = MBBI->getOperand(1).getImm();
90
91 RISCVMatInt::InstSeq Seq =
92 RISCVMatInt::generateInstSeq(Val, MBB.getParent()->getSubtarget());
93 assert(!Seq.empty());
94
95 Register DstReg = MBBI->getOperand(0).getReg();
96 bool DstIsDead = MBBI->getOperand(0).isDead();
97 bool Renamable = MBBI->getOperand(0).isRenamable();
98
99 TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable,
100 DstIsDead);
101
102 MBBI->eraseFromParent();
103 return true;
104 }
105
106 } // end of anonymous namespace
107
108 INITIALIZE_PASS(RISCVPostRAExpandPseudo, "riscv-expand-pseudolisimm32",
109 RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
110 namespace llvm {
111
createRISCVPostRAExpandPseudoPass()112 FunctionPass *createRISCVPostRAExpandPseudoPass() {
113 return new RISCVPostRAExpandPseudo();
114 }
115
116 } // end of namespace llvm
117