1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14// The callseq_start node requires the hasSideEffects flag, even though these 15// instructions are noops on SystemZ. 16let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 17 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_start timm:$amt1, timm:$amt2)]>; 19 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_end timm:$amt1, timm:$amt2)]>; 21} 22 23// Takes as input the value of the stack pointer after a dynamic allocation 24// has been made. Sets the output to the address of the dynamically- 25// allocated area itself, skipping the outgoing arguments. 26// 27// This expands to an LA or LAY instruction. We restrict the offset 28// to the range of LA and keep the LAY range in reserve for when 29// the size of the outgoing arguments is added. 30def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 31 [(set GR64:$dst, dynalloc12only:$src)]>; 32 33 34//===----------------------------------------------------------------------===// 35// Branch instructions 36//===----------------------------------------------------------------------===// 37 38// Conditional branches. 39let isBranch = 1, isTerminator = 1, Uses = [CC] in { 40 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 41 // with the condition-code mask being the first operand. It seems friendlier 42 // to use mnemonic forms like JE and JLH when writing out the assembly though. 43 let isCodeGenOnly = 1 in { 44 // An assembler extended mnemonic for BRC. 45 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 46 // An assembler extended mnemonic for BRCL. (The extension is "G" 47 // rather than "L" because "JL" is "Jump if Less".) 48 def BRCL : CondBranchRIL<"jg#", 0xC04>; 49 let isIndirectBranch = 1 in { 50 def BC : CondBranchRX<"b#", 0x47>; 51 def BCR : CondBranchRR<"b#r", 0x07>; 52 def BIC : CondBranchRXY<"bi#", 0xe347>, 53 Requires<[FeatureMiscellaneousExtensions2]>; 54 } 55 } 56 57 // Allow using the raw forms directly from the assembler (and occasional 58 // special code generation needs) as well. 59 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 60 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 61 let isIndirectBranch = 1 in { 62 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 63 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 64 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 65 Requires<[FeatureMiscellaneousExtensions2]>; 66 } 67 68 // Define AsmParser extended mnemonics for each general condition-code mask 69 // (integer or floating-point) 70 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 71 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 72 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 73 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 74 let isIndirectBranch = 1 in { 75 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 76 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 77 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 78 Requires<[FeatureMiscellaneousExtensions2]>; 79 } 80 } 81} 82 83// Unconditional branches. These are in fact simply variants of the 84// conditional branches with the condition mask set to "always". 85let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 86 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 87 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 88 let isIndirectBranch = 1 in { 89 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 90 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 91 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 92 Requires<[FeatureMiscellaneousExtensions2]>; 93 } 94} 95 96// NOPs. These are again variants of the conditional branches, 97// with the condition mask set to "never". 98def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 99def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 100 101// Fused compare-and-branch instructions. 102// 103// These instructions do not use or clobber the condition codes. 104// We nevertheless pretend that the relative compare-and-branch 105// instructions clobber CC, so that we can lower them to separate 106// comparisons and BRCLs if the branch ends up being out of range. 107let isBranch = 1, isTerminator = 1 in { 108 // As for normal branches, we handle these instructions internally in 109 // their raw CRJ-like form, but use assembly macros like CRJE when writing 110 // them out. Using the *Pair multiclasses, we also create the raw forms. 111 let Defs = [CC] in { 112 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 113 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 114 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 115 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 116 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 117 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 118 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 119 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 120 } 121 let isIndirectBranch = 1 in { 122 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 123 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 124 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 125 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 126 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 127 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 128 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 129 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 130 } 131 132 // Define AsmParser mnemonics for each integer condition-code mask. 133 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 134 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 135 let Defs = [CC] in { 136 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 137 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 138 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 139 imm32sx8>; 140 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 141 imm64sx8>; 142 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 143 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 144 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 145 imm32zx8>; 146 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 147 imm64zx8>; 148 } 149 let isIndirectBranch = 1 in { 150 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 151 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 152 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 153 imm32sx8>; 154 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 155 imm64sx8>; 156 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 157 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 158 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 159 imm32zx8>; 160 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 161 imm64zx8>; 162 } 163 } 164} 165 166// Decrement a register and branch if it is nonzero. These don't clobber CC, 167// but we might need to split long relative branches into sequences that do. 168let isBranch = 1, isTerminator = 1 in { 169 let Defs = [CC] in { 170 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 171 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 172 } 173 // This doesn't need to clobber CC since we never need to split it. 174 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 175 Requires<[FeatureHighWord]>; 176 177 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 178 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 179 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 180 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 181} 182 183let isBranch = 1, isTerminator = 1 in { 184 let Defs = [CC] in { 185 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 186 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 187 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 188 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 189 } 190 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 191 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 192 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 193 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 194} 195 196//===----------------------------------------------------------------------===// 197// Trap instructions 198//===----------------------------------------------------------------------===// 199 200// Unconditional trap. 201let hasCtrlDep = 1, hasSideEffects = 1 in 202 def Trap : Alias<4, (outs), (ins), [(trap)]>; 203 204// Conditional trap. 205let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 206 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 207 208// Fused compare-and-trap instructions. 209let hasCtrlDep = 1, hasSideEffects = 1 in { 210 // These patterns work the same way as for compare-and-branch. 211 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 212 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 213 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 214 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 215 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 216 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 217 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 218 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 219 let Predicates = [FeatureMiscellaneousExtensions] in { 220 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 221 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 222 } 223 224 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 225 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 226 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 227 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 228 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 229 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 230 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 231 imm32sx16>; 232 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 233 imm64sx16>; 234 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 235 imm32zx16>; 236 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 237 imm64zx16>; 238 let Predicates = [FeatureMiscellaneousExtensions] in { 239 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 240 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 241 } 242 } 243} 244 245//===----------------------------------------------------------------------===// 246// Call and return instructions 247//===----------------------------------------------------------------------===// 248 249// Define the general form of the call instructions for the asm parser. 250// These instructions don't hard-code %r14 as the return address register. 251let isCall = 1, Defs = [CC] in { 252 def BRAS : CallRI <"bras", 0xA75>; 253 def BRASL : CallRIL<"brasl", 0xC05>; 254 def BAS : CallRX <"bas", 0x4D>; 255 def BASR : CallRR <"basr", 0x0D>; 256} 257 258// Regular calls. 259let isCall = 1, Defs = [R14D, CC] in { 260 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 261 [(z_call pcrel32:$I2)]>; 262 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 263 [(z_call ADDR64:$R2)]>; 264} 265 266// TLS calls. These will be lowered into a call to __tls_get_offset, 267// with an extra relocation specifying the TLS symbol. 268let isCall = 1, Defs = [R14D, CC] in { 269 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 270 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 271 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 272 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 273} 274 275// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 276// are argument registers and since branching to R0 is a no-op. 277let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 278 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 279 [(z_sibcall pcrel32:$I2)]>; 280 let Uses = [R1D] in 281 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 282} 283 284// Conditional sibling calls. 285let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 286 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 287 pcrel32:$I2), []>; 288 let Uses = [R1D] in 289 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 290} 291 292// Fused compare and conditional sibling calls. 293let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 294 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 295 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 296 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 297 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 298 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 299 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 300 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 301 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 302} 303 304// A return instruction (br %r14). 305let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 306 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 307 308// A conditional return instruction (bcr <cond>, %r14). 309let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 310 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 311 312// Fused compare and conditional returns. 313let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 314 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 315 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 316 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 317 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 318 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 319 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 320 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 321 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 322} 323 324//===----------------------------------------------------------------------===// 325// Select instructions 326//===----------------------------------------------------------------------===// 327 328def Select32 : SelectWrapper<i32, GR32>, 329 Requires<[FeatureNoLoadStoreOnCond]>; 330def Select64 : SelectWrapper<i64, GR64>, 331 Requires<[FeatureNoLoadStoreOnCond]>; 332 333// We don't define 32-bit Mux stores if we don't have STOCFH, because the 334// low-only STOC should then always be used if possible. 335defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 336 nonvolatile_anyextloadi8, bdxaddr20only>, 337 Requires<[FeatureHighWord]>; 338defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 339 nonvolatile_anyextloadi16, bdxaddr20only>, 340 Requires<[FeatureHighWord]>; 341defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 342 nonvolatile_load, bdxaddr20only>, 343 Requires<[FeatureLoadStoreOnCond2]>; 344defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 345 nonvolatile_anyextloadi8, bdxaddr20only>; 346defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 347 nonvolatile_anyextloadi16, bdxaddr20only>; 348defm CondStore32 : CondStores<GR32, nonvolatile_store, 349 nonvolatile_load, bdxaddr20only>; 350 351defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 352 nonvolatile_anyextloadi8, bdxaddr20only>; 353defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 354 nonvolatile_anyextloadi16, bdxaddr20only>; 355defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 356 nonvolatile_anyextloadi32, bdxaddr20only>; 357defm CondStore64 : CondStores<GR64, nonvolatile_store, 358 nonvolatile_load, bdxaddr20only>; 359 360//===----------------------------------------------------------------------===// 361// Move instructions 362//===----------------------------------------------------------------------===// 363 364// Register moves. 365// Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 366def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 367 Requires<[FeatureHighWord]>; 368def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 369def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 370 371let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 372 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 373 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 374} 375 376let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 377 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 378 379// Immediate moves. 380let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 381 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 382 // deopending on the choice of register. 383 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 384 Requires<[FeatureHighWord]>; 385 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 386 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 387 388 // Other 16-bit immediates. 389 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 390 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 391 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 392 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 393 394 // 32-bit immediates. 395 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 396 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 397 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 398} 399 400// Register loads. 401let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 402 // Expands to L, LY or LFH, depending on the choice of register. 403 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 404 Requires<[FeatureHighWord]>; 405 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 406 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 407 Requires<[FeatureHighWord]>; 408 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 409 410 // These instructions are split after register allocation, so we don't 411 // want a custom inserter. 412 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 413 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 414 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 415 } 416} 417let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 418 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 419 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 420} 421 422let canFoldAsLoad = 1 in { 423 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 424 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 425} 426 427// Load and zero rightmost byte. 428let Predicates = [FeatureLoadAndZeroRightmostByte] in { 429 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 430 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 431 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 432 (LZRF bdxaddr20only:$src)>; 433 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 434 (LZRG bdxaddr20only:$src)>; 435} 436 437// Load and trap. 438let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 439 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 440 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 441 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 442} 443 444// Register stores. 445let SimpleBDXStore = 1, mayStore = 1 in { 446 // Expands to ST, STY or STFH, depending on the choice of register. 447 def STMux : StoreRXYPseudo<store, GRX32, 4>, 448 Requires<[FeatureHighWord]>; 449 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 450 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 451 Requires<[FeatureHighWord]>; 452 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 453 454 // These instructions are split after register allocation, so we don't 455 // want a custom inserter. 456 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 457 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 458 [(store GR128:$src, bdxaddr20only128:$dst)]>; 459 } 460} 461def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 462def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 463 464// 8-bit immediate stores to 8-bit fields. 465defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 466 467// 16-bit immediate stores to 16-, 32- or 64-bit fields. 468def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 469def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 470def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 471 472// Memory-to-memory moves. 473let mayLoad = 1, mayStore = 1 in 474 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 475let mayLoad = 1, mayStore = 1, Defs = [CC] in { 476 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 477 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 478 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 479} 480 481// String moves. 482let mayLoad = 1, mayStore = 1, Defs = [CC] in 483 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 484 485//===----------------------------------------------------------------------===// 486// Conditional move instructions 487//===----------------------------------------------------------------------===// 488 489let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 490 // Load immediate on condition. Matched via DAG pattern and created 491 // by the PeepholeOptimizer via FoldImmediate. 492 493 // Expands to LOCHI or LOCHHI, depending on the choice of register. 494 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 495 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 496 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 497 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 498 499 // Move register on condition. Matched via DAG pattern and 500 // created by early if-conversion. 501 let isCommutable = 1 in { 502 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 503 // depending on the choice of registers. 504 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 505 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 506 } 507 508 // Load on condition. Matched via DAG pattern. 509 // Expands to LOC or LOCFH, depending on the choice of register. 510 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 511 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 512 513 // Store on condition. Expanded from CondStore* pseudos. 514 // Expands to STOC or STOCFH, depending on the choice of register. 515 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 516 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 517 518 // Define AsmParser extended mnemonics for each general condition-code mask. 519 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 520 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 521 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 522 imm32sx16>; 523 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 524 imm64sx16>; 525 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 526 imm32sx16>; 527 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 528 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 529 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 530 } 531} 532 533let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 534 // Move register on condition. Matched via DAG pattern and 535 // created by early if-conversion. 536 let isCommutable = 1 in { 537 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 538 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 539 } 540 541 // Load on condition. Matched via DAG pattern. 542 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 543 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 544 545 // Store on condition. Expanded from CondStore* pseudos. 546 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 547 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 548 549 // Define AsmParser extended mnemonics for each general condition-code mask. 550 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 551 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 552 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 553 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 554 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 555 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 556 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 557 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 558 } 559} 560//===----------------------------------------------------------------------===// 561// Sign extensions 562//===----------------------------------------------------------------------===// 563// 564// Note that putting these before zero extensions mean that we will prefer 565// them for anyextload*. There's not really much to choose between the two 566// either way, but signed-extending loads have a short LH and a long LHY, 567// while zero-extending loads have only the long LLH. 568// 569//===----------------------------------------------------------------------===// 570 571// 32-bit extensions from registers. 572def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 573def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 574 575// 64-bit extensions from registers. 576def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 577def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 578def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 579 580let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 581 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 582 583// Match 32-to-64-bit sign extensions in which the source is already 584// in a 64-bit register. 585def : Pat<(sext_inreg GR64:$src, i32), 586 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 587 588// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 589// depending on the choice of register. 590def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 591 Requires<[FeatureHighWord]>; 592def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 593def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 594 Requires<[FeatureHighWord]>; 595 596// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 597// depending on the choice of register. 598def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 599 Requires<[FeatureHighWord]>; 600defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 601def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 602 Requires<[FeatureHighWord]>; 603def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 604 605// 64-bit extensions from memory. 606def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 607def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 608def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 609def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 610def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 611let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 612 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 613 614//===----------------------------------------------------------------------===// 615// Zero extensions 616//===----------------------------------------------------------------------===// 617 618// 32-bit extensions from registers. 619 620// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 621def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 622 Requires<[FeatureHighWord]>; 623def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 624// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 625def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 626 Requires<[FeatureHighWord]>; 627def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 628 629// 64-bit extensions from registers. 630def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 631def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 632def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 633 634// Match 32-to-64-bit zero extensions in which the source is already 635// in a 64-bit register. 636def : Pat<(and GR64:$src, 0xffffffff), 637 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 638 639// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 640// depending on the choice of register. 641def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 642 Requires<[FeatureHighWord]>; 643def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 644def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 645 Requires<[FeatureHighWord]>; 646 647// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 648// depending on the choice of register. 649def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 650 Requires<[FeatureHighWord]>; 651def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 652def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 653 Requires<[FeatureHighWord]>; 654def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 655 656// 64-bit extensions from memory. 657def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 658def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 659def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 660def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 661def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 662 663// 31-to-64-bit zero extensions. 664def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 665def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 666def : Pat<(and GR64:$src, 0x7fffffff), 667 (LLGTR GR64:$src)>; 668def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 669 (LLGT bdxaddr20only:$src)>; 670 671// Load and zero rightmost byte. 672let Predicates = [FeatureLoadAndZeroRightmostByte] in { 673 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 674 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 675 (LLZRGF bdxaddr20only:$src)>; 676} 677 678// Load and trap. 679let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 680 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 681 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 682} 683 684// Extend GR64s to GR128s. 685let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 686 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 687 688//===----------------------------------------------------------------------===// 689// "Any" extensions 690//===----------------------------------------------------------------------===// 691 692// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 693def : Pat<(i64 (anyext GR32:$src)), 694 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 695 696// Extend GR64s to GR128s. 697let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 698 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 699 700//===----------------------------------------------------------------------===// 701// Truncations 702//===----------------------------------------------------------------------===// 703 704// Truncations of 64-bit registers to 32-bit registers. 705def : Pat<(i32 (trunc GR64:$src)), 706 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 707 708// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 709// STC, STCY or STCH, depending on the choice of register. 710def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 711 Requires<[FeatureHighWord]>; 712defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 713def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 714 Requires<[FeatureHighWord]>; 715 716// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 717// STH, STHY or STHH, depending on the choice of register. 718def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 719 Requires<[FeatureHighWord]>; 720defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 721def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 722 Requires<[FeatureHighWord]>; 723def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 724 725// Truncations of 64-bit registers to memory. 726defm : StoreGR64Pair<STC, STCY, truncstorei8>; 727defm : StoreGR64Pair<STH, STHY, truncstorei16>; 728def : StoreGR64PC<STHRL, aligned_truncstorei16>; 729defm : StoreGR64Pair<ST, STY, truncstorei32>; 730def : StoreGR64PC<STRL, aligned_truncstorei32>; 731 732// Store characters under mask -- not (yet) used for codegen. 733defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 734def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 735 736//===----------------------------------------------------------------------===// 737// Multi-register moves 738//===----------------------------------------------------------------------===// 739 740// Multi-register loads. 741defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 742def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 743def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 744def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 745 746// Multi-register stores. 747defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 748def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 749def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 750 751//===----------------------------------------------------------------------===// 752// Byte swaps 753//===----------------------------------------------------------------------===// 754 755// Byte-swapping register moves. 756def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 757def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 758 759// Byte-swapping loads. 760def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 761def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 762def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 763 764// Byte-swapping stores. 765def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 766def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 767def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 768 769// Byte-swapping memory-to-memory moves. 770let mayLoad = 1, mayStore = 1 in 771 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 772 773//===----------------------------------------------------------------------===// 774// Load address instructions 775//===----------------------------------------------------------------------===// 776 777// Load BDX-style addresses. 778let isAsCheapAsAMove = 1, isReMaterializable = 1 in 779 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 780 781// Load a PC-relative address. There's no version of this instruction 782// with a 16-bit offset, so there's no relaxation. 783let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 784 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 785 786// Load the Global Offset Table address. This will be lowered into a 787// larl $R1, _GLOBAL_OFFSET_TABLE_ 788// instruction. 789def GOT : Alias<6, (outs GR64:$R1), (ins), 790 [(set GR64:$R1, (global_offset_table))]>; 791 792//===----------------------------------------------------------------------===// 793// Absolute and Negation 794//===----------------------------------------------------------------------===// 795 796let Defs = [CC] in { 797 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 798 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 799 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 800 } 801 let CCValues = 0xE, CompareZeroCCMask = 0xE in 802 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 803} 804def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 805def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 806defm : SXU<z_iabs, LPGFR>; 807defm : SXU<z_iabs64, LPGFR>; 808 809let Defs = [CC] in { 810 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 811 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 812 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 813 } 814 let CCValues = 0xE, CompareZeroCCMask = 0xE in 815 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 816} 817def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 818def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 819defm : SXU<z_inegabs, LNGFR>; 820defm : SXU<z_inegabs64, LNGFR>; 821 822let Defs = [CC] in { 823 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 824 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 825 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 826 } 827 let CCValues = 0xE, CompareZeroCCMask = 0xE in 828 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 829} 830defm : SXU<ineg, LCGFR>; 831 832//===----------------------------------------------------------------------===// 833// Insertion 834//===----------------------------------------------------------------------===// 835 836let isCodeGenOnly = 1 in 837 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 838defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 839 840defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 841defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 842 843defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 844defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 845 846// Insert characters under mask -- not (yet) used for codegen. 847let Defs = [CC] in { 848 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 849 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 850} 851 852// Insertions of a 16-bit immediate, leaving other bits unaffected. 853// We don't have or_as_insert equivalents of these operations because 854// OI is available instead. 855// 856// IIxMux expands to II[LH]x, depending on the choice of register. 857def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 858 Requires<[FeatureHighWord]>; 859def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 860 Requires<[FeatureHighWord]>; 861def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 862def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 863def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 864def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 865def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 866def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 867def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 868def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 869 870// ...likewise for 32-bit immediates. For GR32s this is a general 871// full-width move. (We use IILF rather than something like LLILF 872// for 32-bit moves because IILF leaves the upper 32 bits of the 873// GR64 unchanged.) 874let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 875 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 876 Requires<[FeatureHighWord]>; 877 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 878 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 879} 880def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 881def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 882 883// An alternative model of inserthf, with the first operand being 884// a zero-extended value. 885def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 886 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 887 imm64hf32:$imm)>; 888 889//===----------------------------------------------------------------------===// 890// Addition 891//===----------------------------------------------------------------------===// 892 893// Addition producing a signed overflow flag. 894let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 895 // Addition of a register. 896 let isCommutable = 1 in { 897 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 898 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 899 } 900 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 901 902 // Addition to a high register. 903 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 904 Requires<[FeatureHighWord]>; 905 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 906 Requires<[FeatureHighWord]>; 907 908 // Addition of signed 16-bit immediates. 909 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 910 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 911 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 912 913 // Addition of signed 32-bit immediates. 914 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 915 Requires<[FeatureHighWord]>; 916 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 917 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 918 Requires<[FeatureHighWord]>; 919 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 920 921 // Addition of memory. 922 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 923 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 924 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 925 Requires<[FeatureMiscellaneousExtensions2]>; 926 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 927 def AG : BinaryRXY<"ag", 0xE308, z_sadd, GR64, load, 8>; 928 929 // Addition to memory. 930 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 931 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 932} 933defm : SXB<z_sadd, GR64, AGFR>; 934 935// Addition producing a carry. 936let Defs = [CC] in { 937 // Addition of a register. 938 let isCommutable = 1 in { 939 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 940 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 941 } 942 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 943 944 // Addition to a high register. 945 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 946 Requires<[FeatureHighWord]>; 947 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 948 Requires<[FeatureHighWord]>; 949 950 // Addition of signed 16-bit immediates. 951 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 952 Requires<[FeatureDistinctOps]>; 953 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 954 Requires<[FeatureDistinctOps]>; 955 956 // Addition of unsigned 32-bit immediates. 957 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 958 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 959 960 // Addition of signed 32-bit immediates. 961 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 962 Requires<[FeatureHighWord]>; 963 964 // Addition of memory. 965 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 966 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 967 def ALG : BinaryRXY<"alg", 0xE30A, z_uadd, GR64, load, 8>; 968 969 // Addition to memory. 970 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 971 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 972} 973defm : ZXB<z_uadd, GR64, ALGFR>; 974 975// Addition producing and using a carry. 976let Defs = [CC], Uses = [CC] in { 977 // Addition of a register. 978 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 979 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 980 981 // Addition of memory. 982 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 983 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 984} 985 986// Addition that does not modify the condition code. 987def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 988 Requires<[FeatureHighWord]>; 989 990 991//===----------------------------------------------------------------------===// 992// Subtraction 993//===----------------------------------------------------------------------===// 994 995// Subtraction producing a signed overflow flag. 996let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 997 // Subtraction of a register. 998 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 999 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1000 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1001 1002 // Subtraction from a high register. 1003 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1004 Requires<[FeatureHighWord]>; 1005 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1006 Requires<[FeatureHighWord]>; 1007 1008 // Subtraction of memory. 1009 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1010 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1011 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1012 Requires<[FeatureMiscellaneousExtensions2]>; 1013 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1014 def SG : BinaryRXY<"sg", 0xE309, z_ssub, GR64, load, 8>; 1015} 1016defm : SXB<z_ssub, GR64, SGFR>; 1017 1018// Subtracting an immediate is the same as adding the negated immediate. 1019let AddedComplexity = 1 in { 1020 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1021 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1022 Requires<[FeatureHighWord]>; 1023 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1024 (AFIMux GR32:$src1, simm32n:$src2)>, 1025 Requires<[FeatureHighWord]>; 1026 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1027 (AHI GR32:$src1, imm32sx16n:$src2)>; 1028 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1029 (AFI GR32:$src1, simm32n:$src2)>; 1030 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1031 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1032 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1033 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1034} 1035 1036// Subtraction producing a carry. 1037let Defs = [CC] in { 1038 // Subtraction of a register. 1039 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1040 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1041 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1042 1043 // Subtraction from a high register. 1044 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1045 Requires<[FeatureHighWord]>; 1046 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1047 Requires<[FeatureHighWord]>; 1048 1049 // Subtraction of unsigned 32-bit immediates. 1050 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1051 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1052 1053 // Subtraction of memory. 1054 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1055 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1056 def SLG : BinaryRXY<"slg", 0xE30B, z_usub, GR64, load, 8>; 1057} 1058defm : ZXB<z_usub, GR64, SLGFR>; 1059 1060// Subtracting an immediate is the same as adding the negated immediate. 1061let AddedComplexity = 1 in { 1062 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1063 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1064 Requires<[FeatureDistinctOps]>; 1065 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1066 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1067 Requires<[FeatureDistinctOps]>; 1068} 1069 1070// And vice versa in one special case (but we prefer addition). 1071def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1072 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1073 1074// Subtraction producing and using a carry. 1075let Defs = [CC], Uses = [CC] in { 1076 // Subtraction of a register. 1077 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1078 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1079 1080 // Subtraction of memory. 1081 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1082 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1083} 1084 1085 1086//===----------------------------------------------------------------------===// 1087// AND 1088//===----------------------------------------------------------------------===// 1089 1090let Defs = [CC] in { 1091 // ANDs of a register. 1092 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1093 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1094 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1095 } 1096 1097 let isConvertibleToThreeAddress = 1 in { 1098 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1099 // The CC result only reflects the 16-bit field, not the full register. 1100 // 1101 // NIxMux expands to NI[LH]x, depending on the choice of register. 1102 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1103 Requires<[FeatureHighWord]>; 1104 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1105 Requires<[FeatureHighWord]>; 1106 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1107 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1108 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1109 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1110 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1111 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1112 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1113 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1114 1115 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1116 // The CC result only reflects the 32-bit field, which means we can 1117 // use it as a zero indicator for i32 operations but not otherwise. 1118 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1119 // Expands to NILF or NIHF, depending on the choice of register. 1120 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1121 Requires<[FeatureHighWord]>; 1122 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1123 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1124 } 1125 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1126 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1127 } 1128 1129 // ANDs of memory. 1130 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1131 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1132 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1133 } 1134 1135 // AND to memory 1136 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1137 1138 // Block AND. 1139 let mayLoad = 1, mayStore = 1 in 1140 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1141} 1142defm : RMWIByte<and, bdaddr12pair, NI>; 1143defm : RMWIByte<and, bdaddr20pair, NIY>; 1144 1145//===----------------------------------------------------------------------===// 1146// OR 1147//===----------------------------------------------------------------------===// 1148 1149let Defs = [CC] in { 1150 // ORs of a register. 1151 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1152 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1153 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1154 } 1155 1156 // ORs of a 16-bit immediate, leaving other bits unaffected. 1157 // The CC result only reflects the 16-bit field, not the full register. 1158 // 1159 // OIxMux expands to OI[LH]x, depending on the choice of register. 1160 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1161 Requires<[FeatureHighWord]>; 1162 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1163 Requires<[FeatureHighWord]>; 1164 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1165 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1166 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1167 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1168 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1169 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1170 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1171 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1172 1173 // ORs of a 32-bit immediate, leaving other bits unaffected. 1174 // The CC result only reflects the 32-bit field, which means we can 1175 // use it as a zero indicator for i32 operations but not otherwise. 1176 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1177 // Expands to OILF or OIHF, depending on the choice of register. 1178 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1179 Requires<[FeatureHighWord]>; 1180 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1181 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1182 } 1183 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1184 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1185 1186 // ORs of memory. 1187 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1188 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1189 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1190 } 1191 1192 // OR to memory 1193 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1194 1195 // Block OR. 1196 let mayLoad = 1, mayStore = 1 in 1197 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1198} 1199defm : RMWIByte<or, bdaddr12pair, OI>; 1200defm : RMWIByte<or, bdaddr20pair, OIY>; 1201 1202//===----------------------------------------------------------------------===// 1203// XOR 1204//===----------------------------------------------------------------------===// 1205 1206let Defs = [CC] in { 1207 // XORs of a register. 1208 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1209 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1210 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1211 } 1212 1213 // XORs of a 32-bit immediate, leaving other bits unaffected. 1214 // The CC result only reflects the 32-bit field, which means we can 1215 // use it as a zero indicator for i32 operations but not otherwise. 1216 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1217 // Expands to XILF or XIHF, depending on the choice of register. 1218 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1219 Requires<[FeatureHighWord]>; 1220 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1221 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1222 } 1223 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1224 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1225 1226 // XORs of memory. 1227 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1228 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1229 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1230 } 1231 1232 // XOR to memory 1233 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1234 1235 // Block XOR. 1236 let mayLoad = 1, mayStore = 1 in 1237 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1238} 1239defm : RMWIByte<xor, bdaddr12pair, XI>; 1240defm : RMWIByte<xor, bdaddr20pair, XIY>; 1241 1242//===----------------------------------------------------------------------===// 1243// Multiplication 1244//===----------------------------------------------------------------------===// 1245 1246// Multiplication of a register, setting the condition code. We prefer these 1247// over MS(G)R if available, even though we cannot use the condition code, 1248// since they are three-operand instructions. 1249let Predicates = [FeatureMiscellaneousExtensions2], 1250 Defs = [CC], isCommutable = 1 in { 1251 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1252 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1253} 1254 1255// Multiplication of a register. 1256let isCommutable = 1 in { 1257 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1258 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1259} 1260def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1261defm : SXB<mul, GR64, MSGFR>; 1262 1263// Multiplication of a signed 16-bit immediate. 1264def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1265def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1266 1267// Multiplication of a signed 32-bit immediate. 1268def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1269def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1270 1271// Multiplication of memory. 1272defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1273defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1274def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1275 Requires<[FeatureMiscellaneousExtensions2]>; 1276def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1277def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1278 1279// Multiplication of memory, setting the condition code. 1280let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1281 def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; 1282 def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; 1283} 1284 1285// Multiplication of a register, producing two results. 1286def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1287def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1288 Requires<[FeatureMiscellaneousExtensions2]>; 1289def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1290def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1291 1292def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1293 (MGRK GR64:$src1, GR64:$src2)>; 1294def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1295 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1296 1297// Multiplication of memory, producing two results. 1298def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1299def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1300def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1301 Requires<[FeatureMiscellaneousExtensions2]>; 1302def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1303def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1304 1305def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1306 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1307def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1308 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1309 1310//===----------------------------------------------------------------------===// 1311// Division and remainder 1312//===----------------------------------------------------------------------===// 1313 1314let hasSideEffects = 1 in { // Do not speculatively execute. 1315 // Division and remainder, from registers. 1316 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1317 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1318 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1319 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1320 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1321 1322 // Division and remainder, from memory. 1323 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1324 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1325 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1326 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1327 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1328} 1329def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1330 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1331def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1332 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1333def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1334 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1335def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1336 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1337 1338def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1339 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1340 subreg_l32)), GR32:$src2)>; 1341def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1342 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1343 subreg_l32)), bdxaddr20only:$src2)>; 1344def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1345 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1346def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1347 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1348 1349//===----------------------------------------------------------------------===// 1350// Shifts 1351//===----------------------------------------------------------------------===// 1352 1353// Logical shift left. 1354defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1355def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1356def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1357 1358// Arithmetic shift left. 1359let Defs = [CC] in { 1360 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1361 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1362 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1363} 1364 1365// Logical shift right. 1366defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1367def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1368def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1369 1370// Arithmetic shift right. 1371let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1372 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1373 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1374 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1375} 1376 1377// Rotate left. 1378def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1379def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1380 1381// Rotate second operand left and inserted selected bits into first operand. 1382// These can act like 32-bit operands provided that the constant start and 1383// end bits (operands 2 and 3) are in the range [32, 64). 1384let Defs = [CC] in { 1385 let isCodeGenOnly = 1 in 1386 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1387 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1388 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1389} 1390 1391// On zEC12 we have a variant of RISBG that does not set CC. 1392let Predicates = [FeatureMiscellaneousExtensions] in 1393 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1394 1395// Forms of RISBG that only affect one word of the destination register. 1396// They do not set CC. 1397let Predicates = [FeatureHighWord] in { 1398 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1399 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1400 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1401 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1402 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1403 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1404 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1405} 1406 1407// Rotate second operand left and perform a logical operation with selected 1408// bits of the first operand. The CC result only describes the selected bits, 1409// so isn't useful for a full comparison against zero. 1410let Defs = [CC] in { 1411 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1412 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1413 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1414} 1415 1416//===----------------------------------------------------------------------===// 1417// Comparison 1418//===----------------------------------------------------------------------===// 1419 1420// Signed comparisons. We put these before the unsigned comparisons because 1421// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1422// of the unsigned forms do. 1423let Defs = [CC], CCValues = 0xE in { 1424 // Comparison with a register. 1425 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1426 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1427 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1428 1429 // Comparison with a high register. 1430 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1431 Requires<[FeatureHighWord]>; 1432 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1433 Requires<[FeatureHighWord]>; 1434 1435 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1436 // depending on the choice of register. 1437 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1438 Requires<[FeatureHighWord]>; 1439 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1440 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1441 1442 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1443 // depending on the choice of register. 1444 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1445 Requires<[FeatureHighWord]>; 1446 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1447 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1448 Requires<[FeatureHighWord]>; 1449 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1450 1451 // Comparison with memory. 1452 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1453 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1454 Requires<[FeatureHighWord]>; 1455 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1456 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1457 Requires<[FeatureHighWord]>; 1458 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1459 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1460 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1461 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1462 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1463 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1464 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1465 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1466 1467 // Comparison between memory and a signed 16-bit immediate. 1468 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1469 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1470 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1471} 1472defm : SXB<z_scmp, GR64, CGFR>; 1473 1474// Unsigned comparisons. 1475let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1476 // Comparison with a register. 1477 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1478 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1479 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1480 1481 // Comparison with a high register. 1482 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1483 Requires<[FeatureHighWord]>; 1484 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1485 Requires<[FeatureHighWord]>; 1486 1487 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1488 // or CLIH, depending on the choice of register. 1489 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1490 Requires<[FeatureHighWord]>; 1491 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1492 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1493 Requires<[FeatureHighWord]>; 1494 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1495 1496 // Comparison with memory. 1497 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1498 Requires<[FeatureHighWord]>; 1499 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1500 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1501 Requires<[FeatureHighWord]>; 1502 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1503 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1504 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1505 aligned_azextloadi16>; 1506 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1507 aligned_load>; 1508 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1509 aligned_azextloadi16>; 1510 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1511 aligned_azextloadi32>; 1512 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1513 aligned_load>; 1514 1515 // Comparison between memory and an unsigned 8-bit immediate. 1516 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1517 1518 // Comparison between memory and an unsigned 16-bit immediate. 1519 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1520 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1521 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1522} 1523defm : ZXB<z_ucmp, GR64, CLGFR>; 1524 1525// Memory-to-memory comparison. 1526let mayLoad = 1, Defs = [CC] in { 1527 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1528 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1529 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1530 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1531} 1532 1533// String comparison. 1534let mayLoad = 1, Defs = [CC] in 1535 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1536 1537// Test under mask. 1538let Defs = [CC] in { 1539 // TMxMux expands to TM[LH]x, depending on the choice of register. 1540 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1541 Requires<[FeatureHighWord]>; 1542 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1543 Requires<[FeatureHighWord]>; 1544 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1545 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1546 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1547 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1548 1549 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1550 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1551 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1552 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1553 1554 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1555} 1556 1557def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1558def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1559 1560// Compare logical characters under mask -- not (yet) used for codegen. 1561let Defs = [CC] in { 1562 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1563 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1564} 1565 1566//===----------------------------------------------------------------------===// 1567// Prefetch and execution hint 1568//===----------------------------------------------------------------------===// 1569 1570let mayLoad = 1, mayStore = 1 in { 1571 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1572 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1573} 1574 1575let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1576 // Branch Prediction Preload 1577 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1578 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1579 1580 // Next Instruction Access Intent 1581 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1582} 1583 1584//===----------------------------------------------------------------------===// 1585// Atomic operations 1586//===----------------------------------------------------------------------===// 1587 1588// A serialization instruction that acts as a barrier for all memory 1589// accesses, which expands to "bcr 14, 0". 1590let hasSideEffects = 1 in 1591def Serialize : Alias<2, (outs), (ins), []>; 1592 1593// A pseudo instruction that serves as a compiler barrier. 1594let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1595def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1596 1597let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1598 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1599 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1600 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1601 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1602 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1603 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1604 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1605 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1606 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1607 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1608} 1609 1610def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1611def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1612def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1613 1614def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1615def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1616let Predicates = [FeatureNoInterlockedAccess1] in { 1617 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1618 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1619 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1620 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1621 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1622 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1623} 1624 1625def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1626def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1627def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1628 1629def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1630def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1631let Predicates = [FeatureNoInterlockedAccess1] in { 1632 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1633 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1634 imm32ll16c>; 1635 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1636 imm32lh16c>; 1637 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1638 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1639 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1640 imm64ll16c>; 1641 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1642 imm64lh16c>; 1643 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1644 imm64hl16c>; 1645 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1646 imm64hh16c>; 1647 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1648 imm64lf32c>; 1649 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1650 imm64hf32c>; 1651} 1652 1653def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1654def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1655let Predicates = [FeatureNoInterlockedAccess1] in { 1656 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1657 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1658 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1659 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1660 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1661 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1662 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1663 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1664 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1665 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1666 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1667} 1668 1669def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1670def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1671let Predicates = [FeatureNoInterlockedAccess1] in { 1672 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1673 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1674 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1675 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1676 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1677} 1678 1679def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1680def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1681 imm32lh16c>; 1682def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1683def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1684 imm32ll16c>; 1685def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1686 imm32lh16c>; 1687def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1688def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1689def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1690 imm64ll16c>; 1691def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1692 imm64lh16c>; 1693def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1694 imm64hl16c>; 1695def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1696 imm64hh16c>; 1697def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1698 imm64lf32c>; 1699def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1700 imm64hf32c>; 1701 1702def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1703def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1704def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1705 1706def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1707def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1708def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1709 1710def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1711def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1712def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1713 1714def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1715def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1716def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1717 1718def ATOMIC_CMP_SWAPW 1719 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1720 ADDR32:$bitshift, ADDR32:$negbitshift, 1721 uimm32:$bitsize), 1722 [(set GR32:$dst, 1723 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1724 ADDR32:$bitshift, ADDR32:$negbitshift, 1725 uimm32:$bitsize))]> { 1726 let Defs = [CC]; 1727 let mayLoad = 1; 1728 let mayStore = 1; 1729 let usesCustomInserter = 1; 1730 let hasNoSchedulingInfo = 1; 1731} 1732 1733// Test and set. 1734let mayLoad = 1, Defs = [CC] in 1735 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1736 1737// Compare and swap. 1738let Defs = [CC] in { 1739 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1740 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1741} 1742 1743// Compare double and swap. 1744let Defs = [CC] in { 1745 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1746 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1747} 1748 1749// Compare and swap and store. 1750let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1751 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1752 1753// Perform locked operation. 1754let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1755 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1756 1757// Load/store pair from/to quadword. 1758def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1759def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1760 1761// Load pair disjoint. 1762let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1763 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1764 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1765} 1766 1767//===----------------------------------------------------------------------===// 1768// Translate and convert 1769//===----------------------------------------------------------------------===// 1770 1771let mayLoad = 1, mayStore = 1 in 1772 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1773 1774let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1775 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1776 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1777} 1778 1779let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1780 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1781 1782let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1783 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1784 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1785} 1786 1787let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1788 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1789 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1790 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1791 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1792} 1793 1794let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1795 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1796 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1797 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1798 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1799 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1800 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1801 1802 let isAsmParserOnly = 1 in { 1803 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1804 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1805 } 1806} 1807 1808//===----------------------------------------------------------------------===// 1809// Message-security assist 1810//===----------------------------------------------------------------------===// 1811 1812let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1813 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1814 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1815 1816 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1817 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1818 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1819 1820 let Predicates = [FeatureMessageSecurityAssist4] in { 1821 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1822 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1823 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1824 GR128, GR128, GR128>; 1825 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1826 } 1827 1828 let Predicates = [FeatureMessageSecurityAssist5] in 1829 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1830 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1831 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1832 1833 let Predicates = [FeatureMessageSecurityAssist8] in 1834 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1835 GR128, GR128, GR128>; 1836} 1837 1838//===----------------------------------------------------------------------===// 1839// Guarded storage 1840//===----------------------------------------------------------------------===// 1841 1842// These instructions use and/or modify the guarded storage control 1843// registers, which we do not otherwise model, so they should have 1844// hasSideEffects. 1845let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1846 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1847 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1848 1849 let mayLoad = 1 in 1850 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1851 let mayStore = 1 in 1852 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1853} 1854 1855//===----------------------------------------------------------------------===// 1856// Decimal arithmetic 1857//===----------------------------------------------------------------------===// 1858 1859defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1860def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1861 1862defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1863def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1864 1865let mayLoad = 1, mayStore = 1 in { 1866 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1867 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1868 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1869 1870 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1871 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1872 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1873 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1874 let Defs = [CC] in { 1875 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1876 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1877 } 1878} 1879 1880let mayLoad = 1, mayStore = 1 in { 1881 let Defs = [CC] in { 1882 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1883 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1884 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1885 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1886 } 1887 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1888 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1889 let Defs = [CC] in { 1890 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1891 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1892 } 1893} 1894 1895let Defs = [CC] in { 1896 def CP : CompareSSb<"cp", 0xF9>; 1897 def TP : TestRSL<"tp", 0xEBC0>; 1898} 1899 1900//===----------------------------------------------------------------------===// 1901// Access registers 1902//===----------------------------------------------------------------------===// 1903 1904// Read a 32-bit access register into a GR32. As with all GR32 operations, 1905// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1906// when a 64-bit address is stored in a pair of access registers. 1907def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1908 1909// Set access register. 1910def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1911 1912// Copy access register. 1913def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1914 1915// Load address extended. 1916defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1917 1918// Load access multiple. 1919defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1920 1921// Store access multiple. 1922defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1923 1924//===----------------------------------------------------------------------===// 1925// Program mask and addressing mode 1926//===----------------------------------------------------------------------===// 1927 1928// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1929let Uses = [CC] in 1930 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1931 1932// Set CC and program mask from a register. 1933let hasSideEffects = 1, Defs = [CC] in 1934 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1935 1936// Branch and link - like BAS, but also extracts CC and program mask. 1937let isCall = 1, Uses = [CC], Defs = [CC] in { 1938 def BAL : CallRX<"bal", 0x45>; 1939 def BALR : CallRR<"balr", 0x05>; 1940} 1941 1942// Test addressing mode. 1943let Defs = [CC] in 1944 def TAM : SideEffectInherentE<"tam", 0x010B>; 1945 1946// Set addressing mode. 1947let hasSideEffects = 1 in { 1948 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1949 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1950 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1951} 1952 1953// Branch and set mode. Not really a call, but also sets an output register. 1954let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1955 def BSM : CallRR<"bsm", 0x0B>; 1956 1957// Branch and save and set mode. 1958let isCall = 1, Defs = [CC] in 1959 def BASSM : CallRR<"bassm", 0x0C>; 1960 1961//===----------------------------------------------------------------------===// 1962// Transactional execution 1963//===----------------------------------------------------------------------===// 1964 1965let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1966 // Transaction Begin 1967 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1968 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1969 let hasNoSchedulingInfo = 1 in 1970 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1971 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1972 int_s390_tbeginc, imm32zx16>; 1973 } 1974 1975 // Transaction End 1976 let Defs = [CC] in 1977 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 1978 1979 // Transaction Abort 1980 let isTerminator = 1, isBarrier = 1, mayStore = 1, 1981 hasSideEffects = 1 in 1982 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1983 1984 // Nontransactional Store 1985 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1986 1987 // Extract Transaction Nesting Depth 1988 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1989} 1990 1991//===----------------------------------------------------------------------===// 1992// Processor assist 1993//===----------------------------------------------------------------------===// 1994 1995let Predicates = [FeatureProcessorAssist] in { 1996 let hasSideEffects = 1 in 1997 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1998 def : Pat<(int_s390_ppa_txassist GR32:$src), 1999 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2000 0, 1)>; 2001} 2002 2003//===----------------------------------------------------------------------===// 2004// Miscellaneous Instructions. 2005//===----------------------------------------------------------------------===// 2006 2007// Find leftmost one, AKA count leading zeros. The instruction actually 2008// returns a pair of GR64s, the first giving the number of leading zeros 2009// and the second giving a copy of the source with the leftmost one bit 2010// cleared. We only use the first result here. 2011let Defs = [CC] in 2012 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2013def : Pat<(ctlz GR64:$src), 2014 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2015 2016// Population count. Counts bits set per byte. 2017let Predicates = [FeaturePopulationCount], Defs = [CC] in 2018 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2019 2020// Search a block of memory for a character. 2021let mayLoad = 1, Defs = [CC] in 2022 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2023let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2024 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2025 2026// Compare until substring equal. 2027let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2028 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2029 2030// Compare and form codeword. 2031let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2032 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2033 2034// Update tree. 2035let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2036 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2037 def UPT : SideEffectInherentE<"upt", 0x0102>; 2038 2039// Checksum. 2040let mayLoad = 1, Defs = [CC] in 2041 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2042 2043// Compression call. 2044let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2045 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2046 2047// Execute. 2048let hasSideEffects = 1 in { 2049 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2050 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2051} 2052 2053//===----------------------------------------------------------------------===// 2054// .insn directive instructions 2055//===----------------------------------------------------------------------===// 2056 2057let isCodeGenOnly = 1, hasSideEffects = 1 in { 2058 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2059 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2060 imm32sx16:$I2), 2061 ".insn ri,$enc,$R1,$I2", []>; 2062 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2063 AnyReg:$R3, brtarget16:$I2), 2064 ".insn rie,$enc,$R1,$R3,$I2", []>; 2065 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2066 brtarget32:$I2), 2067 ".insn ril,$enc,$R1,$I2", []>; 2068 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2069 uimm32:$I2), 2070 ".insn rilu,$enc,$R1,$I2", []>; 2071 def InsnRIS : DirectiveInsnRIS<(outs), 2072 (ins imm64zx48:$enc, AnyReg:$R1, 2073 imm32sx8:$I2, imm32zx4:$M3, 2074 bdaddr12only:$BD4), 2075 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2076 def InsnRR : DirectiveInsnRR<(outs), 2077 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2078 ".insn rr,$enc,$R1,$R2", []>; 2079 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2080 AnyReg:$R1, AnyReg:$R2), 2081 ".insn rre,$enc,$R1,$R2", []>; 2082 def InsnRRF : DirectiveInsnRRF<(outs), 2083 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2084 AnyReg:$R3, imm32zx4:$M4), 2085 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2086 def InsnRRS : DirectiveInsnRRS<(outs), 2087 (ins imm64zx48:$enc, AnyReg:$R1, 2088 AnyReg:$R2, imm32zx4:$M3, 2089 bdaddr12only:$BD4), 2090 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2091 def InsnRS : DirectiveInsnRS<(outs), 2092 (ins imm64zx32:$enc, AnyReg:$R1, 2093 AnyReg:$R3, bdaddr12only:$BD2), 2094 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2095 def InsnRSE : DirectiveInsnRSE<(outs), 2096 (ins imm64zx48:$enc, AnyReg:$R1, 2097 AnyReg:$R3, bdaddr12only:$BD2), 2098 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2099 def InsnRSI : DirectiveInsnRSI<(outs), 2100 (ins imm64zx48:$enc, AnyReg:$R1, 2101 AnyReg:$R3, brtarget16:$RI2), 2102 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2103 def InsnRSY : DirectiveInsnRSY<(outs), 2104 (ins imm64zx48:$enc, AnyReg:$R1, 2105 AnyReg:$R3, bdaddr20only:$BD2), 2106 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2107 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2108 bdxaddr12only:$XBD2), 2109 ".insn rx,$enc,$R1,$XBD2", []>; 2110 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2111 bdxaddr12only:$XBD2), 2112 ".insn rxe,$enc,$R1,$XBD2", []>; 2113 def InsnRXF : DirectiveInsnRXF<(outs), 2114 (ins imm64zx48:$enc, AnyReg:$R1, 2115 AnyReg:$R3, bdxaddr12only:$XBD2), 2116 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2117 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2118 bdxaddr20only:$XBD2), 2119 ".insn rxy,$enc,$R1,$XBD2", []>; 2120 def InsnS : DirectiveInsnS<(outs), 2121 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2122 ".insn s,$enc,$BD2", []>; 2123 def InsnSI : DirectiveInsnSI<(outs), 2124 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2125 imm32sx8:$I2), 2126 ".insn si,$enc,$BD1,$I2", []>; 2127 def InsnSIY : DirectiveInsnSIY<(outs), 2128 (ins imm64zx48:$enc, 2129 bdaddr20only:$BD1, imm32zx8:$I2), 2130 ".insn siy,$enc,$BD1,$I2", []>; 2131 def InsnSIL : DirectiveInsnSIL<(outs), 2132 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2133 imm32zx16:$I2), 2134 ".insn sil,$enc,$BD1,$I2", []>; 2135 def InsnSS : DirectiveInsnSS<(outs), 2136 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2137 bdaddr12only:$BD2, AnyReg:$R3), 2138 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2139 def InsnSSE : DirectiveInsnSSE<(outs), 2140 (ins imm64zx48:$enc, 2141 bdaddr12only:$BD1,bdaddr12only:$BD2), 2142 ".insn sse,$enc,$BD1,$BD2", []>; 2143 def InsnSSF : DirectiveInsnSSF<(outs), 2144 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2145 bdaddr12only:$BD2, AnyReg:$R3), 2146 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2147} 2148 2149//===----------------------------------------------------------------------===// 2150// Peepholes. 2151//===----------------------------------------------------------------------===// 2152 2153// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2154// equivalent to (and (xor x, -1), y) 2155def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2156 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2157 2158// Shift/rotate instructions only use the last 6 bits of the second operand 2159// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2160// last 16 bits. 2161// Complexity is added so that we match this before we match NILF on the AND 2162// operation alone. 2163let AddedComplexity = 4 in { 2164 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2165 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2166 2167 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2168 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2169 2170 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2171 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2172 2173 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2174 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2175 2176 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2177 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2178 2179 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2180 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2181 2182 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2183 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2184 2185 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2186 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2187} 2188 2189// Peepholes for turning scalar operations into block operations. 2190defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2191 XCSequence, 1>; 2192defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2193 XCSequence, 2>; 2194defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2195 XCSequence, 4>; 2196defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2197 OCSequence, XCSequence, 1>; 2198defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2199 XCSequence, 2>; 2200defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2201 XCSequence, 4>; 2202defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2203 XCSequence, 8>; 2204