xref: /dpdk/drivers/common/cnxk/hw/sdp.h (revision fa8f86a1) 
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef __SDP_HW_H_
6 #define __SDP_HW_H_
7 
8 /* SDP VF IOQs */
9 #define SDP_MIN_RINGS_PER_VF (1)
10 #define SDP_MAX_RINGS_PER_VF (8)
11 
12 /* SDP VF IQ configuration */
13 #define SDP_VF_MAX_IQ_DESCRIPTORS (512)
14 #define SDP_VF_MIN_IQ_DESCRIPTORS (128)
15 
16 #define SDP_VF_DB_MIN	      (1)
17 #define SDP_VF_DB_TIMEOUT     (1)
18 #define SDP_VF_INTR_THRESHOLD (0xFFFFFFFF)
19 
20 #define SDP_VF_64BYTE_INSTR (64)
21 #define SDP_VF_32BYTE_INSTR (32)
22 
23 /* SDP VF OQ configuration */
24 #define SDP_VF_MAX_OQ_DESCRIPTORS (512)
25 #define SDP_VF_MIN_OQ_DESCRIPTORS (128)
26 #define SDP_VF_OQ_BUF_SIZE	  (2048)
27 #define SDP_VF_OQ_REFIL_THRESHOLD (16)
28 
29 #define SDP_VF_OQ_INFOPTR_MODE (1)
30 #define SDP_VF_OQ_BUFPTR_MODE  (0)
31 
32 #define SDP_VF_OQ_INTR_PKT   (1)
33 #define SDP_VF_OQ_INTR_TIME  (10)
34 #define SDP_VF_CFG_IO_QUEUES SDP_MAX_RINGS_PER_VF
35 
36 /* Wait time in milliseconds for FLR */
37 #define SDP_VF_PCI_FLR_WAIT    (100)
38 #define SDP_VF_BUSY_LOOP_COUNT (10000)
39 
40 #define SDP_VF_MAX_IO_QUEUES SDP_MAX_RINGS_PER_VF
41 #define SDP_VF_MIN_IO_QUEUES SDP_MIN_RINGS_PER_VF
42 
43 /* SDP VF IOQs per rawdev */
44 #define SDP_VF_MAX_IOQS_PER_RAWDEV     SDP_VF_MAX_IO_QUEUES
45 #define SDP_VF_DEFAULT_IOQS_PER_RAWDEV SDP_VF_MIN_IO_QUEUES
46 
47 /* SDP VF Register definitions */
48 #define SDP_VF_RING_OFFSET (0x1ull << 17)
49 
50 /* SDP VF IQ Registers */
51 #define SDP_VF_R_IN_CONTROL_START     (0x10000)
52 #define SDP_VF_R_IN_ENABLE_START      (0x10010)
53 #define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)
54 #define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)
55 #define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)
56 #define SDP_VF_R_IN_CNTS_START	      (0x10050)
57 #define SDP_VF_R_IN_INT_LEVELS_START  (0x10060)
58 #define SDP_VF_R_IN_PKT_CNT_START     (0x10080)
59 #define SDP_VF_R_IN_BYTE_CNT_START    (0x10090)
60 
61 #define SDP_VF_R_IN_CONTROL(ring)                                              \
62 	(SDP_VF_R_IN_CONTROL_START + (SDP_VF_RING_OFFSET * (ring)))
63 
64 #define SDP_VF_R_IN_ENABLE(ring)                                               \
65 	(SDP_VF_R_IN_ENABLE_START + (SDP_VF_RING_OFFSET * (ring)))
66 
67 #define SDP_VF_R_IN_INSTR_BADDR(ring)                                          \
68 	(SDP_VF_R_IN_INSTR_BADDR_START + (SDP_VF_RING_OFFSET * (ring)))
69 
70 #define SDP_VF_R_IN_INSTR_RSIZE(ring)                                          \
71 	(SDP_VF_R_IN_INSTR_RSIZE_START + (SDP_VF_RING_OFFSET * (ring)))
72 
73 #define SDP_VF_R_IN_INSTR_DBELL(ring)                                          \
74 	(SDP_VF_R_IN_INSTR_DBELL_START + (SDP_VF_RING_OFFSET * (ring)))
75 
76 #define SDP_VF_R_IN_CNTS(ring)                                                 \
77 	(SDP_VF_R_IN_CNTS_START + (SDP_VF_RING_OFFSET * (ring)))
78 
79 #define SDP_VF_R_IN_INT_LEVELS(ring)                                           \
80 	(SDP_VF_R_IN_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring)))
81 
82 #define SDP_VF_R_IN_PKT_CNT(ring)                                              \
83 	(SDP_VF_R_IN_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
84 
85 #define SDP_VF_R_IN_BYTE_CNT(ring)                                             \
86 	(SDP_VF_R_IN_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
87 
88 /* SDP VF IQ Masks */
89 #define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)
90 #define SDP_VF_R_IN_CTL_RPVF_POS  (48)
91 
92 #define SDP_VF_R_IN_CTL_IDLE   (0x1ull << 28)
93 #define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
94 #define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)
95 #define SDP_VF_R_IN_CTL_D_NSR  (0x1ull << 8)
96 #define SDP_VF_R_IN_CTL_D_ESR  (0x1ull << 6)
97 #define SDP_VF_R_IN_CTL_D_ROR  (0x1ull << 5)
98 #define SDP_VF_R_IN_CTL_NSR    (0x1ull << 3)
99 #define SDP_VF_R_IN_CTL_ESR    (0x1ull << 1)
100 #define SDP_VF_R_IN_CTL_ROR    (0x1ull << 0)
101 
102 #define SDP_VF_R_IN_CTL_MASK (SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B)
103 
104 /* SDP VF OQ Registers */
105 #define SDP_VF_R_OUT_CNTS_START	       (0x10100)
106 #define SDP_VF_R_OUT_INT_LEVELS_START  (0x10110)
107 #define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)
108 #define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)
109 #define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)
110 #define SDP_VF_R_OUT_CONTROL_START     (0x10150)
111 #define SDP_VF_R_OUT_ENABLE_START      (0x10160)
112 #define SDP_VF_R_OUT_PKT_CNT_START     (0x10180)
113 #define SDP_VF_R_OUT_BYTE_CNT_START    (0x10190)
114 
115 #define SDP_VF_R_OUT_CONTROL(ring)                                             \
116 	(SDP_VF_R_OUT_CONTROL_START + (SDP_VF_RING_OFFSET * (ring)))
117 
118 #define SDP_VF_R_OUT_ENABLE(ring)                                              \
119 	(SDP_VF_R_OUT_ENABLE_START + (SDP_VF_RING_OFFSET * (ring)))
120 
121 #define SDP_VF_R_OUT_SLIST_BADDR(ring)                                         \
122 	(SDP_VF_R_OUT_SLIST_BADDR_START + (SDP_VF_RING_OFFSET * (ring)))
123 
124 #define SDP_VF_R_OUT_SLIST_RSIZE(ring)                                         \
125 	(SDP_VF_R_OUT_SLIST_RSIZE_START + (SDP_VF_RING_OFFSET * (ring)))
126 
127 #define SDP_VF_R_OUT_SLIST_DBELL(ring)                                         \
128 	(SDP_VF_R_OUT_SLIST_DBELL_START + (SDP_VF_RING_OFFSET * (ring)))
129 
130 #define SDP_VF_R_OUT_CNTS(ring)                                                \
131 	(SDP_VF_R_OUT_CNTS_START + (SDP_VF_RING_OFFSET * (ring)))
132 
133 #define SDP_VF_R_OUT_INT_LEVELS(ring)                                          \
134 	(SDP_VF_R_OUT_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring)))
135 
136 #define SDP_VF_R_OUT_PKT_CNT(ring)                                             \
137 	(SDP_VF_R_OUT_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
138 
139 #define SDP_VF_R_OUT_BYTE_CNT(ring)                                            \
140 	(SDP_VF_R_OUT_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
141 
142 /* SDP VF OQ Masks */
143 #define SDP_VF_R_OUT_CTL_IDLE  (1ull << 40)
144 #define SDP_VF_R_OUT_CTL_ES_I  (1ull << 34)
145 #define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)
146 #define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)
147 #define SDP_VF_R_OUT_CTL_ES_D  (1ull << 30)
148 #define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)
149 #define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)
150 #define SDP_VF_R_OUT_CTL_ES_P  (1ull << 26)
151 #define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)
152 #define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)
153 #define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)
154 
155 #define SDP_VF_R_OUT_INT_LEVELS_BMODE (1ull << 63)
156 #define SDP_VF_R_OUT_INT_LEVELS_TIMET (32)
157 
158 /* SDP Instruction Header */
159 struct sdp_instr_ih {
160 	/* Data Len */
161 	uint64_t tlen : 16;
162 
163 	/* Reserved1 */
164 	uint64_t rsvd1 : 20;
165 
166 	/* PKIND for SDP */
167 	uint64_t pkind : 6;
168 
169 	/* Front Data size */
170 	uint64_t fsz : 6;
171 
172 	/* No. of entries in gather list */
173 	uint64_t gsz : 14;
174 
175 	/* Gather indicator */
176 	uint64_t gather : 1;
177 
178 	/* Reserved2 */
179 	uint64_t rsvd2 : 1;
180 } __plt_packed;
181 
182 #endif /* __SDP_HW_H_  */
183