1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that RISCV uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 17 18 #include "RISCV.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 namespace RISCVISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 RET_FLAG, 28 URET_FLAG, 29 SRET_FLAG, 30 MRET_FLAG, 31 CALL, 32 SELECT_CC, 33 BuildPairF64, 34 SplitF64, 35 TAIL 36 }; 37 } 38 39 class RISCVTargetLowering : public TargetLowering { 40 const RISCVSubtarget &Subtarget; 41 42 public: 43 explicit RISCVTargetLowering(const TargetMachine &TM, 44 const RISCVSubtarget &STI); 45 46 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 47 MachineFunction &MF, 48 unsigned Intrinsic) const override; 49 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 50 unsigned AS, 51 Instruction *I = nullptr) const override; 52 bool isLegalICmpImmediate(int64_t Imm) const override; 53 bool isLegalAddImmediate(int64_t Imm) const override; 54 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 55 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 56 bool isZExtFree(SDValue Val, EVT VT2) const override; 57 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 58 59 // Provide custom lowering hooks for some operations. 60 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 61 62 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 63 64 // This method returns the name of a target specific DAG node. 65 const char *getTargetNodeName(unsigned Opcode) const override; 66 67 std::pair<unsigned, const TargetRegisterClass *> 68 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 69 StringRef Constraint, MVT VT) const override; 70 71 MachineBasicBlock * 72 EmitInstrWithCustomInserter(MachineInstr &MI, 73 MachineBasicBlock *BB) const override; 74 75 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 76 EVT VT) const override; 77 shouldInsertFencesForAtomic(const Instruction * I)78 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 79 return isa<LoadInst>(I) || isa<StoreInst>(I); 80 } 81 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 82 AtomicOrdering Ord) const override; 83 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 84 AtomicOrdering Ord) const override; 85 86 private: 87 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 88 const SmallVectorImpl<ISD::InputArg> &Ins, 89 bool IsRet) const; 90 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 91 const SmallVectorImpl<ISD::OutputArg> &Outs, 92 bool IsRet, CallLoweringInfo *CLI) const; 93 // Lower incoming arguments, copy physregs into vregs 94 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 95 bool IsVarArg, 96 const SmallVectorImpl<ISD::InputArg> &Ins, 97 const SDLoc &DL, SelectionDAG &DAG, 98 SmallVectorImpl<SDValue> &InVals) const override; 99 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 100 bool IsVarArg, 101 const SmallVectorImpl<ISD::OutputArg> &Outs, 102 LLVMContext &Context) const override; 103 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 104 const SmallVectorImpl<ISD::OutputArg> &Outs, 105 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 106 SelectionDAG &DAG) const override; 107 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 108 SmallVectorImpl<SDValue> &InVals) const override; shouldConvertConstantLoadToIntImm(const APInt & Imm,Type * Ty)109 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 110 Type *Ty) const override { 111 return true; 112 } 113 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 114 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 115 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 116 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 117 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 118 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 119 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 120 121 bool IsEligibleForTailCallOptimization(CCState &CCInfo, 122 CallLoweringInfo &CLI, MachineFunction &MF, 123 const SmallVector<CCValAssign, 16> &ArgLocs) const; 124 125 TargetLowering::AtomicExpansionKind 126 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 127 virtual Value *emitMaskedAtomicRMWIntrinsic( 128 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, 129 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override; 130 TargetLowering::AtomicExpansionKind 131 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 132 virtual Value * 133 emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, 134 Value *AlignedAddr, Value *CmpVal, 135 Value *NewVal, Value *Mask, 136 AtomicOrdering Ord) const override; 137 }; 138 } 139 140 #endif 141