1 //===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into
10 // separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of
11 // which define GPR3.  A copy is added from GPR3 to the target virtual
12 // register of the original instruction.  The GETtlsADDR[32] is really
13 // a call instruction, so its target register is constrained to be GPR3.
14 // This is not true of ADDItls[gd]L[32], but there is a legacy linker
15 // optimization bug that requires the target register of the addi of
16 // a local- or general-dynamic TLS access sequence to be GPR3.
17 //
18 // This is done in a late pass so that TLS variable accesses can be
19 // fully commoned by MachineCSE.
20 //
21 //===----------------------------------------------------------------------===//
22 
23 #include "PPC.h"
24 #include "PPCInstrBuilder.h"
25 #include "PPCInstrInfo.h"
26 #include "PPCTargetMachine.h"
27 #include "llvm/CodeGen/LiveIntervals.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/InitializePasses.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "ppc-tls-dynamic-call"
37 
38 namespace {
39   struct PPCTLSDynamicCall : public MachineFunctionPass {
40     static char ID;
PPCTLSDynamicCall__anon545074a20111::PPCTLSDynamicCall41     PPCTLSDynamicCall() : MachineFunctionPass(ID) {
42       initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry());
43     }
44 
45     const PPCInstrInfo *TII;
46 
47 protected:
processBlock__anon545074a20111::PPCTLSDynamicCall48     bool processBlock(MachineBasicBlock &MBB) {
49       bool Changed = false;
50       bool NeedFence = true;
51       bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
52       bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI();
53       bool IsPCREL = false;
54 
55       for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
56            I != IE;) {
57         MachineInstr &MI = *I;
58         IsPCREL = isPCREL(MI);
59         // There are a number of slight differences in code generation
60         // when we call .__get_tpointer (32-bit AIX TLS).
61         bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX;
62 
63         if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
64             MI.getOpcode() != PPC::ADDItlsldLADDR &&
65             MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
66             MI.getOpcode() != PPC::ADDItlsldLADDR32 &&
67             MI.getOpcode() != PPC::TLSGDAIX &&
68             MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL) {
69           // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
70           // as scheduling fences, we skip creating fences if we already
71           // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
72           // which causes verification error with -verify-machineinstrs.
73           if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
74             NeedFence = false;
75           else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
76             NeedFence = true;
77 
78           ++I;
79           continue;
80         }
81 
82         LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n    " << MI);
83 
84         Register OutReg = MI.getOperand(0).getReg();
85         Register InReg = PPC::NoRegister;
86         Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
87         Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4;
88         if (!IsPCREL && !IsTLSTPRelMI)
89           InReg = MI.getOperand(1).getReg();
90         DebugLoc DL = MI.getDebugLoc();
91 
92         unsigned Opc1, Opc2;
93         switch (MI.getOpcode()) {
94         default:
95           llvm_unreachable("Opcode inconsistency error");
96         case PPC::ADDItlsgdLADDR:
97           Opc1 = PPC::ADDItlsgdL;
98           Opc2 = PPC::GETtlsADDR;
99           break;
100         case PPC::ADDItlsldLADDR:
101           Opc1 = PPC::ADDItlsldL;
102           Opc2 = PPC::GETtlsldADDR;
103           break;
104         case PPC::ADDItlsgdLADDR32:
105           Opc1 = PPC::ADDItlsgdL32;
106           Opc2 = PPC::GETtlsADDR32;
107           break;
108         case PPC::ADDItlsldLADDR32:
109           Opc1 = PPC::ADDItlsldL32;
110           Opc2 = PPC::GETtlsldADDR32;
111           break;
112         case PPC::TLSGDAIX8:
113           // TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only
114           // set Opc2 here.
115           Opc2 = PPC::GETtlsADDR64AIX;
116           break;
117         case PPC::TLSGDAIX:
118           // TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only
119           // set Opc2 here.
120           Opc2 = PPC::GETtlsADDR32AIX;
121           break;
122         case PPC::GETtlsTpointer32AIX:
123           // GETtlsTpointer32AIX is expanded to a call to GET_TPOINTER on AIX
124           // 32-bit mode within PPCAsmPrinter. This instruction does not need
125           // to change, so Opc2 is set to the same instruction opcode.
126           Opc2 = PPC::GETtlsTpointer32AIX;
127           break;
128         case PPC::PADDI8pc:
129           assert(IsPCREL && "Expecting General/Local Dynamic PCRel");
130           Opc1 = PPC::PADDI8pc;
131           Opc2 = MI.getOperand(2).getTargetFlags() ==
132                          PPCII::MO_GOT_TLSGD_PCREL_FLAG
133                      ? PPC::GETtlsADDRPCREL
134                      : PPC::GETtlsldADDRPCREL;
135         }
136 
137         // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
138         // as scheduling fence to avoid it is scheduled before
139         // mflr in the prologue and the address in LR is clobbered (PR25839).
140         // We don't really need to save data to the stack - the clobbered
141         // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
142         // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
143         if (NeedFence)
144           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
145                                                               .addImm(0);
146 
147         if (IsAIX) {
148           // The variable offset and region handle are copied in r4 and r3. The
149           // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
150           if (!IsTLSTPRelMI) {
151             BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
152                 .addReg(MI.getOperand(1).getReg());
153             BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
154                 .addReg(MI.getOperand(2).getReg());
155             BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
156           } else
157             // The opcode of GETtlsTpointer32AIX does not change, because later
158             // this instruction will be expanded into a call to .__get_tpointer,
159             // which will return the thread pointer into r3.
160             BuildMI(MBB, I, DL, TII->get(Opc2), GPR3);
161         } else {
162           MachineInstr *Addi;
163           if (IsPCREL) {
164             Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
165           } else {
166             // Expand into two ops built prior to the existing instruction.
167             assert(InReg != PPC::NoRegister && "Operand must be a register");
168             Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
169           }
170 
171           Addi->addOperand(MI.getOperand(2));
172 
173           MachineInstr *Call =
174               (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3));
175           if (IsPCREL)
176             Call->addOperand(MI.getOperand(2));
177           else
178             Call->addOperand(MI.getOperand(3));
179         }
180         if (NeedFence)
181           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
182 
183         BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
184           .addReg(GPR3);
185 
186         // Move past the original instruction and remove it.
187         ++I;
188         MI.removeFromParent();
189 
190         Changed = true;
191       }
192 
193       return Changed;
194     }
195 
196 public:
isPCREL__anon545074a20111::PPCTLSDynamicCall197   bool isPCREL(const MachineInstr &MI) {
198     return (MI.getOpcode() == PPC::PADDI8pc) &&
199            (MI.getOperand(2).getTargetFlags() ==
200                 PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
201             MI.getOperand(2).getTargetFlags() ==
202                 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
203   }
204 
runOnMachineFunction__anon545074a20111::PPCTLSDynamicCall205     bool runOnMachineFunction(MachineFunction &MF) override {
206       TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
207 
208       bool Changed = false;
209 
210       for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
211         if (processBlock(B))
212           Changed = true;
213 
214       return Changed;
215     }
216 
getAnalysisUsage__anon545074a20111::PPCTLSDynamicCall217     void getAnalysisUsage(AnalysisUsage &AU) const override {
218       AU.addRequired<LiveIntervals>();
219       AU.addRequired<SlotIndexes>();
220       MachineFunctionPass::getAnalysisUsage(AU);
221     }
222   };
223 }
224 
225 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
226                       "PowerPC TLS Dynamic Call Fixup", false, false)
227 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
228 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
229 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE,
230                     "PowerPC TLS Dynamic Call Fixup", false, false)
231 
232 char PPCTLSDynamicCall::ID = 0;
233 FunctionPass*
createPPCTLSDynamicCallPass()234 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }
235